Quality-Driven SystemC Design



Authors

Daniel Große,
Rolf Drechsler


ISBN 978-90-481-3630-8


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For further information on the book and an overview of the contents the preface is also online available at Springer in pdf-format.



Book Summary:

Faced with the steadily increasing complexity and rapidly shortening time-to-market requirements designing electronic systems is a very challenging task. To manage this situation effectively the level of abstraction in modeling has been raised during the past years in the computer aided design community. Meanwhile, for the so-called system-level design the system description language SystemC has become the de facto standard. However, while modeling from abstract to synthesizable descriptions in combination with specification concepts like Transaction Level Modeling (TLM) leads to very good results, the verification quality is poor. The two main reasons are that (1) the existing SystemC verification techniques do not escort the different abstraction levels effectively and (2) in particular the resulting quality in terms of the covered functionality is only checked manually. Hence, due to the increasing design complexity the number of undetected errors is growing rapidly.

Therefore a quality-driven design and verification flow for digital systems is developed and presented in this book. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction. Second, each verification technique is complemented by an approach to measure the achieved verification quality. The new flow distinguishes three levels of abstraction (namely system level, top level and block level) and can be incorporated in existing approaches. After reviewing the preliminary concepts, in the following chapters the three levels for modeling and verification are considered in detail. At each level the verification quality is measured. In summary, following the new design and verification flow a high overall quality results.




Authors:

Dr. Daniel Große

Daniel Große received the Diploma degree in computer science from Albert Ludwigs University, Freiburg, Germany, in 2002 and the Dr. degree from the University of Bremen, Bremen, Germany, in 2008. He is currently with the Computer Architecture Research Group, University of Bremen. His research interests include verification, logic synthesis, and high-level languages like SystemC.

Prof. Dr. Rolf Drechsler

Rolf Drechsler received his diploma and Dr. phil. nat. degree in computer science from the J.W. Goethe-University in Frankfurt am Main, Germany, in 1992 and 1995, respectively. He was with the Institute of Computer Science at the Albert-Ludwigs-University of Freiburg im Breisgau, Germany from 1995 to 2000. He joined the Corporate Technology Department of Siemens AG, Munich in 2000, where he worked as a Senior Engineer in the formal verification group. Since October 2001 he has been with the University of Bremen, Germany, where he is now a full professor for computer architecture. His research interests include data structures logic synthesis, test, and verification.










UNIVERSITY OF BREMEN GROUP OF COMPUTER ARCHITEKTURE CONTACT - PROF. DR. R. DRECHSLER