entity myDFF is port (clk, d, rst, set:in bit; output:out bit); end entity myDFF; architecture DFF_arch of myDFF is begin ff:process(clk,rst,set) is begin if(rst='1') then output <='0'; elsif (set='1') then output <='1'; elsif (clk='1' and clk'event)then output <=d; end if; end process ff; end architecture Dff_arch; entity Counter8 is port (clk, rst:in bit; output: out bit_vector(0 to 7)) ; end entity Counter8; architecture c8_arch of Counter8 is signal intern:bit_vector(0 to 7); signal invintern:bit_vector(0 to 7); begin d0:entity work.myDFF(DFF_arch) port map(clk, (invintern(0)),rst,'0',intern(0)); invintern(0)<=not intern(0); genlable: for i in 1 to 7 generate ff:entity work.myDFF(DFF_arch) port map(invintern(i-1), (invintern(i)),rst,'0',intern(i)); invintern(i)<=not intern(i); end generate genlable; output<=intern; end architecture c8_arch; entity Segment7 is port (wert:in bit_vector( 0 to 3); zahl:out bit_vector( 0 to 6 )); end entity Segment7; architecture s7_arch of Segment7 is begin umrechnen:process(wert) begin case wert is when "0000" => zahl <= NOT "1111110"; when "1000" => zahl <= NOT "0110000"; when "0100" => zahl <= NOT "1101101"; when "1100" => zahl <= NOT "1111001"; when "0010" => zahl <= NOT "0110011"; when "1010" => zahl <= NOT "1011011"; when "0110" => zahl <= NOT "1011111"; when "1110" => zahl <= NOT "1110000"; when "0001" => zahl <= NOT "1111111"; when "1001" => zahl <= NOT "1111011"; when "0101" => zahl <= NOT "1110111"; when "1101" => zahl <= NOT "0011111"; when "0011" => zahl <= NOT "1001110"; when "1011" => zahl <= NOT "0111101"; when "0111" => zahl <= NOT "1001111"; when "1111" => zahl <= NOT "1000111"; end case; end process umrechnen; end architecture s7_arch; entity Aufgabe1 is port (sparsepin,rstpin: in bit; z0,z1: out bit_vector(0 to 6)); end entity Aufgabe1; architecture a1_arch of Aufgabe1 is signal cout:bit_vector(0 to 7); begin count:entity work.Counter8(c8_arch) port map(not sparsepin, not rstpin,cout); zahl0:entity work.Segment7(s7_arch) port map(cout(0 to 3),z0); zahl1:entity work.Segment7(s7_arch) port map(cout(4 to 7),z1); end architecture a1_arch; --für die Defintion vom Taktgenerator benötigt library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity osc4 is port ( F8M, F500K, F16K, F490, F15 : out std_ulogic); end osc4; --15Hz passt nicht zu 100ms architecture osc4_F16K of osc4 is constant CLOCK_PERIOD: time := 62 us; --korrekt wäre 62,5 aber fürs modell reicht es aus begin -- Not Syntethisable -- CLOCK_GENERATION: process -- begin -- -- F16K <= '0'; -- wait for CLOCK_PERIOD/2; -- F16K <= '1'; -- wait for CLOCK_PERIOD/2; -- end process; end osc4_F16K; --für die Defintion vom Taktgenerator benötigt library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; --gleiches Interface wie Aufgabe1 entity Aufgabe2 is port (sparsepin,rstpin: in bit; z0,z1: out bit_vector(0 to 6)); end entity Aufgabe2; --der komplizierte Weg zählen mit 2 Countern architecture a2_arch of Aufgabe2 is signal internSparse:bit; signal clk:std_ulogic; signal zahl:bit_vector(0 to 15); signal internClk:bit; --for the time counter begin aufgabe1Module:entity work.Aufgabe1(a1_arch) port map(internSparse, rstpin,z0,z1); zahl0:entity work.osc4(osc4_F16K) port map( F8M => open, F500K =>open, F16K => clk, F490 => open, F15 => open ); countLow:entity work.Counter8(c8_arch) port map(internClk, not sparsepin,zahl(0 to 7)); countHigh:entity work.Counter8(c8_arch) port map(not zahl(7), not sparsepin,zahl(8 to 15)); internClkGen:process(clk) begin if( (zahl(15)= '1') or(zahl = "0000001001100000")) then -- counter starts with "11111111" --do nothing --umwandeln von ulogic nach bit elsif(clk='1') then internClk<='1'; else internClk<='0'; end if; end process internClkGen; internSparseGen:process(clk,sparsepin) begin if (zahl = "0000000000000000")then internsparse<='1'; elsif (sparsepin'event and sparsepin='0')then if(zahl = "00000010001100000") then internsparse<='0'; end if; end if; end process internsparseGen; end architecture a2_arch; --Die einfache Variante mit Integer architecture a2_arch2 of Aufgabe2 is signal internSparse:bit; signal clk:std_ulogic; signal zahl:integer; begin aufgabe1Module:entity work.Aufgabe1(a1_arch) port map(internSparse, rstpin,z0,z1); zahl0:entity work.osc4(osc4_F16K) port map( F8M => open, F500K =>open, F16K => clk, F490 => open, F15 => open ); countTime:process(clk,sparsepin) begin if(sparsepin='0')then zahl<=0; elsif(clk'event and clk='1')then if(zahl < 1600)then zahl<= zahl+1; end if; end if; end process countTime; genInternSparse:process(clk,sparsepin) begin if(zahl=0) then internsparse<='1'; elsif (sparsepin'event and sparsepin='0')then if(zahl >=1600) then internsparse<='0'; end if; end if; end process genInternSparse; end architecture a2_arch2;