With increasing complexity of VLSI circuits, the costs for the test phase have risen dramatically. So testability issues have to be considered from the very beginning of the design process to control the test costs and to guarantee the testability of the circuit at the end of the manufacturing process.

In the past, my research interests focussed on the development of efficient algorithms and data structures for logic synthesis and simulation-based verification of circuits and systems. I think that there is still much work to do, as the problems arising here often are real "brainteasers". For the future, I plan to consider evolutionary (i.e., genetic) algorithms or search methods as known from Artificial Intelligence.

In the group I working on solving of SAT-problems and their applications in praxis. I am especially interested in the classes maxSAT and max weighted SAT.

I am since February 2006 a secretary in the AG computer architecture. To my tasks organizational and administrative technical activities belong.

I'm mostly concerned with the development of evolutionary algorithms, especially for electronic circuit design. Learning and working together to find better solutions for hard problems is fun.

Before I had this dream job, some time went into my now rather neglected private home page.

I am doing research in Circuits and Systems Design and Verification.

During my studies of Computer Science I did researches on binary decision diagrams. Nowadays I am working in the area of formal verification and validation.

My main interests are in full search space exploration with techniques known from circuit design, using word level information for circuit verification and fault ordering heuristics for ATPG.

My primary research interests are in the area of on-chip bus architecture synthesis, synthesis for robustness, and low power design. The main aim is to develop algorithms, which address the future SoC design challenges.

I work at the Fraunhofer Institute for Integrated Circuits, Division Design Automation and strengthen the group from Dresden. My interests mainly lie, faithfully the slogan of the Fraunhofer Gesellschaft, in the application oriented research. Here some must be done in order to successfully use theoretical procedures and experimental methods in industrial practice. In this field I deal with static and dynamic analysis to assure the quality of circuits as well as to support formal verification.

I am a almost-one year postdoctoral researcher. My research interest is in the application of formal methods for the verification of SoC. More precisely, I study the link between a model, its design and its specification. My works aim at alleviating the model checking for a given component. On the other hand, I work on an abstraction method that builds a component abstraction directly from its specification. This research plans to verify a composed component in the framework of the counter-example guided abstraction refinement (CEGAR).
homepage: www-asim.lip6.fr/~cecile

My research is in the area of Logic Synthesis. In the last years the focus has been on the synthesis and minimization of reversible logic functions. Reversible logic plays a significant role in the design of emerging quantum computers.

I work as a PhD student in the group of Computer Architecture. My research interests include Evolutionary Algorithms (EA) and Multi-Objective Optimization (MOO). The main focus is the optimization of the process of circuit design. For this purpose, I plan to apply EAs and MOO to VLSI CAD problems, e.g. targeting applications in HW-SW-codesign and co-simulation.

I am visiting the computer architecture group until March 31, 2009 while on sabbatical leave from the University of Victoria, Canada where I am a Professor of Computer Science. My research interests include: logic design of reversible and quantum circuits, decision diagrams, multiple-valued logic and spectral logic. My UVic web page is located at www.cs.uvic.ca/~mmiller