With increasing complexity of VLSI circuits, the costs for the test phase have risen dramatically. So testability issues have to be considered from the very beginning of the design process to control the test costs and to guarantee the testability of the circuit at the end of the manufacturing process.

In the past, my research interests focussed on the development of efficient algorithms and data structures for logic synthesis and simulation-based verification of circuits and systems. I think that there is still much work to do, as the problems arising here often are real "brainteasers". For the future, I plan to consider evolutionary (i.e., genetic) algorithms or search methods as known from Artificial Intelligence.

In the group I working on solving of SAT-problems and their applications in praxis. I am especially interested in the classes maxSAT and max weighted SAT.

I am since February 2006 a secretary in the AG computer architecture. To my tasks organizational and administrative technical activities belong.

I'm mostly concerned with the development of evolutionary algorithms, especially for electronic circuit design. Learning and working together to find better solutions for hard problems is fun.

Before I had this dream job, some time went into my now rather neglected private home page.

I am doing research in Circuits and Systems Design and Verification.

I am working as lecturer and research assistent in the area of evolutionary algorithms and applications. The considered approaches are mainly taken from the world of digital circuit design.

publications

My primary research interests are in the area of on-chip bus architecture synthesis, synthesis for robustness, and low power design. The main aim is to develop algorithms, which address the future SoC design challenges.

I am a almost-one year postdoctoral researcher. My research interest is in the application of formal methods for the verification of SoC. More precisely, I study the link between a model, its design and its specification. My works aim at alleviating the model checking for a given component. On the other hand, I work on an abstraction method that builds a component abstraction directly from its specification. This research plans to verify a composed component in the framework of the counter-example guided abstraction refinement (CEGAR).
homepage: www-asim.lip6.fr/~cecile

My research is in the area of Logic Synthesis. In the last years the focus has been on the synthesis and minimization of reversible logic functions. Reversible logic plays a significant role in the design of emerging quantum computers.

I work as a PhD student in the group of Computer Architecture. My research interests include Evolutionary Algorithms (EA) and Multi-Objective Optimization (MOO). The main focus is the optimization of the process of circuit design. For this purpose, I plan to apply EAs and MOO to VLSI CAD problems, e.g. targeting applications in HW-SW-codesign and co-simulation.