In general I am interested in topics of Human-Computer Interaction (HCI) as the creation of user interfaces, the development of novel interaction techniques, their implementation and evaluation. In the working group I am concentrating on the development of a user-friendly debugging interface.

My research interest is formal verification of circuits. The goal of formal verification is to prove the correctness of circuits (in contrast to simulation based approaches whose limitations were highlighted e.g. by the Pentium Bug).
Especially, I examine how information of high-level descriptions can be used effectively in the formal verification process. Thereby the system description language SystemC plays an important role.

The focus of my research is automation in debugging and diagnosis of reliable systems. Formal verification and semi-formal methods are studied in this area.

Until now I was interested in heuristic and exact optimization procedures in logic synthesis. Actually my research interests are focused on analyzing and debugging of circuits.

My research is about robustness check of digital circuits with use of formal methods. The features sizes in VLSI circuits shrinking continuously. Thus, circuits becoming more and more vulnerable against transient faults. The currently developed methods of robustness verification have to be improved for real-world applications.

In my work I integrate contextual knowledge into system-level verification. This is done by using and extending word-level solvers and combining them with current verification approaches.

The main focus of my research activities is the analysis of description languages for hardware/software design. Major questions are how such hybrid systems can be visualized and what technical prerequisites need to be satisfied for this purpose.

My activities enclose the general support in business and managerial issues. Within these activities I focus on entrepreneurship and marketing.

My main focus lies on the one hand in research and there specially in the technical documentation and formal specification from circuits and systems on the other hand in care of courses and seminars in basic and main studies.

My main focus lies in the research of „testing for reversible circuits“. In particular, I am working on ATPG for reversible circuits.

My scope is the timing analysis of digital circuits with the focus on the efficient identification of false paths or the generation of stimuli for specific paths, respectively.
In particular, I investigate and develop approaches based on formal methods. These methods promise a high degree of robustness which is very important for practical use.

My principally research interests cover the subject areas of revesible circuits, logic synthesis and the Boolean satisfiability problem (SAT).

My role in the the work-group is about developing techniques for design-space exploration and visualization. These techniques are priory used in hardware-software co-design, to develop integrated environments which optimize the VLSI-CAD.

In the past, my research interest has been SAT-Solving. Now, at the group of computer architecture, I mainly focus on Automatic Test Pattern Generation. Goal is to combine these two techniques.

My research interest is the application of constraint programming techniques, such as arc-consistency, in the area of SMT-solving. In particular, I am trying to combine bit vector logic with the SAT problem.

During my studies of Computer Science I did researches on binary decision diagrams. Nowadays I am working in the area of formal verification and validation.

My main interests are in full search space exploration with techniques known from circuit design, using word level information for circuit verification and fault ordering heuristics for ATPG.

I work at the Fraunhofer Institute for Integrated Circuits, Division Design Automation and strengthen the group from Dresden. My interests mainly lie, faithfully the slogan of the Fraunhofer Gesellschaft, in the application oriented research. Here some must be done in order to successfully use theoretical procedures and experimental methods in industrial practice. In this field I deal with static and dynamic analysis to assure the quality of circuits as well as to support formal verification.

I am since February 2006 a secretary in the AG computer architecture. To my tasks organizational and administrative technical activities belong.

I am a almost-one year postdoctoral researcher. My research interest is in the application of formal methods for the verification of SoC. More precisely, I study the link between a model, its design and its specification. My works aim at alleviating the model checking for a given component. On the other hand, I work on an abstraction method that builds a component abstraction directly from its specification. This research plans to verify a composed component in the framework of the counter-example guided abstraction refinement (CEGAR).
homepage: www-asim.lip6.fr/~cecile

My primary research interests are in the area of on-chip bus architecture synthesis, synthesis for robustness, and low power design. The main aim is to develop algorithms, which address the future SoC design challenges.

With increasing complexity of VLSI circuits, the costs for the test phase have risen dramatically. So testability issues have to be considered from the very beginning of the design process to control the test costs and to guarantee the testability of the circuit at the end of the manufacturing process.

In the past, my research interests focussed on the development of efficient algorithms and data structures for logic synthesis and simulation-based verification of circuits and systems. I think that there is still much work to do, as the problems arising here often are real "brainteasers". For the future, I plan to consider evolutionary (i.e., genetic) algorithms or search methods as known from Artificial Intelligence.

In the group I working on solving of SAT-problems and their applications in praxis. I am especially interested in the classes maxSAT and max weighted SAT.

I'm mostly concerned with the development of evolutionary algorithms, especially for electronic circuit design. Learning and working together to find better solutions for hard problems is fun.

Before I had this dream job, some time went into my now rather neglected private home page.

I am doing research in Circuits and Systems Design and Verification.

I am a Professor of ECE at Purdue University, West Lafayette, USA, where I also hold the Roscoe H. George Chair. My research interests include VLSI design/CAD for nano-scale Silicon and non-Silicon technologies, low-power electronics for portable computing and wireless communications, spintronics, and VLSI testing and verification. You can visit my web page for more information.

I work as a PhD student in the group of Computer Architecture. My research interests include Evolutionary Algorithms (EA) and Multi-Objective Optimization (MOO). The main focus is the optimization of the process of circuit design. For this purpose, I plan to apply EAs and MOO to VLSI CAD problems, e.g. targeting applications in HW-SW-codesign and co-simulation.

I am visiting the computer architecture group until March 31, 2009 while on sabbatical leave from the University of Victoria, Canada where I am a Professor of Computer Science. My research interests include: logic design of reversible and quantum circuits, decision diagrams, multiple-valued logic and spectral logic. My UVic web page is located at www.cs.uvic.ca/~mmiller

I am an Associate Professor in the Electrical & computer engineering Department at the Univ. of Utah, USA. My area of interests are in fundamental CAD techniques for Synthesis and Verification of Digital VLSI and post-VLSI systems. I am on sabbatical leave, and spending some time from March - July at the Univ. of Bremen. My current research projects are in Logic & Physical Synthesis of Photonic Logic and also in Application of Computer Algebra Techniques in Design Automation.
For more information, see: http://www.ece.utah.edu/~kalla

My research is in the area of Logic Synthesis. In the last years the focus has been on the synthesis and minimization of reversible logic functions. Reversible logic plays a significant role in the design of emerging quantum computers.

I am a PhD student at Duke University in Durham (North Carolina, USA) in the research group of Prof. Krishnendu Chakrabarty. My current research focuses on design-for-testability and ATPG for integrated circuits, including 3D-stacked ICs.

I am a Professor of Electrical and Computer Engineering at Duke University, Durham (North Carolina), USA. I am also a Chair Professor of Software Theory at Tsinghua University, Beijing, China for 2009-2012 and a Visiting Chair Professor in Computer Science and Information Engineering at National Cheng Kung University in Taiwan for 2012. My research interests include: testing and design-for-testability of integrated circuits; digital microfluidics, biochips, and cyberphysical systems; optimization of digital print and production system infrastructure . You can visit my web page for more information.
More Information: http://www.ee.duke.edu/~krish/