» Verifying UML/OCL Models Using Boolean Satisfiability
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Author:
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Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler |
| Conference: |
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Design, Automation and Test in Europe (DATE) |
Reference:
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| Dresden, 2010
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Hyperlink:
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| [Link to the Conference]
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» Timing Arc Based Logic Analysis for False Noise Reduction
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Author:
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Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler |
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IEEE/ACM International Conference on Computer Aided Design (ICCAD) |
Reference:
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| San Jose, 2009
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Anwendungsbezogene Analyse der Robustheit von Digitalen Schaltungen
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Author:
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Andre Sülflow, Stefan Frehse, Görschwin Fey, Rolf Drechsler |
| Conference: |
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GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) |
Reference:
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| pp. 45-52, Stuttgart, 2009
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Structural Heuristics for SAT-based ATPG
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Author:
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Daniel Tille, Stephan Eggersglüß, Hoang M. Le, Rolf Drechsler |
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17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2009) |
Reference:
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| Florianópolis, 2009
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Speeding up SAT-based ATPG using Dynamic Clause Activation
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Author:
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Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
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18th Asian Test Symposium (ATS'09) |
Reference:
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| Taichung, 2009
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Deterministc Algorithms for ATPG under Leakage Constraints
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Author:
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Görschwin Fey |
| Conference: |
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18th Asian Test Symposium (ATS'09) |
Reference:
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| Taichung, 2009
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Automatic Debugging of System-on-a-Chip Designs
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Author:
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Frank Rogin, Rolf Drechsler, Steffen Rülke |
| Conference: |
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IEEE International SOC Conference (SOCC) |
Reference:
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| Belfast, 2009
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» SAT-Based ATPG Testing of Inter- and Intra-Gate Bridging Faults
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Author:
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Toru Nakura, Yutaro Tatemura, Görschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada |
| Conference: |
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European Conference on Circuit Theory and Design |
Reference:
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| Antalya, 2009
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» SMT-based Stimuli Generation in the SystemC Verification Library
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Author:
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Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler |
| Conference: |
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Forum on specification & Design Languages (FDL) |
Reference:
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| Sophia Antipolis, 2009
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Robustness Check for Multiple Faults using Formal Techniques
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Author:
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Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler |
| Conference: |
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Euromicro Conference on Digital System Design (DSD) |
Reference:
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| pp. 85-90, Patras, 2009
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Synthesizing Reversible Circuits for Irreversible Functions
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Author:
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D. Michael Miller, Robert Wille, Gerhard W. Dueck |
| Conference: |
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Euromicro Conference on Digital System Design (DSD) |
Reference:
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| pp. 749-756, Patras, 2009
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» BDD-based Synthesis of Reversible Logic for Large Functions
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Author:
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Robert Wille, Rolf Drechsler |
| Conference: |
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Design Automation Conference (DAC) |
Reference:
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| pp. 270-275, San Francisco, 2009
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Computing Bounds for Fault Tolerance using Formal Techniques
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Author:
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Görschwin Fey, Andre Sülflow, Rolf Drechsler |
| Conference: |
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Design Automation Conference (DAC) |
Reference:
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| pp. 190-195, San Francisco, USA, 2009
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Generating an Efficient Instruction Set Simulator from a Complete Property Suite
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Author:
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Ulrich Kühne, Sven Beyer, Christian Pichler |
| Conference: |
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IEEE/IFIP International Symposium on Rapid System Prototyping (RSP) |
Reference:
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| pp. 109-115, Paris, 2009
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» WoLFram - A Word Level Framework for Formal Verification
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Author:
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Andre Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler |
| Conference: |
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IEEE/IFIP International Symposium on Rapid System Prototyping (RSP) |
Reference:
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| pp. 11-17, Paris, 2009
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» A Fast Untestability Proof for SAT-based ATPG
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Author:
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Daniel Tille, Rolf Drechsler |
| Conference: |
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12th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems |
Reference:
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| pp. 38-43, Liberec, 2009
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Increasing Robustness of SAT-based Delay Test Generation using Efficient Dynamic Learning Techniques
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Author:
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Stephan Eggersglüß, Rolf Drechsler |
| Conference: |
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14th IEEE European Test Symposium (ETS) |
Reference:
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| pp. 81-86, Sevilla, 2009
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Contradictory Antecedent Debugging in Bounded Model Checking
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Author:
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Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
| Conference: |
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Great Lakes Symposium on VLSI (GLSVLSI) |
Reference:
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| pp. 173-176, Boston, 2009
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Evaluation of Cardinality Constraints on SMT-based Debugging
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Author:
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Andre Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler |
| Conference: |
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39th International Symposium on Multiple-Valued Logic (ISMVL) |
Reference:
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| pp. 298-303, Naha, Okinawa, 2009
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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» Equivalence Checking of Reversible Circuits
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Author:
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Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler |
| Conference: |
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39th International Symposium on Multiple-Valued Logic (ISMVL) |
Reference:
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| pp. 324-330, Naha, Okinawa, 2009
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Hyperlink:
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| [Link to the Conference]
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PDF:
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| [click here]
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