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» Ensuring Safety and Reliability of IP-based System Design – A Container Approach




Author:

Arun Chandrasekharan, Kenneth Schmitz, Ulrich Kühne, Rolf Drechsler
Conference:
IEEE International Symposium on Rapid System Protoyping (RSP), 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Verification of the Decimal Floating-Point Square Root Operation,




Author:

Amr Sayed Ahmed, Hossam Fahmy, Ulrich Kühne
Conference:
19th IEEE European Test Symposium,
Reference:

Paderborn, Germany, 2014.
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Hybrid Algorithm to Conservatively Check the Robustness of Circuits




Author:

Niels Thole, Lorena Anghel, Görschwin Fey
Conference:
IEEE European Test Symposium (ETS)
Reference:

Amsterdam, Niederlande, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» SAT-Based Post-Processing for Regional Capture Power Reduction in At-Speed Scan Test Generation




Author:

Stephan Eggersglüß, Kohei Miyase, Xiaoqing Wen
Conference:
IEEE European Test Symposium (ETS)
Reference:

Amsterdam, Niederlande, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers




Author:

Sebastian Huhn, Stephan Eggersglüß and Rolf Drechsler
Conference:
IEEE European Test Symposium (ETS)
Reference:

Amsterdam, Niederlande, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Unified Formulation of Behavioral Semantics for SysML Models




Author:

Christoph Hilken, Jan Peleska, Robert Wille
Conference:
International Conference on Model-Driven Engineering and Software Development
Reference:

Angers, France, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» SAT-Based ATPG Testing of Inter- and Intra-Gate Bridging Faults




Author:

Toru Nakura, Yutaro Tatemura, Görschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada
Conference:
European Conference on Circuit Theory and Design
Reference:

Antalya, 2009



» Determining Cases of Scenarios to Improve Coverage in Simulation-based Verication




Author:

Shuo Yang, Robert Wille, Rolf Drechsler
Conference:
Symposium on Integrated Circuits and System Design (SBCCI)
Reference:

Aracaju, Brazil, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Self-Verification as the Key Technology for Next Generation Electronic Systems




Author:

Rolf Drechsler, Hoang M. Le, Mathias Soeken
Conference:
Symposium on Integrated Circuits and System Design (SBCCI)
Reference:

Aracaju, Brazil, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Validating SystemC Implementations Against Their Formal Specifications




Author:

Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference:
Symposium on Integrated Circuits and System Design (SBCCI)
Reference:

Aracaju, Brazil, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reverse Engineering with Simulation Graphs




Author:

Mathias Soeken, Baruch Sterin, Rolf Drechsler, Robert K. Brayton
Conference:
Formal Methods in Computer Aided Design (FMCAD)
Reference:

Austin, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A General and Exact Routing Methodology for Digital Microfluidic Biochips




Author:

Oliver Keszöcze, Robert Wille, Krishnendu Chakrabarty Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

Austin, USA, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Formal Methods for Emerging Technologies




Author:

Robert Wille, Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

Austin, USA, 2015
Hyperlink:

[Link to the Conference]



» An MIG-based Compiler for Programmable Logic-in-Memory Architectures




Author:

Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli
Conference:
Design Automation Conference (DAC)
Reference:

Austin, USA, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Approximation-aware Rewriting of AIGs for Error Tolerant Applications




Author:

Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

Austin, USA, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Compiled Symbolic Simulation for SystemC




Author:

Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

Austin, USA, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exact Diagnosis Using Boolean Satisfiability




Author:

Heinz Riener, Görschwin Fey
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

Austin, USA, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Precise Error Determination of Approximated Components in Sequential Circuits with Model Checking




Author:

Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

Austin, USA, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» ProACt: A Processor for High Performance On-demand Approximate Computing




Author:

Arun Chandrasekharan, Daniel Große, Rolf Drechsler
Conference:
27th ACM Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

Banff, Alberta, Canada, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reusing Learned Information in SAT-based ATPG




Author:

Görschwin Fey, Tim Warode, Rolf Drechsler
Conference:
20th International Conference on VLSI Design
Reference:

Bangalore, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Hardware Project Management - What we Can Learn from the Software Development Process for Hardware Design?




Author:

Rolf Drechsler, Andreas Breiter
Conference:
2nd International Conference on Software and Data Technologies
Reference:

Barcelona, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» SyDe - a New Graduate School for System Design in an Excellent Setting




Author:

Ulrich Kühne, Rolf Drechsler
Conference:
Informatics Europe (ECSS)
Reference:

Barcelona, 2012
Hyperlink:

[Link to the Conference]



» Self-practicing of logic circuits through mobile devices: Lecturers' and students' perceptions




Author:

Mazyar Seraj, Cornelia Große, Rolf Drechsler
Conference:
9th annual International Conference on Education and New Learning Technologies (EduLearn17)
Reference:

Barcelona, Spain, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automatic Debugging of System-on-a-Chip Designs




Author:

Frank Rogin, Rolf Drechsler, Steffen Rülke
Conference:
IEEE International SOC Conference (SOCC)
Reference:

Belfast, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Contradiction Analysis for Inconsistent Formal Models




Author:

Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15)
Reference:

Belgrade, Serbia, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Equivalence Checking on System Level using A Priori Knowledge




Author:

Niels Thole, Heinz Riener, Görschwin Fey
Conference:
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15)
Reference:

Belgrade, Serbia, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Requirement Phrasing Assistance using Automatic Quality Assessment




Author:

Arman Allahyari-Abhari, Mathias Soeken, Rolf Drechsler
Conference:
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15)
Reference:

Belgrade, Serbia, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» BDD-based Synthesis for All-optical Mach-Zehnder Interferometer Circuits




Author:

Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Conference:
International Conference on VLSI Design (VLSI Design)
Reference:

Bengaluru, India, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» An Adaptive Prioritized ε-Preferred Evolutionary Algorithm for Approximate BDD Optimization




Author:

Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
Conference:
Genetic and Evolutionary Computation Conference (GECCO)
Reference:

Berlin, Germany, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Semi-Formal Cycle-Accurate Temporal Execution Traces Reconstruction




Author:

Rehab Massoud, Jannis Stoppe, Daniel Große, Rolf Drechsler
Conference:
15th International Conference on Formal Modelling and Analysis of Timed Systems (FORMATS)
Reference:

Berlin, Germany, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Hardware Project Management – What we Can Learn from the Software Development Process for Hardware Design?




Author:

Rolf Drechsler, Andreas Breiter
Conference:
4th Conference of Informatics and Information Technologies
Reference:

Bitola, 2003
Hyperlink:

[Link to the Conference]



» BioViz: An Interactive Visualization Engine for Digital Microfluidic Biochips




Author:

Jannis Stoppe, Oliver Keszöcze, Maximilian Luenert, Robert Wille, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Bochum, Germany, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects




Author:

Tino Flenker, Jan Malburg, Goerschwin Fey, Serhiy Avramenko, Massimo Violante and Matteo Sonza Reorda
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Bochum, Germany, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Enumeration of reversible functions and its application to circuit complexity




Author:

Mathias Soeken, Nabila Abdessaied, Giovanni De Micheli
Conference:
Reversible Computation
Reference:

Bologna, Italy, 2016
Hyperlink:

[Link to the Conference]



» Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs




Author:

Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Bologna, Italy, 2016
Hyperlink:

[Link to the Conference]



» Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata




Author:

Mehran Goli, Jannis Stoppe, Rolf Drechsler
Conference:
35th IEEE International Conference on Computer Design (ICCD)
Reference:

Boston Area, Massachusetts, USA, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Modeling and Formal Verification of Counting Heads for Railways




Author:

Sebastian Kinder, Rolf Drechsler
Conference:
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2007)
Reference:

Braunschweig, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Framework for Quasi-Exact Optimization using Relaxed Best-First Search




Author:

Rüdiger Ebendt, Rolf Drechsler
Conference:
29th Annual German Conference on Artificial Intelligence (KI'06)
Reference:

Bremen, 2006
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Cube Pairing Approach for Synthesis of ESOP based Reversible Circuit




Author:

Chandan Bandyopadhyay, Hafizur Rahaman, Rolf Drechsler
Conference:
44rd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Bremen, 2014
Hyperlink:

[Link to the Conference]



» Envisioning Self-Verification of Electronic Systems




Author:

Rolf Drechsler, Martin Fränzle, Robert Wille
Conference:
Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
Reference:

Bremen, Germany, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Designing Reliable Cyber-Physical Systems




Author:

Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon Ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Bremen, Germany, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Equivalence Checking on ESL Utilizing A Priori Knowledge




Author:

Niels Thole, Heinz Riener, Görschwin Fey
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Bremen, Germany, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-based Error Effect Simulation - A Case Study




Author:

Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Bremen, Germany, 2016
Best Paper Candidate
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Self-Adaptive Evolutionary Many-Objective Optimization based on Relation Epsilon-Preferred




Author:

Nicole Drechsler
Conference:
International Conference on Soft Computing MENDEL
Reference:

Brno, Czech Republic, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Complete and Effective Robustness Checking by Means of Interpolation




Author:

Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav and Rolf Drechsler
Conference:
Formal Methods in Computer-Aided Design (FMCAD'12)
Reference:

Cambridge, UK, 2012, page 82-90
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Machine Learning Based Test Pattern Analysis for Localizing Critical Power Activity Areas




Author:

Harshad Dhotre, Stephan Eggersglüß, Mehdi Dehbashi, Ulrike Pfannkuchen, Rolf Drechsler
Conference:
30th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Reference:

Cambridge, UK, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reconfigurable TAP Controllers with Embedded Compression for Large Test Data Volume




Author:

Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler
Conference:
30th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Reference:

Cambridge, UK, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Unintrusive Aging Analysis based on Offline Learning




Author:

Frank Sill Torres, Pedro F. R. Leite Junior and Rolf Drechsler
Conference:
30th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Reference:

Cambridge, UK, 2017
Hyperlink:

[Link to the Conference]



» Determining the Minimal Number of SWAP Gates for Multi-dimensional Nearest Neighbor Quantum Circuits




Author:

Aaron Lye, Robert Wille, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Chiba/Tokyo, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reverse BDD-based Synthesis for Splitter-free Optical Circuits




Author:

Robert Wille, Oliver Keszöcze, Clemens Hopfmuller, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Chiba/Tokyo, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Enhancing Robustness of Sequential Circuits Using Application-specific Knowledge and Formal Methods




Author:

Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler
Conference:
22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Chiba/Tokyo, Japan, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exact Routing for Micro-Electrode-Dot-Array Digital Microfluidic Biochips




Author:

Oliver Keszöcze, Zipeng Li, Andreas Grimmer, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
Conference:
22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Chiba/Tokyo, Japan, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Property mining using dynamic dependency graphs




Author:

Jan Malburg, Tino Flenker, Goerschwin Fey
Conference:
22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Chiba/Tokyo, Japan, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Trust is good, Control is better: Hardware-based Instruction-Replacement for Reliable Processor-IPs




Author:

Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, Rolf Drechsler
Conference:
22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Chiba/Tokyo, Japan, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Utilizing Don't Care States in SAT-based Bounded Sequential Problems




Author:

Sean Safarpour, Görschwin Fey, Andreas Veneris, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI'05)
Reference:

Chicago, 2005
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Compact Test Set Generation for Test Compression-based Designs




Author:

Stephan Eggersglüß
Conference:
IEEE European Test Symposium (ETS)
Reference:

Cluj-Napoca, Romania, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» The SyReC Hardware Description Language: Enabling Scalable Synthesis of Reversible Circuits




Author:

Robert Wille, Rolf Drechsler
Conference:
International Midwest Symposium on Circuits and Systems (MWSCAS)
Reference:

Columbus, USA, 2013
Hyperlink:

[Link to the Conference]



» Reversible Circuit Rewriting with Simulated Annealing




Author:

Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, and Rolf Drechsler
Conference:
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Reference:

Daejeon, Korea, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Non-Intrusive High-level SystemC Debugging




Author:

Frank Rogin, Erhard Fehlauer, Steffen Ruelke, Sebastian Ohnewald, Thomas Berndt
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Darmstadt, 2006
Hyperlink:

[Link to the Conference]



» Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm




Author:

Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
Conference:
Genetic and Evolutionary Computation Conference (GECCO)
Reference:

Denver, USA, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» An Evolutionary Approach to Reversible Logic Synthesis using Output Permutation




Author:

Kamalika Datta, Indranil Sen Gupta, Hafizur Rahaman, Rolf Drechsler
Conference:
IEEE Design and Test Symposium 2012 (IDT)
Reference:

Doha, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards Dialog Systems for Assisted Natural Language Processing in the Design of Embedded Systems




Author:

Rolf Drechsler, Mathias Soeken, Robert Wille
Conference:
IEEE Design and Test Symposium 2012 (IDT)
Reference:

Doha, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Guiding Coverage Metric for Formal Verification




Author:

Finn Haedicke, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Dresden, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis




Author:

Robert Wille, Rolf Drechsler, Christof Oswald, Alberto Garcia-Ortiz
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Dresden, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exploiting Inherent Characteristics of Reversible Circuits for Faster Combinational Equivalence Checking




Author:

Luca Amaru, Pierre-Emmanuel Gaillardon, Robert Wille, Giovanni De Micheli
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Dresden, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Synthesis of Approximate Coders for On-chip Interconnects Using Reversible Logic




Author:

Robert Wille, Oliver Keszöcze, Stefan Hillmich, Marcel Walter, Alberto Garcia-Ortiz
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Dresden, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Future SoC Verification Methodology: UVM Evolution or Revolution?




Author:

Rolf Drechsler, Christophe Chevallaz, Franco Fummi, Alan Hu, Ronny Morad, Frank Schirrmeister, Alex Goryachev
Conference:
Design, Automation and Test in Europe (DATE'14)
Reference:

Dresden, Germany, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Fast Logic Synthesis for RRAM-based In-Memory Computing using Majority-Inverter Graphs




Author:

Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Dresden, Germany, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Optimizing Majority-Inverter Graphs With Functional Hashing




Author:

Mathias Soeken, Pierre-Emmanuel Gaillardon, Luca Amaru, Giovanni De Micheli
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Dresden, Germany, 2016
Hyperlink:

[Link to the Conference]



» Mapping Abstract and Concrete Hardware Models for Design Understanding




Author:

Tino Flenker, Görschwin Fey
Conference:
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

Dresden, Germany, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Task-Driven Software Summarization




Author:

Dave Binkley, Dawn Lawrie, Emily Hill, Janet Burge, Ian Harris, Regina Hebig, Oliver Keszöcze, Karl Reed, John Slankas
Conference:
29th IEEE International Conference on Software Maintenance (ICSM)
Reference:

Eindhoven, The Netherlands, 2013
Hyperlink:

[Link to the Conference]



» Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables




Author:

Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Goerschwin Fey
Conference:
IEEE Latin-American Test Symposium (LATS2016)
Reference:

Foz do Iguaçu, Brazil, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Leveraging the Analysis for Invariant Independence in Formal System Models




Author:

Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Funchal, Madeira, Portugal, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Verification-driven Design Across Abstraction Levels - A Case Study




Author:

Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Funchal, Madeira, Portugal, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reliability Analysis Reloaded: How Will We Survive?




Author:

Robert Aitken, Görschwin Fey, Zbigniew T. Kalbarczyk, Frank Reichenbach, Matteo Sonza Reorda
Conference:
Design, Automation and Test in Europe (DATE'13)
Reference:

Grenoble, France, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated Feature Localization for Dynamically Generated SystemC Designs




Author:

Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE'15)
Reference:

Grenoble, France, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Ricercar: A Language for Describing and Rewriting Reversible Circuits with Ancillae and its Permutation Semantics




Author:

Michael Kirkedal Thomsen, Mathias Soeken, Robin Kaarsgaard
Conference:
Reversible Computation
Reference:

Grenoble, France, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Technology mapping for quantum circuits using Boolean functional decomposition




Author:

Nabila Abdessaied, Mathias Soeken, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Grenoble, France, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards a Cost Metric for Nearest Neighbor Constraints in Reversible Circuits




Author:

Abhoy Kole, Kamalika Datta, Indranil Sengupta, Robert Wille
Conference:
Reversible Computation
Reference:

Grenoble, France, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards Line-aware Realizations of Expressions for HDL-based Synthesis of Reversible Circuits




Author:

Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Grenoble, France, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automatic Fault Localization for Property Checking




Author:

Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler
Conference:
Haifa Verification Conference
Reference:

Haifa, 2006
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» FoREnSiC - An Automatic Debugging Environment for C Programs




Author:

Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow
Conference:
Haifa Verification Conference (HVC)
Reference:

Haifa, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Hochoptimierter Ablauf zur Robustheitsprüfung




Author:

Stefan Frehse, Finn Haedicke, Melanie Diepenbeck, Görschwin Fey, Rolf Drechsler
Conference:
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)
Reference:

Hamburg-Harburg, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Distributed and Coupled Electrothermal Model of Power Semiconductor Devices




Author:

G. Belkacem, D. Labrousse, S. Lefebvre, P.-Y. Joubert, U. Kühne, L. Fribourg, R. Soulat, E. Florentin, C. Rey
Conference:
International Conference on Renewable Energies and Vehicular Technology
Reference:

Hammamet, 2012
Hyperlink:

[Link to the Conference]



» Revealing Properties of Structural Materials by Combining Regression-based Algorithms and Nano Indentation Measurements




Author:

Sebastian Huhn, Heike Sonnenberg, Stephan Eggersglüß, Brigitte Clausen, Rolf Drechsler
Conference:
10th IEEE Symposium Series on Computational Intelligence (SSCI)
Reference:

Hawaii, USA, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test




Author:

Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen
Conference:
IEEE Asian Test Symposium (ATS)
Reference:

Hiroshima, Japan, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» High-Performance and Lightweight Lattice-Based Public-Key Encryption




Author:

Johannes A. Buchmann, Florian Göpfert, Tim Güneysu, Tobias Oder, Thomas Pöppelmann
Conference:
IoTPTS@AsiaCCS 2016: 2-9
Reference:

http://doi.acm.org/10.1145/2899007.2899011



» Secure architectures of future emerging cryptography SAFEcrypto




Author:

Máire O'Neill, Elizabeth O'Sullivan, Gavin McWilliams, Markku-Juhani Saarinen, Ciara Moore, Ayesha Khalid, James Howe, Rafaël Del Pino, Michel Abdalla, Francesco Regazzoni, Felipe Valencia, Tim Güneysu, Tobias Oder, Adrian Waller, Glyn Jones, Anthony Barnett, Robert Griffin, Andrew Byrne, Bassem Ammar, David Lund
Conference:
Conf. Computing Frontiers 2016: 315-322
Reference:

http://doi.acm.org/10.1145/2903150.2907756



» Standard lattices in hardware




Author:

James Howe, Ciara Moore, Máire O'Neill, Francesco Regazzoni, Tim Güneysu, K. Beeden
Conference:
Design Automation Conference (DAC), Austin, USA, 2016, 162:1-162:6
Reference:

http://doi.acm.org/10.1145/2903150.2907756



» On the Energy Cost of Channel Based Key Agreement




Author:

Christopher Huth, René Guillaume, Paul Duplys, Kumaragurubaran Velmurugan, Tim Güneysu
Conference:
TrustED@CCS 2016: 31-41
Reference:

http://doi.acm.org/10.1145/2995289.2995291



» Robust and One-Pass Parallel Computation of Correlation-Based Attacks at Arbitrary Order




Author:

Tobias Schneider, Amir Moradi, Tim Güneysu
Conference:
COSADE 2016, Graz, p. 199-217
Reference:

http://dx.doi.org/10.1007/978-3-319-43283-0_12



» Secure and Private, yet Lightweight, Authentication for the IoT via PUF and CBKA




Author:

Christopher Huth, Aydin Aysu, Jorge Guajardo, Paul Duplys, Tim Güneysu
Conference:
ICISC 2016: 28-48
Reference:

http://dx.doi.org/10.1007/978-3-319-53177-9_2



» White-Box Cryptography in the Gray Box - A Hardware Implementation and its Side Channels




Author:

Pascal Sasdrich, Amir Moradi, Tim Güneysu
Conference:
FSE 2016: 185-203
Reference:

http://dx.doi.org/10.1007/978-3-662-52993-5_10



» ParTI - Towards Combined Hardware Countermeasures Against Side-Channel and Fault-Injection Attacks




Author:

Tobias Schneider, Amir Moradi, Tim Güneysu
Conference:
CRYPTO (2), Santa Barbara, USA, 2016: 302-332
Reference:

http://dx.doi.org/10.1007/978-3-662-53008-5_11



» Strong 8-bit Sboxes with Efficient Masking in Hardware




Author:

Erik Boss, Vincent Grosso, Tim Güneysu, Gregor Leander, Amir Moradi, Tobias Schneider
Conference:
CHES 2016: 171-193
Reference:

http://dx.doi.org/10.1007/978-3-662-53140-2_9



» A grain in the silicon: SCA-protected AES in less than 30 slices




Author:

Pascal Sasdrich, Tim Güneysu
Conference:
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2016: 25-32
Reference:

http://dx.doi.org/10.1109/ASAP.2016.7760769



» On the problems of realizing reliable and efficient ring oscillator PUFs on FPGAs.




Author:

Alexander Wild, Georg T. Becker, Tim Güneysu
Conference:
Hardware-Oriented Security and Trust (HOST) 2016: 103-108
Reference:

http://dx.doi.org/10.1109/HST.2016.7495565



» An Integrated Approach for Combining BDD and SAT Provers




Author:

Rolf Drechsler, Görschwin Fey, Sebastian Kinder
Conference:
International Conference on VLSI Design
Reference:

Hyderabad, 2006
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Clocks vs. Instants Relations: Verifying CCSL Time Constraints in UML/MARTE Models




Author:

Judith Peters, Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Reference:

Indian Institute of Technology, Kanpur, India, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Frame Conditions in Symbolic Representations of UML/OCL Models




Author:

Nils Przigoda, Jonas Gomes Filho, Philipp Niemann, Robert Wille, Rolf Drechsler
Conference:
14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Reference:

Indian Institute of Technology, Kanpur, India, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exploring Superior Structural Materials Using Multi-Objective Optimization and Formal Techniques




Author:

Rolf Drechsler, Stephan Eggersglüß, Nils Ellendt, Sebastian Huhn, Lutz Mädler
Conference:
6th IEEE International Symposium on Embedded Computing & System Design (ISED)
Reference:

Indian Institute of Technology, Patna, India, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Minimization of Transitions by Complementation and Resequencing using Evolutionary Algorithms




Author:

Rolf Drechsler and Nicole Drechsler
Conference:
21st IASTED International Multi-Conference Applied Informatics (AI 2003)
Reference:

Innsbruck, 2003
Hyperlink:

[Link to the Conference]
PS:

[click here]



» Early SoC Security Validation by VP-based Static Information Flow Analysis




Author:

Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

Irvine, USA, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Coverage-driven Stimuli Generation




Author:

Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler
Conference:
15th Euromicro Conference on Digital System Design (DSD)
Reference:

Izmir, Turkey, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Approximation-aware Testing for Approximate Circuits




Author:

Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große, Rolf Drechsler
Conference:
23rd Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Jeju, Korea, 2018
Hyperlink:

[Link to the Conference]



» Debugging HDL Designs Based on Functional Equivalences with High-Level Specifications




Author:

Alexander Finder, Jan-Philipp Witte, Görschwin Fey
Conference:
16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

Karlovy Vary, Czech Republic, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards a Catalog of Structural and Behavioral Verification Tasks for UML/OCL Models




Author:

Frank Hilken, Philipp Niemann, Martin Gogolla, Robert Wille
Conference:
Modellierung
Reference:

Karlsruhe, Germany, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Hardware/Software Co-Visualization on the Electronic System Level using SystemC




Author:

Rolf Drechsler, Jannis Stoppe
Conference:
International Conference on VLSI Design
Reference:

Kolkata, India, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library




Author:

Laxmidhar Biswal, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Conference:
International Conference on VLSI Design (VLSI Design)
Reference:

Kolkata, India, 2016
Hyperlink:

[Link to the Conference]



» Towards VHDL-based Design of Reversible Circuits




Author:

Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Kolkata, India, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Integrating Observability Don't Cares in All-Solution SAT Solvers




Author:

Sean Safarpour, Andreas Veneris, Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'06)
Reference:

Kos, 2006
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» On the Sensitivity of BDDs with Respect to Path-Related Objective Functions




Author:

Rüdiger Ebendt, Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'06)
Reference:

Kos, 2006
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exploiting Error Detection Latency for Parity-based Soft Error Detection




Author:

Gökçe Aydos, Görschwin Fey
Conference:
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

Košice, Slovakia, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Multi-Objective BDD Optimization for RRAM based Circuit Design




Author:

Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler
Conference:
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'16)
Reference:

Košice, Slovakia, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Mapping NCV Circuits to Optimized Clifford+T Circuits




Author:

D. Michael Miller, Mathias Soeken, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Kyoto, Japan, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Quantum Circuit Optimization by Hadamard Gate Reduction




Author:

Nabila Abdessaied, Mathias Soeken, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Kyoto, Japan, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» RevVis: Visualization of Structures and Properties in Reversible Circuits




Author:

Robert Wille, Jannis Stoppe, Eleonora Schönborn, Kamalika Datta, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Kyoto, Japan, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reversible Computation: An Alternative Computation Paradigm for Low Power Applications




Author:

Rolf Drechsler, Robert Wille
Conference:
International Green and Sustainable Computing Conference (IGSC)
Reference:

Las Vegas, USA, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Optimization of Retargeting for IEEE 1149.1 TAP Controllers with Embedded Compression




Author:

Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Lausanne, Schweiz, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automatic Equivalence Checking for SystemC-TLM 2.0 Models Against their Formal Specifications




Author:

Mehran Goli, Jannis Stoppe, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Data Flow Testing for Virtual Prototypes




Author:

Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Effects of Cell Shapes on the Routability of Digital Microfluidic Biochips




Author:

Kevin Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Endurance Management for Resistive Logic-In-Memory Computing Architectures




Author:

Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Determining Minimal Testsets for Reversible Circuits Using Boolean Satisfiability




Author:

Hongyan Zhang, Stefan Frehse, Robert Wille, Rolf Drechsler
Conference:
10th IEEE Africon
Reference:

Livingstone, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Crossing Reduction by Windows Optimization




Author:

Thomas Eschbach, Wolfgang Günther, Rolf Drechsler and Bernd Becker
Conference:
10th International Symposium on Graph Drawing (GD'2002)
Reference:

LNCS 2528, pp. 285-294, Irvine, 2002
PDF:

[click here]
PS:

[click here]



» Automated Formal Verification of Processors Based on Architectural Models




Author:

Ulrich Kühne, Sven Beyer, Jörg Bormann, John Barstow
Conference:
Formal Methods in Computer Aided Design (FMCAD)
Reference:

Lugano, Switzerland, 2010
Hyperlink:

[Link to the Conference]



» On the Construction of Small Fully Testable Circuits with Low Depth




Author:

Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Architectures, Methods and Tools
Reference:

Lübeck, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Proving Completeness of Properties in Formal Verification of Counting Heads for Railways




Author:

Sebastian Kinder and Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Architectures, Methods and Tools
Reference:

Lübeck, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Coverage of OCL Operation Specifications and Invariants




Author:

Mathias Soeken, Julia Seiter, Rolf Drechsler
Conference:
9th International Conference on Tests & Proofs (TAP)
Reference:

L’Aquila, Italy, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Ein formaler Ansatz zum Robustheitsnachweis




Author:

Görschwin Fey, Rolf Drechsler
Conference:
Zuverlässigkeit und Entwurf
Reference:

München, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Look-ahead Schemes for Nearest Neighbor Optimization of 1D and 2D Quantum Circuits




Author:

Robert Wille, Oliver Keszöcze, Marcel Walter, Patrick Rohrs, Anupam Chattopadhyay, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Macao, China, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Multi-Objective BDD Optimization with Evolutionary Algorithms




Author:

Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler
Conference:
Genetic and Evolutionary Computation Conference (GECCO)
Reference:

Madrid, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Safe IP Integration Using Container Modules




Author:

Rolf Drechsler, Ulrich Kühne
Conference:
International Symposium on Electronic System Design (ISED)
Reference:

Mangalore, India, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Grammar-based Program Generation Based on Model Finding




Author:

Mathias Soeken, Rolf Drechsler
Conference:
IEEE Design and Test Symposium 2013 (IDT)
Reference:

Marrakesch, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Compact and Efficient SAT Encoding for Quantum Circuits




Author:

Robert Wille, Nils Przigoda, Rolf Drechsler
Conference:
IEEE Africon
Reference:

Mauritius, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exploiting Reversibility in the Complete Simulation of Reversible Circuits




Author:

Robert Wille, Simon Stelter, Rolf Drechsler
Conference:
IEEE Africon
Reference:

Mauritius, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Supporting Clinical Guidelines Using DL-Temporal Reasoning




Author:

Serge Autexier, Mohamed Bawadekji, Dieter Hutter, Regine Wolters
Conference:
International Conference & Expo on Emerging Technologies for a Smarter World (CEWIT)
Reference:

Melville, NY, USA, 2013
Hyperlink:

[Link to the Conference]



» Conservatively Analyzing Transient Faults




Author:

Niels Thole, Görschwin Fey, Alberto Garcia-Ortiz
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Montpelier, France, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Equivalence Checking Using Gröbner Bases




Author:

Amr Sayed Ahmed, Daniel Große, Mathias Soeken, Rolf Drechsler
Conference:
Formal Methods in Computer Aided Design (FMCAD)
Reference:

Mountain View, USA, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Diagnostic Tests and Diagnosis for Delay Faults using Path Segmentation




Author:

Tino Flenker, André Sülflow, Görschwin Fey
Conference:
24th IEEE Asian Test Symposium (ATS)
Reference:

Mumbai, India, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automatic Generation of Complex Properties for Hardware Designs




Author:

Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler Steffen Rülke
Conference:
Design, Automation, and Test in Europe (DATE)
Reference:

Munich, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs




Author:

Sujan Pandey, Rolf Drechsler
Conference:
Design, Automation, and Test in Europe (DATE)
Reference:

Munich, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» (Semi-)Automatic Translation of Legal Regulations to Formal Representations: Expanding the Horizon of EDA Applications




Author:

Oliver Keszöcze, Betina Keiner, Matthias Richter, Gottfried Antpöhler, Robert Wille
Conference:
Special Session at the Forum on specification & Design Languages (FDL'14)
Reference:

Munich, Germany, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automatic Refinement Checking for Formal System Models




Author:

Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Munich, Germany, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automating the Translation of Assertions Using Natural Language Processing Techniques




Author:

Mathias Soeken, Christopher B. Harris, Nabila Abdessaied, Ian G. Harris and Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Munich, Germany, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemC




Author:

Hoang M. Le, Rolf Drechsler
Conference:
Design and Verification Conference and Exhibition Europe (DVCon Europe)
Reference:

Munich, Germany, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Quality Assessment for Requirements based on Natural Language Processing




Author:

Mathias Soeken, Nabila Abdessaied, Arman Allahyari-Abhari, Andi Buzo, Liana Musat, Georg Pelz, Rolf Drechsler
Conference:
Special Session at the Forum on Specification & Design Languages (FDL'14)
Reference:

Munich, Germany, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Verifying Consistency between Activity Diagrams and Their Corresponding OCL Contracts




Author:

Christoph Hilken, Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Munich, Germany, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven Generation




Author:

Hoang M. Le, Rolf Drechsler
Conference:
Design and Verification Conference and Exhibition Europe (DVCon Europe)
Reference:

Munich, Germany, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Data Extraction from SystemC Designs using Debug Symbols and the SystemC API




Author:

Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Natal, Brazil, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Improved Fault Diagnosis for Reversible Circuits




Author:

Hongyan Zhang, Robert Wille, Rolf Drechsler
Conference:
Asian Test Symposium (ATS)
Reference:

New Delhi, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Technical Documentation of Software and Hardware in Embedded Systems




Author:

Beate Muranko, Rolf Drechsler
Conference:
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC 2006)
Reference:

Nice, France 2006
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Error Bounded Exact BDD Minimization in Approximate Computing




Author:

Saman Froehlich, Daniel Große, Rolf Drechsler
Conference:
47th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Novi Sad, Serbia, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exact Synthesis of Ternary Reversible Functions using Ternary Toffoli Gates




Author:

Abhoy Kole, P. Mercy Nesa Rani, Kamalika Datta, Indranil Sengupta, Rolf Drechsler
Conference:
47th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Novi Sad, Serbia, 2017
Hyperlink:

[Link to the Conference]



» Extensions to the Reversible Hardware Description Language SyReC




Author:

Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Conference:
47th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Novi Sad, Serbia, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» OR-Inverter Graphs for the Synthesis of Optical Circuits




Author:

Arighna Deb, Robert Wille, Rolf Drechsler
Conference:
47th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Novi Sad, Serbia, 2017
Hyperlink:

[Link to the Conference]



» Synchronized Debugging across Different Abstraction Levels in System Design




Author:

Rolf Drechsler, Daniel Große, Hoang M. Le, André Sülflow
Conference:
embedded world Conference 2013
Reference:

Nürnberg, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Efficient Realization of Control Logic in Reversible Circuits




Author:

Sebastian Offermann, Robert Wille, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Oldenburg, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL




Author:

Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler
Conference:
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07)
Reference:

Oslo, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Experimental Studies on SAT-based ATPG for Gate Delay Faults




Author:

Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Conference:
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07)
Reference:

Oslo, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Empirical Results on Parity-based Soft Error Detection with Software-based Retry




Author:

Gökçe Aydos, Görschwin Fey
Conference:
IEEE Nordic Circuits and Systems Conference (NORCAS)
Reference:

Oslo, Norway, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Checking Concurrent Behavior in UML/OCL Models




Author:

Nils Przigoda, Christoph Hilken, Robert Wille, Jan Peleska, Rolf Drechsler
Conference:
ACM/IEEE 18th International Conference on Model Driven Engineering Languages and Systems (MoDELS)
Reference:

Ottawa, Kanada, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits




Author:

Rolf Drechsler, Junhao Shi and Görschwin Fey
Conference:
IEEE Great Lakes Symposium on VLSI (GLSV'03)
Reference:

p. 80-83, Washington, 2003
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability




Author:

Junhao Shi, Görschwin Fey, Rolf Drechsler
Conference:
Twelfth Asian Test Symposium (ATS03)
Reference:

p.290-293, Xi'an, 2003
Hyperlink:

[Link to the Conference]
PS:

[click here]



» Optimization-based Multiple Target Test Generation for Highly Compacted Test Sets




Author:

Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
Conference:
19th IEEE European Test Symposium (ETS)
Reference:

Paderborn, Germany, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» SAT-Based Speedpath Debugging Using Waveforms




Author:

Mehdi Dehbashi, Görschwin Fey
Conference:
19th IEEE European Test Symposium (ETS)
Reference:

Paderborn, Germany, 2014
Hyperlink:

[Link to the Conference]



» JADE: Implementation and Visualization of a BDD Package in JAVA




Author:

Rolf Drechsler
Conference:
IEEE Design, Automation and Test in Europe (DATE'02) - User Forum
Reference:

page 259, Paris, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» IND-CCA Secure Hybrid Encryption from QC-MDPC Niederreiter




Author:

Ingo von Maurich, Lukas Heberle, Tim Güneysu
Conference:
Post-Quantum Cryptography (PQCrypto 2016)
Reference:

pages 1-17, LNCS Vol. 9606, Fukuoka, Japan
Hyperlink:

[Link to the Conference]



» Secure software update and IP protection for untrusted devices in the Internet of Things via physically unclonable functions




Author:

Christopher Huth, Paul Duplys, Tim Güneysu
Conference:
IEEE International Conference on Pervasive Computing and Communication Workshops (PerCom Workshops)
Reference:

pages 1-6, Sydney, Australia
Hyperlink:

[Link to the Conference]



» Formal Verification on Register Transfer Level - Utilizing High-Level Information for Hardware Verification




Author:

Peer Johannsen and Rolf Drechsler
Conference:
IFIP International Conference on Very Large Scale Integration (VLSI'01)
Reference:

pages 127-132, Montpellier, 2001
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Decision Diagrams Optimization Using Copy Properties




Author:

Dragan Jankovic, Radomir Stankovic and Rolf Drechsler
Conference:
Euromicro Symposium on Digital System Design (DSD'2002)
Reference:

pages 236-243, Dortmund, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» On the Construction of Multi-Valued Decision Diagrams




Author:

Michael Miller and Rolf Drechsler
Conference:
IEEE International Symposium on Multi-Valued Logic (ISMVL'2002)
Reference:

pages 245-253, Boston, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Evaluation of Static Variable Ordering Heuristics for MDD Construction




Author:

Rolf Drechsler
Conference:
IEEE International Symposium on Multi-Valued Logic (ISMVL'2002)
Reference:

pages 254-260, Boston, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Reachability Analysis for Formal Verification of SystemC




Author:

Rolf Drechsler and Daniel Große
Conference:
Euromicro Symposium on Digital System Design (DSD'2002)
Reference:

pages 337-340, Dortmund, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Minimizing the Number of Paths in BDDs




Author:

Görschwin Fey and Rolf Drechsler
Conference:
15th Symposium on Integrated Circuits and System Design
Reference:

pages 359-364, Porto Alegre, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Recursive Bi-Partitioning of Netlists for Large Number of Partitions




Author:

Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard and Gerhard Angst
Conference:
Euromicro Symposium on Digital System Design (DSD'2002)
Reference:

pages 38-44, Dortmund, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» On the Relation Between SAT and BDDs for Equivalence Checking




Author:

Sherif Reda, Rolf Drechsler and Alex Orailoglu
Conference:
International Symposium on Quality of Electronic Design (ISQED 2002)
Reference:

pages 394-399, San Jose, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Fast and Efficient Equivalence Checking based on NAND-BDDs




Author:

Rolf Drechsler and Mitch Thornton
Conference:
IFIP International Conference on Very Large Scale Integration (VLSI'01)
Reference:

pages 401-405, Montpellier, 2001
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Multi-Output Timed Shannon Circuits




Author:

Mitch Thorton, Rolf Drechsler and Michael Miller
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002)
Reference:

pages 47-52, Pittsburgh, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» RTL-Datapath Verification using Integer Linear Programming




Author:

Raik Brinkmann and Rolf Drechsler
Conference:
IEEE VLSI Design'02 & Asia and South Pacific Design Automation Conference
Reference:

pages 741-746, Bangalore, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Efficient Calculation of Fixed-Polarity Polynomial Expressions for Multi-Valued Logic Functions




Author:

Dragan Jankovic, Radomir Stankovic and Rolf Drechsler
Conference:
IEEE International Symposium on Multi-Valued Logic (ISMVL'2002)
Reference:

pages 76-82, Boston, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» IMITATOR 2.5: A Tool for Analyzing Robustness in Scheduling Problems (Tool Paper)




Author:

Étienne André, Laurent Fribourg, Ulrich Kühne, Romain Soulat
Conference:
International Symposium on Formal Methods (FM)
Reference:

Paris, France, 2012
Hyperlink:

[Link to the Conference]



» An Improved Gate Library for Logic Synthesis of Optical Circuits




Author:

Shuchisman Burman, Kamalika Datta, Robert Wille, Indranil Sengupta, Rolf Drechsler
Conference:
International Symposium on Electronic System Design (ISED)
Reference:

Patna, Indien, 2016
Hyperlink:

[Link to the Conference]



» Generating and Checking Control Logic in the HDL-based Design of Reversible Circuits




Author:

Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
Conference:
International Symposium on Electronic System Design (ISED)
Reference:

Patna, Indien, 2016
Hyperlink:

[Link to the Conference]



» Towards a Model-Based Verification Methodology for Complex Swarm Systems




Author:

Jonas Gomes Filho, Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
International Symposium on Electronic System Design (ISED)
Reference:

Patna, Indien, 2016
Hyperlink:

[Link to the Conference]



» AIBA: an Automated Intra-Cycle Behavioral Analysis for SystemC-based Design Exploration




Author:

Mehran Goli, Jannis Stoppe, Rolf Drechsler
Conference:
IEEE International Conference on Computer Design (ICCD)
Reference:

Phoenix, USA, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Guided Lightweight Software Test Qualification for IP Integration using Virtual Prototypes




Author:

Daniel Große, Hoang M. Le, Muhammad Hassan, Rolf Drechsler
Conference:
IEEE International Conference on Computer Design (ICCD)
Reference:

Phoenix, USA, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Parametric Analysis of Hybrid Systems Using HyMITATOR (Tool Presentation)




Author:

Étienne André, Ulrich Kühne
Conference:
International Conference on Integrated Formal Methods (iFM)
Reference:

Pisa, Italy, 2012
Hyperlink:

[Link to the Conference]



» A Hybrid Algorithm to Conservatively Check the Robustness of Circuits




Author:

Niels Thole, Lorena Anghel, Görschwin Fey
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Pittsburgh, USA, 2016
Hyperlink:

[Link to the Conference]



» Robust Algorithms for High Quality Test Pattern Generation Using Boolean Satisfiability




Author:

Stephan Eggersglüß, Rolf Drechsler
Conference:
International Test Conference (ITC)
Reference:

pp. 1-10, Austin, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Recent Advances in SAT-based ATPG: Non-Standard Fault Models, Multi Constraints and Optimization




Author:

Bernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer
Conference:
International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
Reference:

pp. 1-10, Santorini, Greece, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Hardware-Software Co-Visualization: Developing Systems in the Holodeck




Author:

Rolf Drechsler, Mathias Soeken
Conference:
16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 1-4, Karlovy Vary, Czech Republic, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Synthesis of Reversible Circuits Using Decision Diagrams




Author:

Rolf Drechsler, Robert Wille
Conference:
International Symposium on Electronic System Design (ISED)
Reference:

pp. 1-5, Kolkata, WB, India, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits




Author:

Amr Sayed Ahmed, Ulrich Kühne, Daniel Große, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2015).
Reference:

pp. 1-6, Montpellier, France, 2015.
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» metaSMT: A Unified Interface to SMT-LIB2




Author:

Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL'14)
Reference:

pp. 1-6, Munich, Germany, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» SMT-based Stimuli Generation in the SystemC Verification Library




Author:

Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 1-6, Sophia Antipolis, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC




Author:

Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
International Symposium on System-on-Chip (SoC)
Reference:

pp. 1-7, Tampere, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Analyzing Dependability Measures at the Electronic System Level




Author:

Marc Michael, Daniel Große, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 1-8, Oldenburg, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Quantified Synthesis of Reversible Logic




Author:

Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große
Conference:
Design, Automation, and Test in Europe (DATE)
Reference:

pp. 1015-1020, Munich, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Formal Verification of Integer Multipliers by Combining Gröbner Basis with Logic Reduction




Author:

Amr Sayed Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1048-1053, Dresden, Germany, 2016
Best Paper Candidate
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated Formal Verification of X Propagation with Respect to Testability Issues




Author:

Mehdi Dehbashi, Daniel Tille, Ulrike Pfannkuchen, Stephan Eggersglüß
Conference:
IEEE International Design and Test Symposium 2014 (IDT)
Reference:

pp. 106-111, Algiers, Algerien, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Verifying Dynamic Aspects of UML Models




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1077-1082, Grenoble, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Debugging of Inconsistent UML/OCL Models




Author:

Robert Wille, Mathias Soeken, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1078-1083, Dresden, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Generating an Efficient Instruction Set Simulator from a Complete Property Suite




Author:

Ulrich Kühne, Sven Beyer, Christian Pichler
Conference:
IEEE/IFIP International Symposium on Rapid System Prototyping (RSP)
Reference:

pp. 109-115, Paris, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» WoLFram - A Word Level Framework for Formal Verification




Author:

Andre Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler
Conference:
IEEE/IFIP International Symposium on Rapid System Prototyping (RSP)
Reference:

pp. 11-17, Paris, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Proving Transaction and System-level Properties of Untimed SystemC TLM Designs




Author:

Daniel Große, Hoang M. Le, Rolf Drechsler
Conference:
International Conference on Formal Methods and Models for Codesign (MEMOCODE)
Reference:

pp. 113-122, Grenoble, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» On the Relation Between Simulation-based and SAT-based Diagnosis




Author:

Görschwin Fey, Sean Safarpour, Andreas Veneris, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1139-1144, Munich, 2006
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State-of-the-Art and Research Challenges




Author:

Jan-Hendrik Oetjens, Nico Bannow, Markus Becker, Oliver Bringmann, Andreas Burger, Moomen Chaari, Samarjit Chakraborty, Rolf Drechsler, Wolfgang Ecker, Kim Gruettner, Thomas Kruse, Christoph Kuznik, Hoang M. Le, Andreas Mauderer, Wolfgang Mueller, Daniel Mueller-Gritschneder, Frank Poppen, Hendrik Post, Sebastian Reiter, Wolfgang Rosenstiel, Simon Roth, Ulf Schlichtmann, Andreas von Schwerin, Bogdan-Andrei Tabacaru, Alexander Viehl
Conference:
Design Automation Conference (DAC)
Reference:

pp. 113:1-6, San Francisco, 2014
Hyperlink:

[Link to the Conference]



» Eliminating Invariants in UML/OCL Models




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1142-1145, Dresden, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Generating SystemC Implementations for Clock Constraints specified in UML/MARTE CCSL




Author:

Judith Peters, Robert Wille, Rolf Drechsler
Conference:
International Conference on Engineering of Complex Computer Systems (ICECCS)
Reference:

pp. 116-125, Tianjin, China, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards Formal Verification of Real-World SystemC TLM Peripheral Models - A Case Study




Author:

Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1160-1163, Dresden, Germany, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Verifying SystemC using an Intermediate Verification Language and Symbolic Simulation




Author:

Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

pp. 116:1-6 Austin, Texas, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Estimating Functional Coverage in Bounded Model Checking




Author:

Daniel Große, Ulrich Kühne, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1176-1181, Nice, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Tuning Dynamic Data Flow Analysis to Support Design Understanding




Author:

Jan Malburg, Alexander Finder, Görschwin Fey
Conference:
Design, Automation and Test in Europe (DATE'13)
Reference:

pp. 1179-1184, Grenoble, France, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Determining Relevant Model Elements for the Verification of UML/OCL Specifications




Author:

Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1189-1192, Grenoble, France, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards a Generic Verification Methodology for System Models




Author:

Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1193-1196, Grenoble, France, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization




Author:

Robert Wille, Hongyan Zhang, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

pp. 120-125, Chennai, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Determining the Minimal Number of Lines for Large Reversible Circuits




Author:

Robert Wille, Oliver Keszöcze, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1204—1207, Grenoble, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks




Author:

Görschwin Fey, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1225-1226, Munich, 2006
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Property Analysis and Design Understanding




Author:

Ulrich Kühne, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1246-1249, Nice, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» On the “Q” in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-structure




Author:

Philipp Niemann, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 125-140, Victoria, Canada, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Debugging of Toffoli Networks




Author:

Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1284-1289, Nice, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Latency Analysis for Sequential Circuits




Author:

Alexander Finder, André Sülflow, Görschwin Fey
Conference:
16th IEEE European Test Symposium (ETS)
Reference:

pp. 129-134, Trondheim, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Optimizing DD-based Synthesis of Reversible Circuits using Negative Control Lines




Author:

Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Conference:
IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 129-134, Warschau, Polen, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization




Author:

Stephan Eggersglüß, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1291-1296, Grenoble, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated Post-Silicon Debugging of Failing Speedpaths




Author:

Mehdi Dehbashi, Görschwin Fey
Conference:
21st IEEE Asian Test Symposium (ATS)
Reference:

pp. 13-18, Niigata, Japan, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Contradiction Analysis for Constraint-based Random Simulation




Author:

Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 130-135, Stuttgart, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Efficient Minimization of Fully Testable 2-SPP Networks




Author:

Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1300-1305, Munich, 2006
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Increasing the Accuracy of SAT-based Debugging




Author:

Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1326-1332, Nice, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Verifying UML/OCL Models Using Boolean Satisfiability




Author:

Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1341-1344, Dresden, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» An Integrated SystemC Debugging Environment




Author:

Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke
Conference:
Forum on Specification & Design Languages (FDL)
Reference:

pp. 140-145, Barcelona, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Improving the Mapping of Reversible Circuits to Quantum Circuits Using Multiple Target Lines




Author:

Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 145-150. Yokohama, Japan, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Measuring the Quality of a SystemC Testbench by using Code Coverage Technqiues




Author:

Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 146-151, Barcelona, 2007
Received Best Paper Award
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» From UML/OCL to Base Models: Transformation Concepts for Generic Validation and Verification




Author:

Frank Hilken, Philipp Niemann, Martin Gogolla, Robert Wille
Conference:
International Conference on Model Transformation (ICMT)
Reference:

pp. 149-165, L’Aquila, Italy, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions




Author:

Alexander Finder, Rolf Drechsler
Conference:
40th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 150-155, Barcelona, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Encoding OCL Data Types for SAT-based Verification of UML/OCL Models




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference:
5th International Conference on Tests & Proofs (TAP)
Reference:

pp. 152-170, Zurich, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards Verifying Determinism of SystemC Designs




Author:

Hoang M. Le, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE'14)
Reference:

pp. 153:1-4, Dresden, Germany, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Efficient Simulation-based Debugging of Reversible Logic




Author:

Stefan Frehse, Robert Wille, Rolf Drechsler
Conference:
40th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 156-161, Barcelona, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Improving the Quality of Bounded Model Checking by Means of Coverage Estimation




Author:

Ulrich Kühne, Daniel Große, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
Reference:

pp. 165-170, Porto Alegre, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» BDD Circuit Optimization for Path Delay Fault Testability




Author:

Görschwin Fey, Junhao Shi, Rolf Drechsler
Conference:
Euromicro Symposium on Digital System Design (DSD'2004)
Reference:

pp. 168-172, Rennes, 2004
Hyperlink:

[Link to the Conference]
PS:

[click here]



» Designing a RISC CPU in Reversible Logic




Author:

Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
Conference:
41st International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 170-175, Tuusula, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Checkers for SystemC Designs




Author:

Daniel Große, Rolf Drechsler
Conference:
Second ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2004)
Reference:

pp. 171-178, San Diego, 2004
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Contradictory Antecedent Debugging in Bounded Model Checking




Author:

Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 173-176, Boston, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits




Author:

Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler
Conference:
42nd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 173-178, Victoria, Canada, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Improving CNF Representations in SAT-based ATPG for Industrial Circuits using BDDs




Author:

Daniel Tille, Stephan Eggersglüß, René Krenz-Bååth, Juergen Schloeffel, Rolf Drechsler
Conference:
15th IEEE European Test Symposium (ETS)
Reference:

pp. 176-181, Prag, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Functional Analysis of Circuits Under Timing Variations




Author:

Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
Conference:
17th IEEE European Test Symposium (ETS)
Reference:

pp. 177, Annecy, France, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Speeding up SAT-based ATPG using Dynamic Clause Activation




Author:

Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Conference:
18th Asian Test Symposium (ATS'09)
Reference:

pp. 177-182, Taichung, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Computing Walsh, Arithmetic and Reed-Muller Spectral Decision Diagrams Using Graph Transformations




Author:

Whitney Townsend, Mitch Thornton, Rolf Drechsler and Michael Miller
Conference:
IEEE Great Lakes Symposium on VLSI (GLSV'02)
Reference:

pp. 178-183, New York, 2002
PDF:

[click here]



» Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults




Author:

Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel
Conference:
Fifth ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2007)
Reference:

pp. 181-187, Nice, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure




Author:

Arighna Deb, Debesh Kumar Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 182-195, Victoria, Canada, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» From Requirements and Scenarios to ESL Design in SystemC




Author:

Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
International Symposium on Electronic System Design (ISED)
Reference:

pp. 183-187, Kolkata, WB, India, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» SyReC: A Programming Language for Synthesis of Reversible Circuits




Author:

Robert Wille, Sebastian Offermann, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 184-189, Southampton, 2010
Received Best Paper Award
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Bridging Fault Testability of BDD Circuits




Author:

Junhao Shi, Görschwin Fey, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005)
Reference:

pp. 188-191 Shanghai, 2005
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reversible Logic Synthesis with Output Permutation




Author:

Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler
Conference:
22nd International Conference on VLSI Design
Reference:

pp. 189-194, New Delhi, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Computing Bounds for Fault Tolerance using Formal Techniques




Author:

Görschwin Fey, Andre Sülflow, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

pp. 190-195, San Francisco, USA, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Assessment of Message Missing Failures in FlexRay-Based Networks




Author:

Vahid Lari, Mehdi Dehbashi, Seyed Ghassem Miremadi, Navid Farazmand
Conference:
13th IEEE/IFIP Pacific Rim International Symposium on Dependable Computing (PRDC)
Reference:

pp. 191-194, Melbourne, Australia, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» White Dots do Matter: Rewriting Reversible Logic Circuits




Author:

Mathias Soeken, Michael Kirkedal Thomsen
Conference:
Reversible Computation
Reference:

pp. 196-208, Victoria, Canada, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Equivalence Checking in Multi-level Quantum Systems




Author:

Philipp Niemann, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 201-215, Kyoto, Japan, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Debugging Sequential Circuits Using Boolean Satisfiability




Author:

Moayad Ali, Andreas Veneris, Sean Safarpour, Magdy Abadir, Rolf Drechsler, Alexander Smith
Conference:
IEEE International Conference on Computer Aided Design (ICCAD'04)
Reference:

pp. 204-209, San Jose, 2004
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exploiting Negative Control Lines in the Optimization of Reversible Circuits




Author:

Kamalika Datta, Gaurav Rathi, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 209-220, Victoria, Canada, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automatically Connecting Hardware Blocks via Light-Weight Matching Techniques




Author:

Jan Malburg Niklas Krafczyk Görschwin Fey
Conference:
IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 21-26, Warschau, Polen, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Circuit Line Minimization in the HDL-based Synthesis of Reversible Logic




Author:

Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

pp. 213-218, Amherst, USA, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don’t Cares




Author:

Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Conference:
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Reference:

pp. 214-219, Dallas, 2008
Received IEEE Young Researcher Award
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Efficient Construction of QMDDs for Irreversible, Reversible and Quantum Functions




Author:

Philipp Niemann, Alwin Zulehner, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 214-231, Kolkata, India, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reducing Reversible Circuit Cost by Adding Lines




Author:

D. Michael Miller, Robert Wille, Rolf Drechsler
Conference:
40th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 217-222, Barcelona, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» RevLib: An Online Resource for Reversible Functions and Reversible Circuits




Author:

Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler
Conference:
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Reference:

pp. 220-225, Dallas, 2008
RevLib is available at www.revlib.org
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reducing the Depth of Quantum Circuits Using Additional Lines




Author:

Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 221-233, Victoria, Canada, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Simulation-based Equivalence Checking between SystemC Models at different Levels of Abstraction




Author:

Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 223-228, Lausanne, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Targeting Leakage Constraints during ATPG




Author:

Görschwin Fey, Sathoshi Komatsu, Yasuo Furukawa, Masahiro Fujita
Conference:
Asian Test Symposium (ATS)
Reference:

pp. 225-230, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Timing Arc Based Logic Analysis for False Noise Reduction




Author:

Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler
Conference:
IEEE/ACM International Conference on Computer Aided Design (ICCAD)
Reference:

pp. 225-230, San Jose, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» RobuCheck: A Robustness Checker for Digital Circuits




Author:

Stefan Frehse, Görschwin Fey, Andre Sülflow and Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

pp. 226-231, Lille, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Lazy-CSeq-SP: Boosting Sequentialization-based Verification of Multi-Threaded C Programs via Symbolic Pruning of Redundant Schedules




Author:

Vladimir Herdt, Hoang M. Le, Daniel Große and Rolf Drechsler
Conference:
Automated Technology for Verification and Analysis (ATVA)
Reference:

pp. 228-233, Shanghai, China, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reduction of Sizes of Multiple-Valued Decision Diagrams by Copy Properties




Author:

Dragan Jankovic, Radomir Stankovic, Rolf Drechsler
Conference:
IEEE International Symposium on Multi-Valued Logic (ISMVL'2004)
Reference:

pp. 229-234, Toronto, 2004
Hyperlink:

[Link to the Conference]



» A New SAT-based ATPG for Generating Highly Compacted Test Sets




Author:

Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler
Conference:
15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 230-235, Tallinn, Estonia, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Fast Heuristics for the Edge Coloring of Large Graphs




Author:

Mario Hilgemeier, Nicole Drechsler and Rolf Drechsler
Conference:
Euromicro Symposium on Digital System Design (DSD'2003)
Reference:

pp. 230-237, Antalya, 2003
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Efficient Formal Verification of Track Vacancy Detection Sections




Author:

Sebastian Kinder und Rolf Drechsler
Conference:
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008)
Reference:

pp. 233-240, Budapest, 2008
Hyperlink:

[Link to the Conference]



» Algorithms for Taylor Expansion Diagrams




Author:

Görschwin Fey, Rolf Drechsler, Maciej Ciesielski
Conference:
IEEE International Symposium on Multi-Valued Logic (ISMVL'2004)
Reference:

pp. 235-240, Toronto, 2004
Hyperlink:

[Link to the Conference]
PS:

[click here]



» Efficient Minimization of Multi-Valued Decision Diagrams for Incompletely Specified Functions




Author:

Denis Popel and Rolf Drechsler
Conference:
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003)
Reference:

pp. 241-246, Tokyo, 2003
Hyperlink:

[Link to the Conference]
PS:

[click here]



» Automatic Fault Localization for Programmable Logic Controllers




Author:

Andre Sülflow, Rolf Drechsler
Conference:
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT)
Reference:

pp. 247-256, Braunschweig, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Synthesis of Quantum Circuits for Dedicated Physical Machine Descriptions




Author:

Philipp Niemann, Saikat Basu, Amlan Chakrabarti, Niraj K. Jha, Robert Wille
Conference:
Reversible Computation
Reference:

pp. 248-264, Grenoble, France, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Controlling the Memory During Manipulation of Word-Level Decision Diagrams




Author:

Sebastian Kinder, Görschwin Fey, Rolf Drechsler
Conference:
IEEE International Symposium on Multi-Valued Logic (ISMVL 2005)
Reference:

pp. 250-255, Calgary, 2005
Hyperlink:

[Link to the Conference]
PS:

[click here]



» CEGAR-based EF Synthesis of Boolean Functions with an Application to Circuit Rectification




Author:

Heinz Riener, Rüdiger Ehlers, Görschwin Fey
Conference:
22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 251-256, Chiba/Tokyo, Japan, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated Verification For Train Control Systems




Author:

Jan Peleska, Daniel Große, Anne E. Haxthausen, Rolf Drechsler
Conference:
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2004)
Reference:

pp. 252-265, Braunschweig, 2004
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Extracting Frame Conditions from Operation Contracts




Author:

Philipp Niemann, Frank Hilken, Martin Gogolla, Robert Wille
Conference:
ACM/IEEE 18th International Conference on Model Driven Engineering Languages and Systems (MoDELS)
Reference:

pp. 266-275, Ottawa, Canada, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Assisted Behavior Driven Development Using Natural Language Processing




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference:
50th International Conference on Objects, Models, Components, Patterns (TOOLS)
Reference:

pp. 269-287, Prague, Czech Republic, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Graph Transformation Units Guided by a SAT Solver




Author:

Hans-Jörg Kreowski, Susanne Kuske, Robert Wille
Conference:
International Conference on Graph Transformations (ICGT)
Reference:

pp. 27-42, Enschede, 2010
Hyperlink:

[Link to the Conference]



» BDD-based Synthesis of Reversible Logic for Large Functions




Author:

Robert Wille, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

pp. 270-275, San Francisco, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Modeling Multi-Valued Circuits in SystemC




Author:

Daniel Große, Görschwin Fey and Rolf Drechsler
Conference:
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003)
Reference:

pp. 281-286, Tokyo, 2003
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Elementary Quantum Gate Realizations for Multiple-Control Toffoli Gates




Author:

D. Michael Miller, Robert Wille, Z. Sasanian
Conference:
41st International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 288-293, Tuusula, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits




Author:

Robert Wille, Hongyan Zhang, Rolf Drechsler
Conference:
43rd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 29-34, Toyama, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization




Author:

Stephan Eggersglüß, Mahmut Yilmaz, Krishnendu Chakrabarty
Conference:
21st IEEE Asian Test Symposium (ATS)
Reference:

pp. 290-295, Niigata, Japan, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Evaluation of Cardinality Constraints on SMT-based Debugging




Author:

Andre Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler
Conference:
39th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 298-303, Naha, Okinawa, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Synthesis Flow for Sequential Reversible Circuits




Author:

Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler
Conference:
42nd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 299-304, Victoria, Canada, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Co-Synthesis of Custom On-Chip Bus and Memory for MPSoC Architectures




Author:

Sujan Pandey, Christian Genz, Rolf Drechsler
Conference:
IFIP International Conference on Very Large Scale Integration Systems and Systems on Chip (VLSI-SoC)
Reference:

pp. 304-307, Atlanta, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Assisted Generation of Frame Conditions for Formal Models




Author:

Philipp Niemann, Frank Hilken, Martin Gogolla, Robert Wille
Conference:
Design, Automation and Test in Europe (DATE'15)
Reference:

pp. 309-312, Grenoble, France, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Peak Capture Power Reduction for Compact Test Sets Using Opt-Justification-Fill




Author:

Stephan Eggersglüß
Conference:
22nd IEEE Asian Test Symposium (ATS)
Reference:

pp. 31-16, Yilan, Taiwan, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» The System Verification Methodology for Advanced TLM Verification




Author:

Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler, Wolfgang Ecker, Volkan Esen
Conference:
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
Reference:

pp. 313-322, Tampere, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Debugging of Reversible Circuits using πDDs




Author:

Laura Tague, Mathias Soeken, Shin-ichi Minato, Rolf Drechsler
Conference:
43rd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 316-321, Toyama, Japan, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated Debugging from Pre-Silicon to Post-Silicon




Author:

Mehdi Dehbashi, Görschwin Fey
Conference:
15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 324-329, Tallinn, Estonia, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Equivalence Checking of Reversible Circuits




Author:

Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
Conference:
39th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 324-330, Naha, Okinawa, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exact Template Matching Using Boolean Satisfiability




Author:

Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler
Conference:
43rd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 328-333, Toyama, Japan, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Testability of SPP Three-Level Logic Networks




Author:

Valentina Ciriani, Anna Bernasconi, Rolf Drechsler
Conference:
IFIP International Conference on Very Large Scale Integration (VLSI'03)
Reference:

pp. 331-336, Darmstadt, 2003
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» System Exploration of SystemC Designs




Author:

Christian Genz, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

pp. 335-340, Karlsruhe, 2006
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Synthesizing Multiplier in Reversible Logic




Author:

Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Conference:
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 335-340, Vienna, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Application of Timing Variation Modeling to Speedpath Diagnosis




Author:

Mehdi Dehbashi, Görschwin Fey
Conference:
4th International Conference on System, Software, SoC and Silicon Debug (S4D)
Reference:

pp. 34-37, Vienna, Austria, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Acceleration of SAT-based Iterative Property Checking




Author:

Daniel Große, Rolf Drechsler
Conference:
Correct Hardware Design and Verification Methods (CHARME)
Reference:

pp. 349-353, Saarbrücken, 2005
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Scalable Fault Localization for SystemC TLM Designs




Author:

Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE'13)
Reference:

pp. 35-38, Grenoble, France, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» VisSAT: Visualization of SAT Solver Internals for Computer Aided Hardware Verification




Author:

Robert Wille, André Sülflow, Rolf Drechsler
Conference:
International Conference on Modeling, Simulation and Visualization Methods (MSV)
Reference:

pp. 36-39, Las Vegas, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Using Games for Benchmarking and Representing the Complete Solution Space Using Symbolic Techniques




Author:

Görschwin Fey, Sebastian Kinder and Rolf Drechsler
Conference:
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003)
Reference:

pp. 361-366, Tokyo, 2003
PS:

[click here]



» SAT-based ATPG for Path Delay Faults in Sequential Circuits




Author:

Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'07)
Reference:

pp. 3671-3674, New Orleans, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Evaluating Debugging Algorithms from a Qualitative Perspective




Author:

Alexander Finder, Görschwin Fey
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 37-42, Southampton, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Augmented Sifting for Multiple-Valued Decision Diagrams




Author:

Michael Miller and Rolf Drechsler
Conference:
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003)
Reference:

pp. 375-382, Tokyo, 2003
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Fast Untestability Proof for SAT-based ATPG




Author:

Daniel Tille, Rolf Drechsler
Conference:
12th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
Reference:

pp. 38-43, Liberec, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Completeness-Driven Development




Author:

Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille
Conference:
International Conference on Graph Transformation
Reference:

pp. 38-50, Bremen, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Evaluation of Babbling Idiot Failures in FlexRay-Based Networks




Author:

Vahid Lari, Mehdi Dehbashi, Seyed Ghassem Miremadi, Mojtaba Amiri
Conference:
7th IFAC International Conference on Fieldbuses and Networks in Industrial and Embedded Systems (FET)
Reference:

pp. 399-406, Toulouse, France, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability




Author:

Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

pp. 411-416, Montpellier, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Visualization of SystemC Designs




Author:

Christian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS)
Reference:

pp. 413-416, New Orleans, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» CheckSyC: An Efficient Property Checker for RTL SystemC Designs




Author:

Daniel Große, Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'05)
Reference:

pp. 4167-4170, Kobe, 2005
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automatic Property Generation for the Formal Verification of Bus Bridges




Author:

Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
Conference:
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 417-422, Cottbus, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^m) in SystemC




Author:

Andre Sülflow, Rolf Drechsler
Conference:
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07)
Reference:

pp. 42, Oslo, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» HW/SW Co-Verification of Embedded Systems using Bounded Model Checking




Author:

Daniel Große, Ulrich Kühne, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 43-48, Philadelphia, 2006
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Verification of PLC Programs using Formal Proof Techniques




Author:

Andre Sülflow, Rolf Drechsler
Conference:
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008)
Reference:

pp. 43-50, Budapest, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Model-Based Diagnosis versus Error Explanation




Author:

Heinz Riener, Görschwin Fey
Conference:
10th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'12)
Reference:

pp. 43-52, Arlington, Virginia, USA, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Window Optimization of Reversible and Quantum Circuits




Author:

Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Conference:
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 431-435, Vienna, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» On Modeling and Evaluation of Logic Circuits Under Timing Variations




Author:

Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
Conference:
15th Euromicro Conference on Digital System Design (DSD)
Reference:

pp. 431-436, Izmir, Turkey, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» TLM Protocol Compliance Checking at the Electronic System Level




Author:

Mohamed Bawadekji, Daniel Große, Rolf Drechsler
Conference:
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 435-440, Cottbus, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Debug Automation for Synchronization Bugs at RTL




Author:

Mehdi Dehbashi, Görschwin Fey
Conference:
27th International Conference on VLSI Design
Reference:

pp. 44-49, Mumbai, India, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Improving Test Pattern Compactness in SAT-based ATPG




Author:

Stephan Eggersglüß, Rolf Drechsler
Conference:
16th Asian Test Symposium (ATS’07)
Reference:

pp. 445-450, Beijing, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Anwendungsbezogene Analyse der Robustheit von Digitalen Schaltungen




Author:

Andre Sülflow, Stefan Frehse, Görschwin Fey, Rolf Drechsler
Conference:
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)
Reference:

pp. 45-52, Stuttgart, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Enhancing Debugging of Multiple Missing Control Errors in Reversible Logic




Author:

Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 465-470, Rhode Island, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» BDD Minimization for Approximate Computing




Author:

Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 474-479, Macao, China, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated Design Debugging in a Testbench-Based Verification Environment




Author:

Mehdi Dehbashi, André Sülflow, Görschwin Fey
Conference:
14th Euromicro Conference on Digital System Design (DSD)
Reference:

pp. 479-486, Oulu, Finland, 2011
Best Paper Candidate
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Efficient Automated Speedpath Debugging




Author:

Mehdi Dehbashi, Görschwin Fey
Conference:
16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 48-53, Karlovy Vary, Czech Republic, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Efficient Synthesis of Quantum Circuits Implementing Clifford Group Operations




Author:

Philipp Niemann, Robert Wille, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 483-488, Singapore, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Optimal SWAP Gate Insertion for Nearest Neighbor Quantum Circuits




Author:

Robert Wille, Aaron Lye, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 489-494, Singapore, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Fault Effects in FlexRay-Based Networks with Hybrid Topology




Author:

Mehdi Dehbashi, Vahid Lari, Seyed Ghassem Miremadi, Mohammad Shokrollah-Shirazi
Conference:
3rd IEEE International Conference on Availability, Reliability and Security (ARES)
Reference:

pp. 491-496, Barcelona, Spain, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Improvements for Constraint Solving in the SystemC Verification Library




Author:

Daniel Große, Rüdiger Ebendt, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 493-496, Stresa, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Finding Good Counter-Examples to Aid Design Verification




Author:

Görschwin Fey, Rolf Drechsler
Conference:
First ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2003)
Reference:

pp. 51-52, Mont Saint-Michel, 2003
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Exact BDD Minimization for Path-Related Objective Functions




Author:

Rüdiger Ebendt, Rolf Drechsler
Conference:
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC 2005)
Reference:

pp. 525-530, Perth, 2005
Hyperlink:

[Link to the Conference]
PS:

[click here]



» Formal Specification Level: Towards Verification-driven Design Based on Natural Language Processing




Author:

Rolf Drechsler, Mathias Soeken, Robert Wille
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 53-58, Vienna, Austria, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking




Author:

Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

pp. 542-549, Parma, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Lower Bounds for Dynamic BDD Reordering




Author:

Rüdiger Ebendt and Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005)
Reference:

pp. 579-582, Shanghai, 2005
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Quasi-Exact BDD Minimization using Relaxed Best-First Search




Author:

Rüdiger Ebendt and Rolf Drechsler
Conference:
IEEE Annual Symposium on VLSI (ISVLSI '05)
Reference:

pp. 59-64, Tampa, Florida, 2005
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Analyse dynamischer Abhängigkeitsgraphen zum Debugging von Hardwaredesigns




Author:

Jan Malburg Alexander Finder Görschwin Fey
Conference:
7. ITG/GMM/GI-Fachtagung Zuverlässigkeit und Entwurf (ZuE2013)
Reference:

pp. 59-66, Dresden, Germany, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Overcoming Limitations of the SystemC Data Introspection




Author:

Christian Genz, Rolf Drechsler
Conference:
Design Automation and Test in Europe (DATE)
Reference:

pp. 590-593, Nice, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Improving Coverage of Simulation-based Verification by Dedicated Stimuli Generation




Author:

Shuo Yang, Robert Wille, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

pp. 599-606, Verona, Italy, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Fast Exact Toffoli Network Synthesis of Reversible Logic




Author:

Robert Wille, Daniel Große
Conference:
IEEE International Conference on Computer Aided Design (ICCAD)
Reference:

pp. 60-64, San Jose, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Behaviour Driven Development for Tests and Verification




Author:

Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
Conference:
8th International Conference on Tests & Proofs (TAP)
Reference:

pp. 61-77, York, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Improving Simulation-Based Verification by Means of Formal Methods




Author:

Görschwin Fey, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
Reference:

pp. 640-643, Yokohama, 2004
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Efficient Automatic Visualization of SystemC Designs




Author:

Daniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst
Conference:
Forum on Specification & Design Languages (FDL'03)
Reference:

pp. 646-657, Frankfurt, 2003
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reducing the Number of Lines in Reversible Circuits




Author:

Robert Wille, Mathias Soeken, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

pp. 647-652, Anaheim, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Efficient Test Generation with Maximal Crosstalk-Induced Noise using Unconstrained Aggressor Excitation




Author:

Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS)
Reference:

pp. 649-652, Paris, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated Post-Silicon Debugging of Design Bugs




Author:

Mehdi Dehbashi, Görschwin Fey
Conference:
3rd International Conference on System, Software, SoC and Silicon Debug (S4D)
Reference:

pp. 67-71, Munich, Germany, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines




Author:

Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler
Conference:
42nd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 69-74, Victoria, Canada, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Robust Multi-Objective Optimization in High Dimensional Spaces




Author:

André Sülflow, Nicole Drechsler, Rolf Drechsler
Conference:
Fourth International Conference on Evolutionary Multi-Criterion Optimization
Reference:

pp. 715-726, Matsushima, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Synthesizing Reversible Circuits for Irreversible Functions




Author:

D. Michael Miller, Robert Wille, Gerhard W. Dueck
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

pp. 749-756, Patras, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Formaler Nachweis der Fehlertoleranz von Schaltkreisen




Author:

Görschwin Fey, Andre Sülflow, Stefan Frehse, Ulrich Kühne, Rolf Drechsler
Conference:
GMM/GI/ITG-Fachtagung: Zuverlässigkeit und Entwurf (ZuE 2008)
Reference:

pp. 75-82, Ingolstadt, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Combination of Lower Bounds in Exact BDD Minimization




Author:

Rüdiger Ebendt, Wolfgang Günther and Rolf Drechsler
Conference:
IEEE Design, Automation and Test in Europe (DATE'03)
Reference:

pp. 758-763, Munich, 2003
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Structural Heuristics for SAT-based ATPG




Author:

Daniel Tille, Stephan Eggersglüß, Hoang M. Le, Rolf Drechsler
Conference:
17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2009)
Reference:

pp. 77-82, Florianópolis, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Using Unsatisfiable Cores to Debug Multiple Design Errors




Author:

Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler
Conference:
IEEE Great Lakes Symposium on VLSI (GLSVLSI'08)
Reference:

pp. 77-82, Orlando, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Better-Than-Worst-Case Robustness Measure




Author:

Stefan Frehse, Görschwin Fey, Rolf Drechsler
Conference:
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 78-83, Vienna, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits




Author:

Rolf Drechsler, Robert Wille
Conference:
41st International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 78-85, Tuusula, 2011
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Quantitative Timing Analysis of UML Activity Diagrams Using Statistical Model Checking




Author:

Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 780-785, Dresden, Germany, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Constraint-based Platform Variants Specification for Early System Verification




Author:

Andreas Burger, Alexander Viehl, Andreas Braun, Finn Haedicke, Daniel Große, Oliver Bringmann, Wolgang Rosenstiel
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 800-805, Singapore, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exploration of Sequential Depth by Evolutionary Algorithms




Author:

Nicole Drechsler, Rolf Drechsler
Conference:
IFIP International Conference on Very Large Scale Integration (VLSI'03)
Reference:

pp. 81-85, Darmstadt, 2003
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Increasing Robustness of SAT-based Delay Test Generation using Efficient Dynamic Learning Techniques




Author:

Stephan Eggersglüß, Rolf Drechsler
Conference:
14th IEEE European Test Symposium (ETS)
Reference:

pp. 81-86, Sevilla, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Robustness Check for Multiple Faults using Formal Techniques




Author:

Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

pp. 85-90, Patras, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Improved SAT-based ATPG: More Constraints, Better Compaction




Author:

Stephan Eggersglüß, Robert Wille, Rolf Drechsler
Conference:
IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
Reference:

pp. 85-90, San Jose, USA, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Synthesis of Reversible Circuits with Minimal Lines for Large Functions




Author:

Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 85-92, Sydney, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Minimization of the Expected Path Length in BDDs Based on Local Changes




Author:

Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
Reference:

pp. 866-871, Yokohama, 2004
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Post-Verification Debugging of Hierarchical Designs




Author:

Moayad Ali, Sean Safarpour, Andreas Veneris, Magdy Abadir, Rolf Drechsler
Conference:
IEEE International Conference on Computer Aided Design (ICCAD'05)
Reference:

pp. 871-876, San Jose, 2005
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Combining Ordered Best-First Search with Branch and Bound for Exact BDD Minimization




Author:

Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
Reference:

pp. 876-879, Yokohama, 2004
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» SWORD: A SAT like Prover Using Word Level Information




Author:

Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
Conference:
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC)
Reference:

pp. 88-93, Atlanta, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Hardware-Software-Co-Synthese zur Verbesserung der Fehlertoleranz




Author:

Stefan Frehse, Heinz Riener, Görschwin Fey
Conference:
6. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE'12)
Reference:

pp. 90-96, Bremen, Germany, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Improving Fault Tolerance Utilizing Hardware-Software-Co-Synthesis




Author:

Heinz Riener, Stefan Frehse, Görschwin Fey
Conference:
Design, Automation and Test in Europe (DATE'13)
Reference:

pp. 939-943, Grenoble, France, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» On the Influence of Boolean Encodings in SAT-based ATPG for Path Delay Faults




Author:

Stephan Eggersglüß, Rolf Drechsler
Conference:
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Reference:

pp. 94-99, Dallas, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated Feature Localization for Hardware Designs using Coverage Metrics




Author:

Jan Malburg, Alexander Finder, Görschwin Fey
Conference:
Design Automation Conference (DAC)
Reference:

pp. 941-946, San Francisco, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exact SAT-based Toffoli Network Synthesis




Author:

Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 96-101, Stresa, 2007
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Experimental Studies on SAT-based Test Pattern Generation for Industrial Circuits




Author:

Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke
Conference:
International Conference on ASIC (ASICON 2005)
Reference:

pp. 967-970, Shanghai, 2005
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Filmstripping and Unrolling: A Comparison of Verification Approaches for UML and OCL Behavioral Models




Author:

Frank Hilken, Philipp Niemann, Martin Gogolla, Robert Wille
Conference:
8th International Conference on Tests & Proofs (TAP)
Reference:

pp. 99-116, York, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Synthesizing Checkers for On-line Verification of System-on-Chip Designs




Author:

Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'03)
Reference:

pp. IV:748-IV:751, Bangkok, 2003
PDF:

[click here]



» Formal Verification of LTL Formulas for SystemC Designs




Author:

Daniel Große, Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'03)
Reference:

pp. V:245-V:248, Bangkok, 2003
PDF:

[click here]



» Reducing the Number of Variable Movements in Exact BDD Minimization




Author:

Rüdiger Ebendt
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'03)
Reference:

pp. V:605-V:608, Bangkok, 2003
PDF:

[click here]



» PASSAT: Efficient SAT-based Test Pattern Generation




Author:

Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Conference:
IEEE Annual Symposium on VLSI (ISVLSI '05)
Reference:

pp.212-217, Tampa, Florida, 2005
Hyperlink:

[Link to the Conference]
PS:

[click here]



» Using QBF to Increase Accuracy of SAT-Based Debugging




Author:

Andre Sülflow, Görschwin Fey, Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS)
Reference:

pp.641-644, Paris, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips




Author:

Oliver Keszöcze, Mohamed Ibrahim, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
Conference:
International Conference on VLSI Design (VLSID)
Reference:

Pune, Indien, 2018
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» An Introduction to Reversible Circuit Design




Author:

Robert Wille
Conference:
Saudi International Electronics, Communications and Photonics Conference (SIECPC)
Reference:

Riyadh, 2011
Hyperlink:

[Link to the Conference]



» Ground Setting Properties for an Efficient Translation of OCL in SMT-based Model Finding




Author:

Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
ACM/IEEE 19th International Conference on Model Driven Engineering Languages and Systems (MoDELS)
Reference:

Saint Malo, Brittany, France, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Orchestrated Multi-level Information Flow Analysis to Understand SoCs




Author:

Görschwin Fey
Conference:
48th Design Automation Conference (DAC)
Reference:

San Diego, USA, 2011
Promotion video on YouTube
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Realizing Reversible Circuits Using a New Class of Quantum Gates




Author:

Zahra Sasanian, Robert Wille, Michael Miller
Conference:
Design Automation Conference (DAC)
Reference:

San Francisco, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exact One-pass Synthesis of Digital Microfluidic Biochips




Author:

Oliver Keszöcze, Robert Wille, Tsung-Yi Ho, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

San Francisco, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Generic Representation of CCSL Time Constraints for UML/MARTE Models




Author:

Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

San Francisco, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Verifying SystemC using Stateful Symbolic Simulation




Author:

Vladimir Herdt, Hoang M. Le, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

San Francisco, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Hiding Higher-Order Side-Channel Leakage - Randomizing Cryptographic Implementations in Reconfigurable Hardware




Author:

Pascal Sasdrich, Amir Moradi, Tim Güneysu
Conference:
RSA Conference Cryptographers’ Track (CT-RSA)
Reference:

San Francisco, US, 2017.
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» A Basis for Formal Robustness Checking




Author:

Görschwin Fey, Rolf Drechsler
Conference:
International Symposium on Quality of Electronic Design (ISQED)
Reference:

San Jose, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Adaptive Branch and Bound using SAT to Estimate False Crosstalk




Author:

Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler
Conference:
International Symposium on Quality of Electronic Design (ISQED)
Reference:

San Jose, 2008
Hyperlink:

[Link to the Conference]



» Polynomial Datapath Optimization using Constraint Solving and Formal Modelling




Author:

Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler
Conference:
IEEE/ACM International Conference on Computer Aided Design (ICCAD)
Reference:

San Jose, 2010
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Automated and Quality-driven Requirements Engineering




Author:

Rolf Drechsler, Mathias Soeken, Robert Wille,
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

San Jose, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Exact Routing for Digital Microfluidic Biochips with Temporary Blockages




Author:

Oliver Keszöcze, Robert Wille, Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

San Jose, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Cone of Influence Analysis at the Electronic System Level Using Machine Learning




Author:

Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Santander, Spain, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Minimal Stimuli Generation in Simulation-based Verification




Author:

Shuo Yang, Robert Wille, Daniel Große and Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Santander, Spain, 2013
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Fault Detection in Parity Preserving Reversible Circuits




Author:

Nils Przigoda, Gerhard Dueck, Robert Wille, Rolf Drechsler
Conference:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Sapporo, Japan, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits




Author:

Md. Mazder Rahman, Gerhard W. Dueck, Anupam Chattopadhyay, Robert Wille
Conference:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Sapporo, Japan, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Logic Synthesis for Quantum State Generation




Author:

Philipp Niemann, Rhitam Datta, Robert Wille
Conference:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Sapporo, Japan, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation




Author:

Laxmidhar Biswal, Chandan Bandyopadhyay, Anupam Chattopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Conference:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Sapporo, Japan, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Re-writing HDL Descriptions for Line-aware Synthesis of Reversible Circuits




Author:

Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Conference:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Sapporo, Japan, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Technology mapping of reversible circuits to Clifford+T quantum circuits




Author:

Nabila Abdessaied, Matthew Amy, Mathias Soeken, Rolf Drechsler
Conference:
46rd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Sapporo, Japan, 2016
Hyperlink:

[Link to the Conference]



» Switching Activity Estimation for Finite State Machines for Low Power Synthesis (Poster)




Author:

Mikael Kerttu, Per Lindgren, Mitch Thornton and Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'02)
Reference:

Scottsdale, 2002
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» Process Variations Aware Robust on-Chip Bus Architecture Synthesis for MPSoCs




Author:

Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'08)
Reference:

Seattle, 2008
Hyperlink:

[Link to the Conference]



» Robust On-Chip Bus architecture Synthesis for MPSoCs Under Random Tasks Arrival




Author:

Sujan Pandey, Rolf Drechsler
Conference:
13th Asia and South Pacific Design Automation Conference, (ASP-DAC 2008)
Reference:

Seoul, 2008
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology




Author:

Rolf Drechsler, Robert Wille
Conference:
International Symposium on VLSI Design and Test (VDAT)
Reference:

Shibpur, India, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Efficiency of Multiple-Valued Encoding in SAT-based ATPG




Author:

Görschwin Fey, Junhao Shi, Rolf Drechsler
Conference:
IEEE International Symposium on Multiple-Valued Logic (ISMVL '06)
Reference:

Singapore, 2006
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Deterministc Algorithms for ATPG under Leakage Constraints




Author:

Görschwin Fey
Conference:
18th Asian Test Symposium (ATS'09)
Reference:

Taichung, 2009
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Approximate BDD Minimization by Weighted A*




Author:

Rüdiger Ebendt, Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'09)
Reference:

Taipei, 2009
Hyperlink:

[Link to the Conference]



» Identification of Efficient Clustering Techniques for Test Power Activity on the Layout




Author:

Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
Conference:
26th IEEE Asian Test Symposium (ATS)
Reference:

Taipei, Taiwan, 2017
Hyperlink:

[Link to the Conference]



» WCET Overapproximation for Software in the Context of Cyber-Physical Systems




Author:

Niklas Krafczyk, Heinz Riener, Görschwin Fey
Conference:
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Reference:

Tallinn, Estonia, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» ParCoSS: Efficient Parallelized Compiled Symbolic Simulation




Author:

Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
International Conference on Computer Aided Verification (CAV)
Reference:

Toronto, Canada, 2016
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Transaction-Based Online Debug for NoC-Based Multiprocessor SoCs




Author:

Mehdi Dehbashi, Görschwin Fey
Conference:
22nd Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP)
Reference:

Turin, Italy, 2014
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Placement and Routing Optimization for Circuits Derived from BDDs




Author:

Thomas Eschbach, Rolf Drechsler, Bernd Becker
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'04)
Reference:

Vancouver, 2004
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Towards Early Validation of Firmware-Based Power Management using Virtual Prototypes: A Constrained Random Approach




Author:

Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Verona, Italy, 2017
Best Paper Candidate
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Localizing Features of ESL Models for Design Understanding




Author:

Marc Michael, Daniel Große, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Vienna, 2012
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» More than true or false: Native Support of Irregular Values in the Automatic Validation & Verification of UML/OCL Models




Author:

Nils Przigoda, Philipp Niemann, Judith Peters, Frank Hilken, Robert Wille, Rolf Drechsler
Conference:
15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Reference:

Vienna, Austria, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Yise - A novel Framework for Boolean Networks using Y-Inverter Graphs




Author:

Arun Chandrasekharan, Daniel Große, Rolf Drechsler
Conference:
15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Reference:

Vienna, Austria, 2017
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Incorporating User Preferences in Many-Objective Optimization using Relation Epsilon-Preferred




Author:

Nicole Drechsler, André Sülflow, Rolf Drechsler
Conference:
International Conference on Evolutionary Computation Theory and Applications (ECTA)
Reference:

Vilamoura, Portugal, 2013
Hyperlink:

[Link to the Conference]



» Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor




Author:

Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey
Conference:
IEEE Design, Automation and Test in Europe
Reference:

Vol. I, pp. 162-167, Paris, 2004
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Managing Don't Cares in Boolean Satisfiability




Author:

Sean Safarpour, Andreas Veneris, Rolf Drechsler, Joanne Hang
Conference:
IEEE Design, Automation and Test in Europe
Reference:

Vol. I, pp. 260-265, Paris, 2004
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Minimizing the Number of One-Paths in BDDs by an Evolutionary Algorithm




Author:

Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler
Conference:
Congress on Evolutionary Computation 2003 (CEC2003)
Reference:

Vol.3, pp.1724-1731, Canberra, 2003
Hyperlink:

[Link to the Conference]
PDF:

[click here]
PS:

[click here]



» SPIHT implemented in a XC4000 device




Author:

Jörg Ritter, Görschwin Fey and Paul Molitor
Conference:
IEEE The 45rd Midwest Symposium on Circuits and Systems (MWSCAS'2002)
Reference:

volume I, pages 239-242, Tulsa, 2002
PDF:

[click here]



» Utilizing BDDs for disjoint SOP minimization




Author:

Görschwin Fey and Rolf Drechsler
Conference:
IEEE The 45rd Midwest Symposium on Circuits and Systems (MWSCAS'2002)
Reference:

volume II, pages 306-309, Tulsa, 2002
PS:

[click here]



» An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization




Author:

Arighna Deb, Robert Wille, Rolf Drechsler, Debesh Das
Conference:
45th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Waterloo, Canada, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» An Examination of the NCV-v1 Quantum Library Based on Minimal Circuits




Author:

Arman Allahyari-Abhari, Robert Wille, Rolf Drechsler
Conference:
45th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Waterloo, Canada, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Dynamic Template Matching with Mixed-polarity Toffoli Gates




Author:

Md Mazder Rahman, Mathias Soeken, Gerhard W. Dueck
Conference:
45th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Waterloo, Canada, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Fredkin-Enabled Transformation-based Reversible Logic Synthesis




Author:

Mathias Soeken, Anupam Chattopadhyay
Conference:
45th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Waterloo, Canada, 2015
Hyperlink:

[Link to the Conference]
PDF:

[click here]



» Kompositionelle Formale Robustheitsprüfung




Author:

Stefan Frehse, Görschwin Fey
Conference:
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)
Reference:

Wildbad Kreuth, 2010
Hyperlink:

[Link to the Conference]






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