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Supporting doctoral candidates is very important. The following doctoral theses have been supervised in the group, the list gives a chronological overview of authors and titles.

Dr. David Lemma

Specification Analysis for System-Level Power-Aware ASIC Design, 2021

Dr. Muhammad Hassan

Enhanced Modern Virtual Prototype based Verification Flow for Heterogeneous Systems, 2021

Dr. Fritjof Bornebusch

COQ meets CλaSH - Proposing a Hardware Design Synthesis Flow that Combines Proof Assistants with Functional Hardware Description Languages, 2021

Dr. Marcel Walter

Design Automation for Field-Coupled Nanotechnologies, 2021

Dr. Mazyar Seraj

Impacts of Block-based Programming on Young Learners’ Programming Skills and Attitude in the Context of Smart Environments, 2020

Dr. Sebastian Huhn

Next Generation Design For Testability, Debug and Reliability Using Formal Techniques, 2020
also presented at PhD-Forum: ASP-DAC 2021 und DATE 2021

Dr. Vladimir Herdt

Efficient Modeling, Verification and Analysis Techniques to Enhance the Virtual Prototype based Design Flow for Embedded Systems, 2020

Dr. Harshad Dhotre

Pattern Analysis for Power Safe Testing and Prediction Using Machine Learning, 2019

Dr. Mehran Goli

Automated Analysis of Virtual Prototypes at the Electronic System Level -Design Understanding and Applications-, 2019

Dr. Kenneth Schmitz

Trust is good, Control is better: A Container based System Design Scheme, 2019

Dr. Arighna Deb

Logic Synthesis Techniques for Optical Circuits, 2018

Dr. Saeideh Shirinzadeh

Synthesis and Optimization for Logic-in-Memory Computing using Memristive Devices, 2018

Dr. Zaid Saleem Ali Al-Wardi

HDL-based Synthesis of Reversible Circuits|A Scalable Design Approach, 2018

Dr. Arun Chandrasekharan

Design Automation Techniques for Approximation Circuits - Synthesis, Verification and Test -, 2017

Dr. Oliver Keszöcze

Exact Design of Digital Microfluidic Biochips, 2017

Dr. Nils Przigoda

SMT-based Validation & Verification of UML/OCL Models, 2017

Dr. Amr Sayed-Ahmed

Highly Automated Formal Verification of Arithmetic Circuits, 2017

Dr. Jannis Stoppe

Non-Intrusive Analysis of Electronic System Level Designs in SystemC, 2017

Dr. Thole Niels

Formal Verification throughout the Development of Robust Systems, 2016

Dr. Ngouo´goum Tague Laura Sandrine

Using Decision Diagrams in the Design of Reversible Circuit, 2016

Dr. Philipp Niemann

Towards Computer-Aided Design of Quantum Logic: Compact Representations and Efficient Synthesis Methods for an Emerging Technology, 2016

Dr. Eleonora Schönborn

Scalable Design and Synthesis of Reversible Circuits, 2016

Dr. Finn Haedicke

High-Quality Hardware Design and Verification using Word-Level Satisfiability Techniques, 2016

Dr. Judith Peters

Exploiting MARTE/CCSL in Modern Design Flows, 2015

Dr. Nabila Abdessaied

Reversible and Quantum Circuits | Optimization and Complexity Analysis, 2015

Dr. Jan Malburg

Feature Localization and Design Understanding for Hardware Designs, 2015

Dr. Melanie Diepenbeck

Completing Behaviour Driven Development for Testing and Verification, 2015

Dr. Julia Seiter

Formal Model Refinement, 2015

Dr. Hoang M. Le

Automated Techniques for Functional Verification at the Electronic System Level, 2015
also presented at PhD-Forum: DATE 2013 (Best Poster Award)

Dr. Shuo Yang

Improving Coverage in Simulation-based Verification, 2015

Dr. Marc Michael

Methoden zum Erfassen und Entwickeln von SystemC Modellen, 2014

Dr. Elsa Andrea Kirchner

Embedded Brain Reading, 2014

Dr. Mathias Soeken

Formal Specification Level Concepts, Methods, and Algorithms, 2013

Dr. Mehdi Dehbashi

Debug Automation from Pre-Silicon to Post-Silicon, 2013

Dr. Stefan Frehse

Quality and Quantity in Robustness Checking Using Formal Techniques, 2013

Dr. Hongyan Zhang

Testing of Reversible Circuits, 2013

Dr. Beate Kapturek

Vorgehensmodelle für die Technische Dokumentation Eingebetteter Systeme, 2013

Dr. Daniel Tille

Advanced Utilization of Formal Methods in Automatic Test Pattern Generation for Industrial Designs, 2011
also presented at Student-Forum: ETS 2009

Dr. Stephan Eggersglüß

Robust Algorithms for High Quality Test Pattern Generation Using Boolean Satisfiability, 2010
also presented at PhD-Forum: DATE 2009

Dr. André Sülflow

WoLFram – A Word Level Framework for Formal Verification and its Application, 2010
also presented at PhD-Forum: DATE 2011

Dr. Robert Wille

Towards a Design Flow for Reversible Logic, 2009
also presented at PhD-Forum: DAC 2009

Dr. Ulrich Kühne

Advanced Automation in Formal Verification of Processors, 2009
also presented at PhD-Forum: DATE 2010

Dr. Frank Rogin

An Integrated Approach to Utilize Designer´s Debug Capacity in System-on-a-Chip Designs, 2009
also presented at PhD-Forum: DATE 2009

Dr. Daniel Große

Quality-Driven Design and Verification Flow for Digital Systems, 2008
also presented at PhD-Forum: DATE 2008

Dr. Sebastian Kinder

Automated Validation and Verification of Railway Specific Components and Systems, 2008

Dr. Junhao Shi

Boolean Techniques in Testing of Digital Circuits, 2007

Dr. Görschwin Fey

Increasing Robustness and Usability of Circuit Design Tools by Using Formal Techniques, 2006
also presented at PhD-Forum: DATE 2007


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