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Design Rewiring Using ATPG

Prof. Dr. Andreas Veneris
[ University of Toronto, Kanada ]


Date: 2005-02-14
Time: 10.00 Uhr c.t.
Place: Bremen, Uni Bremen
Meetingpoint: Raum 5210, MZH


ABSTRACT
Logic optimization is the step of the VLSI design cycle where the designer performs modifications on a design (netlist) to satisfy different constraints such as area, power or delay. Recently, ATPG-based design rewiring techniques for logic optimization have gained increasing popularity when compared to symbolic ones. In this talk we present a novel ATPG-based design rewiring methodology that borrows from design error diagnosis and correction techniques. The method optimizes a design by adding an error and correcting this error in a less critical part of the design. It can be shown that it works in the opposite direction to what existing ATPG-based design rewiring procedures do. However, when design rewiring is viewed in this new direction it can be shown that it offers additional optimization gains and a more systematic platform to design rewiring. We also examine the complexity requirements of this method and we arrive to a new set of interesting results with particular importance in the area. Experiments justify its robustness and practicality while they motivate future work in the topic. Finally, we will outline the application of this method to delay optimization in the latest series of the PowerPC(tm) Microprocessor by Motorola (now Freescale) where this work was implemented since 2002.

VITA
Andreas Veneris received a Diploma in Computer Engineering and Informatics from the University of Patras in 1991, an M.S. degree in Computer Science from the University of Southern California, Los Angeles in 1992 and a Ph.D. degree in Computer Science from the University of Illinois at Urbana-Champaign in 1998. In 1998 he was a visiting faculty at the University of Illinois until 1999 when he joined the Department of Electrical and Computer Engineering and the Department of Computer Science at the University of Toronto where he is an Associate Professor today. His research interests include CAD for synthesis, testing/diagnosis and verification of digital circuits and systems and combinatorics.



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