» Weighted A* search - unifying view and application
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Autor:
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Rüdiger Ebendt, Rolf Drechsler |
| Journal: |
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Artificial Intelligence |
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Volume 173, Issue 15, Pages 1367-1456 (September 2009) |
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2009
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» Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
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Autor:
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Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille |
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it - information technology |
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Volume 51, Number 2, pp. 102-111
Pdf download |
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2009
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» Exact Synthesis of Elementary Quantum Gate Circuits
[Link to the homepage of the journal]
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Autor:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Journal: |
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Multiple-Valued Logic and Soft Computing |
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Volume 15, Number 4, pp. 283-300 |
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2009
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» Advanced Verification by Automatic Property Generation
[Link to the homepage of the journal]
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Autor:
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Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke |
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IET Computers & Digital Techniques |
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Volume 3, Issue 4, pp. 338-353, July |
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2009
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» Exact Multiple Control Toffoli Network Synthesis with SAT Techniques
[Link to the homepage of the journal]
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Autor:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Journal: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 28, Number 5, pp. 703-715, May |
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2009
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» Modeling and Proving Completeness in Formal Verification of Counting Heads
[Link to the homepage of the journal]
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Autor:
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Sebastian Kinder, Rolf Drechsler |
| Journal: |
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Software Tools for Technology Transfer (STTT)
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Springer, Volume 10, Number 6, pp. 521 - 534 |
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2008
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» On Acceleration of SAT-based ATPG for Industrial Designs
[Link to the homepage of the journal]
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Autor:
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Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Daniel Tille |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 27, Number 7, pp. 1329-1333, July |
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2008
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» Improved SAT-based Reachability Analysis with Observability Don’t Cares
[Link to the homepage of the journal]
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Autor:
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Sean Safarpour, Andreas Veneris and Rolf Drechsler |
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Journal on Satisfiability, Boolean Modeling and Computation (JSAT) |
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Volume 5, pp. 1-25, Special Volume on Application of Constraints to Formal Verification |
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2008
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» On the Construction of Small Fully Testable Circuits with Low Depth
[Link to the homepage of the journal]
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Autor:
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Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler |
| Journal: |
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Embedded Hardware Design - Microprocessors and Microsystems (MICPRO) |
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Special Issue, Volume 32, Issues 5-6, pp. 263-269 |
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2008
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» Logic Minimization and Testability of 2-SPP Networks
[Link to the homepage of the journal]
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Autor:
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Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa |
| Journal: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 27, Number 7, pp. 1190-1202, July |
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2008
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» Analyzing Functional Coverage in Bounded Model Checking
[Link to the homepage of the journal]
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Autor:
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Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Journal: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 27, Number 7, pp. 1305-1314, July |
Year:
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2008
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» Automatic Fault Localization for Property Checking
[Link to the homepage of the journal]
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Autor:
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Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler |
| Journal: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 27, Number 6, pp. 1138-1149, June |
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2008
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» BDD-based Verification of Scalable Designs
[Link to the homepage of the journal]
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Autor:
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Daniel Große, Rolf Drechsler |
| Journal: |
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Facta Universitatis, Series: Electronics and Energetics |
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Volume 20, Number 3, pp. 367-379 |
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2007
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» Building Free Binary Decision Diagrams Using SAT Solvers
[Link to the homepage of the journal]
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Autor:
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Robert Wille, Görschwin Fey, Rolf Drechsler |
| Journal: |
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Facta Universitatis, Series: Electronics and Energetics |
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Volume 20, Number 3, pp. 381-394, |
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2007
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» An Integrated Approach for Combining BDDs and SAT Provers
[Link to the homepage of the journal]
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Autor:
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Rolf Drechsler, Görschwin Fey, Sebastian Kinder |
| Journal: |
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Facta Universitatis, Series: Electronics and Energetics
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| Details: |
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Volume 20, Number 3, pp. 415-436 |
Year:
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2007
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» Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic
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Autor:
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Sujan Pandey, Manfred Glesner |
| Journal: |
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IEEE Transaction on Very Large Scale Integration (VLSI) Systems |
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Volume 15, Number 10, pp. 1111-1124, October |
Year:
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2007
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» Technische Dokumentation von Soft- und Hardware in
eingebetteten Systemen
[Link to the homepage of the journal]
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Autor:
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Beate Muranko, Rolf Drechsler |
| Journal: |
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it - information technology |
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Number 2, pp. 110-117
Pdf download |
Year:
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2007
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» Exact minimisation of path-related objective functions for binary decision diagrams
[Link to the homepage of the journal]
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Autor:
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Rüdiger Ebendt, Rolf Drechsler |
| Journal: |
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IEE Proceedings Computer & Digital Techniques |
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Volume 153, Number 4, pp. 231-242, July |
Year:
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2006
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» Testability of SPP Three-Level Logic Networks in Static Fault Models
[Link to the homepage of the journal]
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Autor:
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Valentina Ciriani, Anna Bernasconi, Rolf Drechsler |
| Journal: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 25, Number 10, pp. 2241-2248, October |
Year:
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2006
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» The Effect of Improved Lower Bounds in Dynamic BDD Reordering
[Link to the homepage of the journal]
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Autor:
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Rüdiger Ebendt, Rolf Drechsler |
| Journal: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 25, Number 5, pp. 902-909, May |
Year:
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2006
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