Homepage Sitemap Contact




Home « Publications « Journals

sort: [ Title ] [ Author ] [ Journal ] [ Year ]
Suche nach:




» Analyzing SystemC Designs: SystemC Analysis Approaches for Varying Applications
[Link to the homepage of the journal]







Autor:

Jannis Stoppe, Rolf Drechsler
Journal:
Sensors
Details:
Volume (issue) 15(5), pages 10399-10421
Year:


2015






» Transaction-based online debug for NoC-based multiprocessor SoCs
[Link to the homepage of the journal]







Autor:

Mehdi Dehbashi, Görschwin Fey
Journal:
Microprocessors and Microsystems (MICPRO)
Details:
39(3): 157-166
Year:


2015






» Scalable One-Pass Synthesis for Digital Microfluidic Biochips
[Link to the homepage of the journal]







Autor:

Robert Wille, Oliver Keszöcze, Tobias Boehnisch, Alexander Kroker, Rolf Drechsler
Journal:
IEEE Design & Test of Computers
Details:
Volume 32, Issue 66, Pages 41—50
Year:


2015






» QMDDs: Efficient Quantum Function Representation and Manipulation
[Link to the homepage of the journal]







Autor:

Philipp Niemann, Robert Wille, D. Michael Miller, Mitchell A. Thornton, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 35, Number 1, pp. 86-99
DOI: 10.1109/TCAD.2015.2459034
Year:


2016






» Embedding of Large Boolean Functions for Reversible Logic
[Link to the homepage of the journal]







Autor:

Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler
Journal:
Journal on Emerging Technologies in Computing Systems (JETC)
Details:
Volume 12, Issue 4
Preprint available at arXiv 1408.3586
Year:


2015






» Ancilla-free synthesis of large reversible functions using binary decision diagrams
[Link to the homepage of the journal]







Autor:

Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler
Journal:
Journal of Symbolic Computation
Details:
accepted, preprint available at arXiv 1408.3955
Year:


2015






» Benefits of illustrations and videos for technical documentations
[Link to the homepage of the journal]







Autor:

Cornelia Große, Lisa Jungmann, Rolf Drechsler
Journal:
Computers in Human Behavior
Details:
Volume 45, April 2015, Pages 109–120
DOI: 10.1016/j.chb.2014.11.095
Year:


2015






» Incorporating User Preferences in Many-Objective Optimization using Relation epsilon-Preferred
[Link to the homepage of the journal]







Autor:

Nicole Drechsler, André Sülflow, Rolf Drechsler
Journal:
Natural Computing
Details:
Volume 14, Issue 3, pp 469-483
Year:


2015






» Exact Reordering of Circuit Lines for Nearest Neighbor Quantum Architectures
[Link to the homepage of the journal]







Autor:

Robert Wille, Aaron Lye, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 33, Number 12, pp. 1818-1831
DOI: 10.1109/TCAD.2014.2356463
Year:


2014






» A Simulation Based Approach for Automated Feature Localization
[Link to the homepage of the journal]







Autor:

Jan Malburg, Alexander Finder, Görschwin Fey
Journal:
IEEE Trans. on CAD of Integrated Circuits and Systems
Details:
Volume:33, Issue: 12, Pages 1886-1899 DOI: 10.1109/TCAD.2014.2360462 Link
Year:


2014






» Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets






Autor:

Stephan Eggersglüß
Journal:
Journal of Electronic Testing: Theory and Applications
Details:
Volume 30, Number 5, pp. 557-567
Year:


2014






» Latency Analysis for Sequential Circuits






Autor:

Alexander Finder, André Sülflow, Görschwin Fey
Journal:
IEEE Trans. on CAD of Integrated Circuits and Systems
Details:
Volume 33, Number 4, pp. 643-647, DOI: 10.1109/TCAD.2013.2292501
Year:


2014






» Special Issue on Reversible Computation
[Link to the homepage of the journal]







Autor:

Robert Wille, Rolf Drechsler, Mehdi . B. Tahoori (editors)
Journal:
Journal on Emerging Technologies in Computing Systems (JETC)
Details:
Volume 11, Number 2
Year:


2014






» An effective fault ordering heuristic for SAT-based dynamic test compaction techniques
[Link to the homepage of the journal]







Autor:

Stephan Eggersglüß, Rolf Drechsler
Journal:
it-Information Technology
Details:
Volume 56, Number 4, pp. 157-164
Special Issue
Year:


2014






» Testing integrated circuits
[Link to the homepage of the journal]







Autor:

Rolf Drechsler
Journal:
it-Information Technology
Details:
Volume 56, Number 4, pp. 148-149
Special Issue
Year:


2014






» Finite controlled invariants for sampled switched systems
[Link to the homepage of the journal]







Autor:

Laurent Fribourg, Ulrich Kühne, Romain Soulat
Journal:
Formal Methods in System Design
Details:
online, DOI: 10.1007/s10703-014-0211-2
Year:


2014






» Learning to solve story problems – supporting transitions between reality and mathematics
[Link to the homepage of the journal]







Autor:

Cornelia Große
Journal:
European Journal of Psychology of Education
Details:
Volume 29, Number 4, pp 619-634. DOI: 10.1007/s10212-014-0217-6
Year:


2014






» Mathematics learning with multiple solution methods: effects of types of solutions and learners’ activity
[Link to the homepage of the journal]







Autor:

Cornelia Große
Journal:
Instructional Science
Details:
Volume 42, Number 5, pp 715-745. DOI: 10.1007/s11251-014-9312-y
Year:


2014






» Upper bounds for reversible circuits based on Young subgroups
[Link to the homepage of the journal]







Autor:

Nabila Abdessaied, Mathias Soeken, Michael Kirkedal Thomsen, Rolf Drechsler
Journal:
Information Processing Letters
Details:
Volume 114, Number 06 (June 2014), pp. 282-286. DOI: 10.1016/j.ipl.2014.01.003
Year:


2014






» Search-based testing using constraint-based mutation
[Link to the homepage of the journal]







Autor:

Jan Malburg, Gordon Fraser
Journal:
Software Testing, Verification and Reliability
Details:
Volume 24, Issue 6, pages 472–495, September 2014, DOI: 10.1002/stvr.1508 Link
Year:


2013 (online)






» Considering Nearest Neighbor Constraints of Quantum Circuits at the Reversible Circuit Level






Autor:

Robert Wille, Aaron Lye, Rolf Drechsler
Journal:
Quantum Information Processing
Details:
DOI: http://dx.doi.org/10.1007/s11128-013-0642-5
Year:


2013






» Quantum circuits employing roots of the Pauli matrices
[Link to the homepage of the journal]







Autor:

Mathias Soeken, D. Michael Miller, Rolf Drechsler
Journal:
Physical Review A
Details:
Volume 88, 042322, 2013, DOI: 10.1103/PhysRevA.88.042322
Year:


2013






» Trading Off Circuit Lines and Gate Costs in the Synthesis of Reversible Logic
[Link to the homepage of the journal]







Autor:

Robert Wille, Mathias Soeken, D. Michael Miller, Rolf Drechsler
Journal:
INTEGRATION, the VLSI Journal
Details:
Volume 47, Number 2, pp. 284-294, DOI: 10.1016/j.vlsi.2013.08.002
Year:


2014






» Speci fication-Driven Model Transformation Testing
[Link to the homepage of the journal]







Autor:

Esther Guerra, Mathias Soeken
Journal:
Software and Systems Modeling
Details:
accepted
Year:


2013






» A Formal Model for Embedded Brain Reading
[Link to the homepage of the journal]







Autor:

Elsa Andrea Kirchner, Rolf Drechsler
Journal:
Industrial Robot: an International Journal
Details:
Volume 40, Issue 6, pp. 530-540
Year:


2013






» Debug Automation for Logic Circuits Under Timing Variations
[Link to the homepage of the journal]







Autor:

Mehdi Dehbashi, Görschwin Fey
Journal:
IEEE Design & Test of Computers
Details:
Volume 30, Issue 6, pp. 60-69
Year:


2013






» Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits
[Link to the homepage of the journal]







Autor:

Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler
Journal:
Multiple-Valued Logic and Soft Computing
Details:
Volume 21, Number 5-6, 2013, pp. 627-640
Year:


2013






» Parametric Verification and Test Coverage for Hybrid Automata using the Inverse Method
[Link to the homepage of the journal]







Autor:

Laurent Fribourg, Ulrich Kühne
Journal:
International Journal of Foundations of Computer Science (IJFCS)
Details:
Volume 24, Number 02 (February 2013), pp. 233-250
Year:


2013






» RevKit: An Open Source Toolkit for the Design of Reversible Circuits
[Link to the homepage of the journal]







Autor:

Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Journal:
Reversible Computation 2011 (Series: Lecture Notes in Computer Science)
Details:
Volume 7165, Third International Workshop, RC 2011, Revised Papers, pp. 64-76
Year:


2012






» Automated Design Debugging in a Testbench-Based Verification Environment
[Link to the homepage of the journal]







Autor:

Mehdi Dehbashi, André Sülflow, Görschwin Fey
Journal:
Embedded Hardware Design - Microprocessors and Microsystems (MICPRO)
Details:
Volume 37, Issue 2, pp. 206-217
Year:


2013






» Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis






Autor:

Daniel Große, Görschwin Fey, Rolf Drechsler
Journal:
Electronic Communications of the EASST
Details:
Volume 62, 13 pages
Year:


2013






» Automatic TLM Fault Localization for SystemC
[Link to the homepage of the journal]







Autor:

Hoang M. Le, Daniel Große, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 31, Number 8, pp. 1249-1262,
DOI: 10.1109/TCAD.2012.2188800
Year:


2012






» Special Issue on Reversible Computation
[Link to the homepage of the journal]







Autor:

Rolf Drechsler, Irek Ulidowski, Robert Wille (editors)
Journal:
Multiple-Valued Logic and Soft Computing
Details:
Volume 18, Number 1
Year:


2012






» RevKit: A Toolkit for Reversible Circuit Design
[Link to the homepage of the journal]







Autor:

Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Journal:
Multiple-Valued Logic and Soft Computing
Details:
Volume 18, Number 1, pp. 55-65
Year:


2012






» A Highly Fault-Efficient SAT-Based ATPG Flow
[Link to the homepage of the journal]







Autor:

Stephan Eggersglüß, Rolf Drechsler
Journal:
IEEE Design & Test of Computers
Details:
Volume 29, Issue 4 (July/August), pp. 63-70
Year:


2012






» Efficient Data Structures and Methodologies for SAT-based ATPG providing High Fault Coverage in Industrial Application
[Link to the homepage of the journal]







Autor:

Stephan Eggersglüß, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 30, Number 9, pp. 1411-1415,
DOI: 10.1109/TCAD.2011.2152450
Year:


2011






» Effective Robustness Analysis using Bounded Model Checking Techniques
[Link to the homepage of the journal]







Autor:

Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 30, Number 8, pp. 1239-1252 DOI: 10.1109/TCAD.2011.2120950
Year:


2011






» Synthesis of Quantum Circuits for Linear Nearest Neighbor Architectures
[Link to the homepage of the journal]







Autor:

Mehdi Saeedi, Robert Wille, Rolf Drechsler
Journal:
Quantum Information Processing
Details:
Volume 10, Number 3, pp. 355-377
DOI: 10.1007/s11128-010-0201-2
Year:


2011






» Debugging Reversible Circuits
[Link to the homepage of the journal]







Autor:

Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
Journal:
INTEGRATION, the VLSI Journal
Details:
Volume 44, Number 1, pp. 51-61, January
DOI: 10.1016/j.vlsi.2010.08.002
Year:


2011






» BDD-Based Synthesis of Reversible Logic
[Link to the homepage of the journal]







Autor:

Robert Wille, Rolf Drechsler
Journal:
International Journal of Applied Metaheuristic Computing (IJAMC)
Details:
Volume 1, Number 4, pp. 25-41
Year:


2010






» Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen
[Link to the homepage of the journal]







Autor:

Görschwin Fey, Andre Sülflow, Stefan Frehse, Rolf Drechsler
Journal:
it-Information Technology
Details:
Volume 52, Number 4, pp. 216-223
PDF Download
Year:


2010






» Towards Fully Automatic Synthesis of Embedded Software
[Link to the homepage of the journal]







Autor:

Ulrich Kühne, Daniel Große, Rolf Drechsler
Journal:
IEEE Embedded Systems Letters
Details:
Volume 2, Number 3, pp. 53-57, September
Year:


2010






» Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic
[Link to the homepage of the journal]







Autor:

Robert Wille, Rolf Drechsler
Journal:
Electronic Notes in Theoretical Computer Science
Details:
Volume 253, Number 6, pp. 57-70
DOI: 10.1016/j.entcs.2010.02.006
Year:


2010






» Incremental Solving Techniques for SAT-based ATPG
[Link to the homepage of the journal]







Autor:

Daniel Tille, Stephan Eggersglüß, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 29, Number 7, pp. 1125-1130, July
Year:


2010






» Synthese reversibler Logik
[Link to the homepage of the journal]







Autor:

Robert Wille, Rolf Drechsler
Journal:
it-Information Technology
Details:
Volume 52, Number 1, pp. 30-38
PDF Download
Year:


2010






» MONSOON: SAT-based ATPG for Path Delay Faults Using Multiple-Valued Logics
[Link to the homepage of the journal]







Autor:

Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Rolf Drechsler
Journal:
Journal of Electronic Testing: Theory and Applications
Details:
Volume 26, Number 3 / June, pp. 307-322
Pdf download (Preliminary Version)
The final publication is available at www.springerlink.com
Year:


2010






» Overcoming the limitations of data introspection for SystemC
[Link to the homepage of the journal]







Autor:

Christian Genz, Rolf Drechsler
Journal:
EDA Tech Forum
Details:
Volume 6, Issue 5, Pages 30-34 (December 2009)
Year:


2009






» Weighted A* search - unifying view and application
[Link to the homepage of the journal]







Autor:

Rüdiger Ebendt, Rolf Drechsler
Journal:
Artificial Intelligence
Details:
Volume 173, Issue 15, Pages 1367-1456 (September 2009)
Year:


2009






» Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
[Link to the homepage of the journal]







Autor:

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille
Journal:
it - information technology
Details:
Volume 51, Number 2, pp. 102-111
Pdf download
Year:


2009






» Exact Synthesis of Elementary Quantum Gate Circuits
[Link to the homepage of the journal]







Autor:

Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Journal:
Multiple-Valued Logic and Soft Computing
Details:
Volume 15, Number 4, pp. 283-300
Year:


2009






» Advanced Verification by Automatic Property Generation
[Link to the homepage of the journal]







Autor:

Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke
Journal:
IET Computers & Digital Techniques
Details:
Volume 3, Issue 4, pp. 338-353, July
Year:


2009






» Exact Multiple Control Toffoli Network Synthesis with SAT Techniques
[Link to the homepage of the journal]







Autor:

Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 28, Number 5, pp. 703-715, May
DOI: 10.1109/TCAD.2009.2017215
Year:


2009






» Modeling and Proving Completeness in Formal Verification of Counting Heads
[Link to the homepage of the journal]







Autor:

Sebastian Kinder, Rolf Drechsler
Journal:
Software Tools for Technology Transfer (STTT)
Details:
Springer, Volume 10, Number 6, pp. 521 - 534
Year:


2008






» On Acceleration of SAT-based ATPG for Industrial Designs
[Link to the homepage of the journal]







Autor:

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Daniel Tille
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 27, Number 7, pp. 1329-1333, July
Year:


2008






» Improved SAT-based Reachability Analysis with Observability Don’t Cares
[Link to the homepage of the journal]







Autor:

Sean Safarpour, Andreas Veneris and Rolf Drechsler
Journal:
Journal on Satisfiability, Boolean Modeling and Computation (JSAT)
Details:
Volume 5, pp. 1-25, Special Volume on Application of Constraints to Formal Verification
Year:


2008






» On the Construction of Small Fully Testable Circuits with Low Depth
[Link to the homepage of the journal]







Autor:

Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler
Journal:
Embedded Hardware Design - Microprocessors and Microsystems (MICPRO)
Details:
Special Issue, Volume 32, Issues 5-6, pp. 263-269
Year:


2008






» Logic Minimization and Testability of 2-SPP Networks
[Link to the homepage of the journal]







Autor:

Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 27, Number 7, pp. 1190-1202, July
Year:


2008






» Analyzing Functional Coverage in Bounded Model Checking
[Link to the homepage of the journal]







Autor:

Daniel Große, Ulrich Kühne, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 27, Number 7, pp. 1305-1314, July
Year:


2008






» Automatic Fault Localization for Property Checking
[Link to the homepage of the journal]







Autor:

Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 27, Number 6, pp. 1138-1149, June
Year:


2008






» BDD-based Verification of Scalable Designs
[Link to the homepage of the journal]







Autor:

Daniel Große, Rolf Drechsler
Journal:
Facta Universitatis, Series: Electronics and Energetics
Details:
Volume 20, Number 3, pp. 367-379
Year:


2007






» Building Free Binary Decision Diagrams Using SAT Solvers
[Link to the homepage of the journal]







Autor:

Robert Wille, Görschwin Fey, Rolf Drechsler
Journal:
Facta Universitatis, Series: Electronics and Energetics
Details:
Volume 20, Number 3, pp. 381-394,
Year:


2007






» An Integrated Approach for Combining BDDs and SAT Provers
[Link to the homepage of the journal]







Autor:

Rolf Drechsler, Görschwin Fey, Sebastian Kinder
Journal:
Facta Universitatis, Series: Electronics and Energetics
Details:
Volume 20, Number 3, pp. 415-436
Year:


2007






» Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic






Autor:

Sujan Pandey, Manfred Glesner
Journal:
IEEE Transaction on Very Large Scale Integration (VLSI) Systems
Details:
Volume 15, Number 10, pp. 1111-1124, October
Year:


2007






» Technische Dokumentation von Soft- und Hardware in eingebetteten Systemen
[Link to the homepage of the journal]







Autor:

Beate Muranko, Rolf Drechsler
Journal:
it - information technology
Details:
Number 2, pp. 110-117
Pdf download
Year:


2007






» Exact minimisation of path-related objective functions for binary decision diagrams
[Link to the homepage of the journal]







Autor:

Rüdiger Ebendt, Rolf Drechsler
Journal:
IEE Proceedings Computer & Digital Techniques
Details:
Volume 153, Number 4, pp. 231-242, July
Year:


2006






» Testability of SPP Three-Level Logic Networks in Static Fault Models
[Link to the homepage of the journal]







Autor:

Valentina Ciriani, Anna Bernasconi, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 25, Number 10, pp. 2241-2248, October
Year:


2006






» The Effect of Improved Lower Bounds in Dynamic BDD Reordering
[Link to the homepage of the journal]







Autor:

Rüdiger Ebendt, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 25, Number 5, pp. 902-909, May
Year:


2006






» Minimizing the Number of Paths in BDDs - Theory and Algorithm
[Link to the homepage of the journal]







Autor:

Görschwin Fey, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 25, Number 1, pp. 4-11, January
Year:


2006






» Combining Ordered Best-First Search with Branch and Bound for Exact BDD Minimization
[Link to the homepage of the journal]







Autor:

Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 24, Number 10, pp. 1515-1529, October
Year:


2005






» System Level Validation Using Formal Techniques
[Link to the homepage of the journal]







Autor:

Rolf Drechsler, Daniel Große
Journal:
IEE Proceedings Computer & Digital Techniques, Special Issue on Embedded Microelectronic Systems: Status and Trends
Details:
Volume 152, Number 3, pp. 393-406, May
Year:


2005






» Generic Implementation of Multi-Valued Decision Diagram Packages






Autor:

Rolf Drechsler, Dragan Jankovic, Radomir Stankovic
Journal:
Multiple-Valued Logic and Soft Computing
Details:
Volume 11, Numbers 1-2, pp. 1-18
Year:


2005






» Project-Based Learning in Student Teams in Computer Science Education
[Link to the homepage of the journal]







Autor:

Andreas Breiter, Görschwin Fey, Rolf Drechsler
Journal:
Facta Universitatis, Series: Electronics and Energetics
Details:
Volume 18, Number 2, August, pp. 165-180.
Year:


2005






» Synthesis of Fully Testable Circuits from BDDs
[Link to the homepage of the journal]







Autor:

Rolf Drechsler, Junhao Shi, Görschwin Fey
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 23, Number 3, March
Year:


2004






» Methods for Construction of Recursive Algorithms for Reed-Mulle-Fourier Polarity Matrices Calculation






Autor:

Dragan Jankovic, Rolf Drechsler
Journal:
Multiple-Valued Logic and Soft Computing
Details:
Volume 10, Numbers 1, pp. 29-50
Year:


2004






» Using Word-Level Information in Formal Hardware Verification
[Link to the homepage of the journal]







Autor:

Rolf Drechsler
Journal:
Automation and Remote Control
Details:
Year:


Volume 65, Issue 6, pp. 963-977, June 2004






» An Improved Branch and Bound Algorithm for Exact BDD Minimization
[Link to the homepage of the journal]







Autor:

Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 22, Number 12, pp. 1657-1663, December
Year:


2003






» Recursive Bi-Partitioning of Netlists for Large Number of Partitions
[Link to the homepage of the journal]







Autor:

Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst
Journal:
Journal of Systems Architecture - the Euromicro Journal
Details:
Volume 49, pp. 521-528
Year:


2003






» Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC
[Link to the homepage of the journal]







Autor:

Daniel Große, Rolf Drechsler
Journal:
it - information technology
Details:
Number 4, pp. 219-226, August
Year:


2003






» Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams
[Link to the homepage of the journal]







Autor:

Wolfgang Günther, Rolf Drechsler
Journal:
IEEE Transactions on Computers
Details:
Volume 52, Number 9, pp. 1196-1209, September
Year:


2003






» Exact Routing with Search Space Reduction
[Link to the homepage of the journal]







Autor:

Frank Schmiedle, Rolf Drechsler, Bernd Becker
Journal:
IEEE Transactions on Computers
Details:
Volume 52, Number 6, pp. 815-825, June
Year:


2003






» Computer Architecture Core of Knowledge for Computer Science Studies






Autor:

M. Stojcev, I. Milentijevic, D. Kehagias, Rolf Drechsler, M. Gusev
Journal:
Cyprus Computer Society Journal
Details:
Volume I, Edition 4, April
Year:


2003






» Polynomial Formal Verification of Multipliers
[Link to the homepage of the journal]







Autor:

Martin Keim, Rolf Drechsler, Bernd Becker, Michael Martin, Paul Molitor
Journal:
Formal Methods in System Design: An International Journal
Details:
Volume 22, Issue 1, pp. 39-58
Year:


2003






» Low Power Optimization Techniques for BDD Mapped Circuits Using Temporal Correlation
[Link to the homepage of the journal]







Autor:

Rolf Drechsler, Mikael Kerttu, Per Lindgren, Mitch Thornton
Journal:
Canadian Journal of Electrical and Computer Engineering
Details:
Volume 27, Number 4, pp. 159-164, October
Year:


2002






» Minimization of Word-level Decision Diagrams
[Link to the homepage of the journal]







Autor:

Rolf Drechsler, Wolfgang Günther, Stefan Höreth.
Journal:
INTEGRATION, the VLSI Journal
Details:
Volume 33, Issue 1-2, pp. 39-70
Year:


2002






» Minimization of Free BDDs
[Link to the homepage of the journal]







Autor:

Wolfgang Günther, Rolf Drechsler
Journal:
INTEGRATION, the VLSI Journal
Details:
Volume 32, Issue 1-2, pp. 41-59
Year:


2002






» Verifying Integrity of Decision Diagrams
[Link to the homepage of the journal]







Autor:

Rolf Drechsler
Journal:
INTEGRATION, the VLSI Journal
Details:
Volume 32, Issue 1-2, pp. 61-75
Year:


2002






» Heuristic Learning based on Genetic Programming
[Link to the homepage of the journal]







Autor:

Frank Schmiedle, Nicole Drechsler, Daniel Große and Rolf Drechsler
Journal:
Genetic Programming and Evolvable Machines
Details:
Volume 3, pp. 363-388, December
Year:


2002






» Dynamic Re-Encoding During MDD Minimization
[Link to the homepage of the journal]







Autor:

Frank Schmiedle, Wolfgang Günther, Rolf Drechsler
Journal:
Multiple-Valued Logic - An International Journal
Details:
Volume 8, Numbers 5-6, pp. 625-643
Year:


2002






» History-based Dynamic BDD Minimization
[Link to the homepage of the journal]







Autor:

Rolf Drechsler, Wolfgang Günther
Journal:
INTEGRATION, the VLSI Journal
Details:
Volume 31, Issue 1, pp. 51-63
Year:


2001






» Äquivalenzvergleich digitaler Schaltungen im industriellen Umfeld






Autor:

Rolf Drechsler
Journal:
it+ti - Informationstechnik und Technische Informatik
Details:
Oldenbourg Wissenschaftsverlag, Number 4, pp. 200-205
Year:


2001






» Fault Simulation in Multi-Valued Logic Networks
[Link to the homepage of the journal]







Autor:

Rolf Drechsler, Martin Keim, Bernd Becker
Journal:
Multiple-Valued Logic - An International Journal
Details:
Volume 7, Numbers 1-2, pp. 25-47
Year:


2001






» Binary Decision Diagrams in Theory and Practice
[Link to the homepage of the journal]







Autor:

Rolf Drechsler, Detlef Sieling
Journal:
Software Tools for Technology Transfer (STTT)
Details:
Springer, Number 3, pp. 112-136
Year:


2001






» Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
[Link to the homepage of the journal]







Autor:

Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker
Journal:
Journal of Electronic Testing, Theory and Application (JETTA)
Details:
No. 17, pp. 37-51, February
Year:


2001






» Decision Diagram Method for Calculation of Pruned Walsh Transform
[Link to the homepage of the journal]







Autor:

Dragan Jankovic, Radomir Stankovic, Rolf Drechsler
Journal:
IEEE Transactions on Computers
Details:
Volume 50, Number 2, pp. 147-157, February
Year:


2001






» Using Lower Bounds during Dynamic BDD Minimization
[Link to the homepage of the journal]







Autor:

Rolf Drechsler, Wolfgang Günther, Fabio Somenzi
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 20, Number 1, pp. 51-57, January
Year:


2001






» ACTion: Combining Logic Synthesis and Technology Mapping for MUX based FPGAs
[Link to the homepage of the journal]







Autor:

Wolfgang Günther and Rolf Drechsler.
Journal:
Journal of Systems Architecture - the Euromicro Journal
Details:
Volume 46, Issue 14, pp. 1321-1334, December
Year:


2000






» Boolean Function Representation and Spectral Characterization Using AND/OR Graphs
[Link to the homepage of the journal]







Autor:

Alenka Zuzek, Rolf Drechsler, Mitch Thornton
Journal:
INTEGRATION, the VLSI Journal
Details:
Volume 29, Issue 2, pp. 101-116, September
Year:


2000






» Genetic Algorithm for Minimization of fixed polarity Reed-Muller expressions






Autor:

Rolf Drechsler, Bernd Becker and Nicole Drechsler
Journal:
IEE Proceedings Computers and Digital Techniques
Details:
Volume 147, Number 5, September
Year:


2000






» On the Computational Power of Linearly Transformed BDDs
[Link to the homepage of the journal]







Autor:

Wolfgang Günther, Rolf Drechsler
Journal:
Information Processing Letters
Details:
Volume 75, Nummer 3, pp. 119-125, August
Year:


2000






» Fast Exact Minimization of BDDs
[Link to the homepage of the journal]







Autor:

Rolf Drechsler, Nicole Drechsler, Wolfgang Günther
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 19, Number 3, pp. 384-389, March
Year:


2000






» Pseudo Kronecker Expressions for Symmetric Functions
[Link to the homepage of the journal]







Autor:

Rolf Drechsler
Journal:
IEEE Transactions on Computers
Details:
Volume 48, Number 9, pp. 987-990, September
Year:


1999






» Testability of 2-Level AND/EXOR Circuits
[Link to the homepage of the journal]







Autor:

Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker
Journal:
Journal of Electronic Testing, Theory and Application (JETTA)
Details:
Volume 14, Number 3, pp. 173-192, June
Year:


1999






» BDD Minimization Using Symmetries
[Link to the homepage of the journal]







Autor:

Christoph Scholl, Dirk Möller, Paul Molitor, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 18, Number 2, pp. 81-100, February
Year:


1999






» On Variable Ordering and Decomposition Type Choice in OKFDDs
[Link to the homepage of the journal]







Autor:

Rolf Drechsler, Bernd Becker, Andrea Jahnke
Journal:
IEEE Transactions on Computers
Details:
Volume 47, Number 12, December
Year:


1998






» High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design
[Link to the homepage of the journal]







Autor:

Rahebeh Niaraki Asli, Saeideh Shirinzadeh
Journal:
Journal of Electronic Testing
Details:
Volume 29, Issue 4, pp 537-544
Year:


2013








back







Deutsch







Sitemap Kontakt

ISMVL2014 DUHDE