Together with the company Concept Engineering algorithms and technologies for visualization of circuits and systems are developed.

In the BMBF funded project URANOS analysis methods for the design flow are investigated which take possible application contexts into consideration.

In the project it is studied how SAT algorithms can be used in automatic test pattern generation.

Das Projekt MAYA wird vom BMBF gefördert, die Arbeitsgruppe ist hier Unterauftragnehmer von Philips, Hamburg. Ziel des Projektes ist die Verbesserung des Testens von Schaltkreisen auf funktionale Fehler, die während der Produktion entstanden sind. Insbesondere sollen die Testkosten gesenkt und die Testzeiten reduziert werden.

Detailed description is only available in german.

Modern Method in formal verification

In the project the synthesis of quantum circuits is improved. Furthermore the reliablity of quantum circuits is ensured by methods known from verification and test.

Techniques to ensure fault tolerance - or robustness - gain an increasing importance in circuit design. Methods to automatically prove such robustness by using formal methods are investigated in the research project.