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» NANOTEST
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The project is concerned with the development of new methods for the test generation of digital circuits in low-Nanometer process.

Contact: Rolf Drechsler, Stephan Eggersglüß
 
» Automated Test Generation for Multi-core Virtual Prototypes
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The project develops new methods for automated generation of tests with high coverage for multi-core virtual prototypes.

Contact: Prof. Dr. Rolf Drechsler, Dr. Daniel Große, Dr. Hoang M. Le
 
» Faster Formal Verification with Reverse Engineering
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The project develops new methods for reverse engineering a circuit aiming at increase the efficiency of formal verification.

Contact: Dr. Mathias Soeken
 
» EffektiV: Efficient Fault Simulation using Virtual Prototypes for Qualification of Intelligent Motion-Control-Systems in Industrial Automation
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The project develops high-level fault simulation techniques using virtual prototypes.

For more information see:
https://www.edacentrum.de/effektiv/


Contact: Prof. Dr. Rolf Drechsler, Dr. Daniel Große, Dr. Hoang M. Le
 
» Development of a Modular Framework for Automatic Validation and Verification of UML/OCL Models
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In the project, a modular framework shall be developed which can generically be applied to solve verification tasks in the UML/OCL-based design.

Contact: Dr. Robert Wille
 
» Synthesis of Reversible Circuits using Probabilistic Methods
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This project investigtes the synthesis of reversible circuits. We are cooperating thereby with the Bengal Engineering & Science University (India).

Contact: Prof. Dr. Rolf Drechsler, Dr. Robert Wille
 
» Utilizing Reversible Logic for Low Power Design
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This project investigtes the utilization of a new computing paradigm, namely reversible logic, for low power design. We are cooperating thereby with the Purdue University (USA).

Contact: Prof. Dr. Rolf Drechsler, Dr. Robert Wille
 
» Fostering Competencies in Mathematical Modeling
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In the project methods to foster mathematical competencies are developed and their effectiveness is experimentally evaluated.

Contact: Dr. Cornelia Große
 
» High Quality Test Generation for Small Delay Defects
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Focus of this project is the development of new methods for the generation of high-quality tests. Special attention is paid to the application of formal methods like Boolean Satisfiability (SAT) or Pseudo-Boolean Optimization.

Contact: Prof. Dr. Rolf Drechsler, Dr. Stephan Eggersglüß
 
» SolVerTec – Solution Verification Technologies
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The spin-off project SolVerTec aims at developing an automatic debugging tool.

For more information see: http://www.solvertec.de


Contact: Prof. Dr. Rolf Drechsler, Dr. Görschwin Fey, Dr. Daniel Große, Dr. Andre Sülflow
 
» VisES: Visualization Technology for Complex System Descriptions aiming for the Improvement of the Safety and Robustness of Electronic Systems
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The project VisES aims for the development of new visualization technologies for system designs at the Electronic System Level (ESL).

Contact: Prof. Dr. Rolf Drechsler, Dr. Robert Wille
 
» RESCAR 2.0 - robust design of new electronic components for applications in the field of electromobility
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The project develops analytical methods for the accurate estimation of the timing behavior of digital electronic components.

Contact: Prof. Dr. Rolf Drechsler, Dr. Stephan Eggersglüß
 
» Synthesis and Optimization of Quantum Logic
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Within this project, a new synthesis flow for quantum logic should be developed. We are cooperating thereby with the University of Victoria (Canada).

Contact: Prof. Dr. Rolf Drechsler
 
» Debugging Embedded Systems
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Junior Research Group funded by the DFG within the Emmy-Noether-Programme.

Contact: Dr. Görschwin Fey
 
» DIAMOND - Diagnosis, Error Modelling and Correction for Reliable Systems Design
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DIAMOND focusses on debugging support for design bugs and the analysis of physical faults.

For further deatils see the webpage of DIAMOND:
http://www.fp7-diamond.eu


Contact: Prof. Dr. Rolf Drechsler, Dr. Görschwin Fey
 
» SANITAS
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The project develops verification methods on a high level of abstraction.

Contact: Prof. Dr. Rolf Drechsler, Dr. Daniel Große
 
» Quality-driven Synthesis of Large Functions in Reversible Logic
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Traditional technologies more and more reach their limits. Reversible logic provides an alternative with promising applications e.g. in quantum computation or low-power design. Unfortunately, research in this area still is at the beginning. In the project new methods to synthesize reversible logic are developed. Thereby, the focus is on how to efficiently handle large functions resulting in complex circuits.

Contact: Prof. Dr. Rolf Drechsler
 
» Quality-driven design of systems with reconfigurable components
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This is a joint project with the OFFIS institute at university of Oldenburg. It addresses new verification problems that are specific to reconfigurable hardware systems.

Contact: Prof. Dr. Rolf Drechsler
 
» Visualization of circuits and systems
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Together with the company Concept Engineering algorithms and technologies for visualization of circuits and systems are developed.

Contact: Prof. Dr. Rolf Drechsler
 
» Analysis Methods for the Design of Application-Robust Nanoelectronic Systems (URANOS)
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In the BMBF funded project URANOS analysis methods for the design flow are investigated which take possible application contexts into consideration.

Contact: Prof. Dr. Rolf Drechsler
 
» Hierarchical and Sequential Information for Boolean Satisfiability in Computer Aided Design of Integrated Circuits
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Methods to exploit problem specific sequential and hierarchical information when solving Boolean satisfiability problems are develeoped and empirically evaluated in this project.

Contact: Prof. Dr. Rolf Drechsler
 
» Reachbility Analysis based on Word Level Provers
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Within this project word-level proof techniques are applied to perform a reachability analysis for circuits.
The exchange project is jointly pursued with the research group of Prof. Andreas Veneris at the University of Toronto.


Contact: Dr. Görschwin Fey
 
» Design Methodology for Embedded Systems
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Within this project design methodology for embedded systems is considered. The project focuses on the promotion of young researchers.
The exchange project is jointly pursued with the research group of Prof. Masahiro Fujita at the University of Tokyo.


Contact: Dr. Görschwin Fey
 
» DeAR: Debugging of circuits using abstraction refinement
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In this project automated debugging techniques for harware will be examined. The goal is to improve the performance by using abstraction and refinement techniques. In this project we cooperate with the LIP6 in Paris.

Contact: Prof. Dr. Rolf Drechsler
 
» Efficient SAT Algorithms for the Generation of Test Patterns
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In the project it is studied how SAT algorithms can be used in automatic test pattern generation.

Contact: Prof. Dr. Rolf Drechsler
 
» Neue Methoden für den Massiv-Parallel-Test im Hochvolumen, Yield Learning und beste Testqualität (MAYA)
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Das Projekt MAYA wird vom BMBF gefördert, die Arbeitsgruppe ist hier Unterauftragnehmer von Philips, Hamburg. Ziel des Projektes ist die Verbesserung des Testens von Schaltkreisen auf funktionale Fehler, die während der Produktion entstanden sind. Insbesondere sollen die Testkosten gesenkt und die Testzeiten reduziert werden.

Contact: Prof. Dr. Rolf Drechsler
 
» HERKULES: Hardware Design Techniques for Zero-Fault-Designs
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Detailed description is only available in german.

Contact: Prof. Dr. Rolf Drechsler
 
» Manipulation of Boolean Functions based on Hybrid Data Structures
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In the project the combination of classical methods to robust hybrid solvers as well as their extension is to a higher abstraction level is examined and experimentally evaluated.

Contact: Prof. Dr. Rolf Drechsler
 
» Verisoft XT
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Modern Method in formal verification

Contact: Prof. Dr. Rolf Drechsler
 
» Synthesis of reliable quantum circuits
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In the project the synthesis of quantum circuits is improved. Furthermore the reliablity of quantum circuits is ensured by methods known from verification and test.

Contact: Prof. Dr. Rolf Drechsler
 
» Formal Robustness Checking
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Techniques to ensure fault tolerance - or robustness - gain an increasing importance in circuit design. Methods to automatically prove such robustness by using formal methods are investigated in the research project.

Contact: Prof. Dr. Rolf Drechsler, Dr. Görschwin Fey
 
» Formal Verification of Circuits using Inforamtion from High-Level Languages
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In the project it is studied how information from high-level descriptions can be used in the formal verification of properties.

Contact: Prof. Dr. Rolf Drechsler
 
» Circuit- and System Verification using Word-Level Information
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In this project data structures are investigated from a theoretical and practical point of view to allow for the use of word-level information in the verification process.

Contact: Prof. Dr. Rolf Drechsler
 
» Debugging in the formal module verification
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In this project debugging techniques in the context of formal module verification are investigated. The project is funded by BMBF and is carried out together with Infineon Technologies AG and Concept Engineering GmbH.

Contact: Prof. Dr. Rolf Drechsler
 
» Implementing Modules and ECTS for Computer Studies
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Implementing Modules and ECTS for Computer Studies

Contact: Prof. Dr. Rolf Drechsler
 
» Efficient Methods for Debugging of Circuits and Systems
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A methodology for a unified view on the design process is developed and applied in this project.

Contact: Prof. Dr. Rolf Drechsler
 
» Test Synthesis of Circuits with small Delay
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In this project a synthesis approach for the automatic generation of testable circuits of small depth is analysed, implemented and applied.

Contact: Prof. Dr. Rolf Drechsler
 
» Pilot Implementation of ECTS
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In this project the status of the ECTS implementation in international comparison is studied.

Contact: Prof. Dr. Rolf Drechsler
 
» Verisoft
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Verisoft is a long-term research project funded by the German Federal Ministry of Education and Research (bmb+f). Project management agency is the German Aerospace Center (DLR). The main goal of the project is the pervasive formal verification of computer systems. The correct functionality of systems, as they are applied, for example, in automotive engineering, in security technology and in the sector of medical technology, are to be mathematically proved.

Contact: Prof. Dr. Rolf Drechsler
 







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