Development of a Continuous Verification Flow for ESL

In the Reinhart Koselleck Project new methods are developed to ensure the correctness of modern circuit and system descriptions in embedded systems.

Contact: Prof. Dr. Rolf Drechsler

In modern circuit and system design the modeling of hardware and (hardware-dependent) software for embedded systems becomes increasingly important. For decades the complexity of systems increased resulting in systems with several hundred millions of components. Design productivity enhancements are only possible with increasing design reuse or modeling on a higher level of abstraction. Thus, the design starts at the Electronic System Level (ESL) and no longer at the Register Transfer Level (RTL). Here, the correctness of the systems becomes the center of attention. However, no continuous methodology exists so far. In this project a continuous verification flow for ESL will be developed. Besides new verification methods the flow will include approaches to automatically generate properties and algorithms to check their completeness. In addition, it will be possible to relate the ESL-properties with properties at lower levels of abstractions (such as RTL). This allows ensuring the correctness from the system-level description down to the logic level.