High Quality Test Generation for Small Delay Defects

Focus of this project is the development of new methods for the generation of high-quality tests. Special attention is paid to the application of formal methods like Boolean Satisfiability (SAT) or Pseudo-Boolean Optimization.

Contact: Prof. Dr. Rolf Drechsler, Dr. Stephan Eggersglüß

Every fabricated chip is subjected to a post-production test to avoid that defective chips are delivered to customers and, by this, could cause failures in operation mode. The test costs, however, are over half of the manufacturing cost now, and test time and the quality of the test patterns are of paramount importance. The test set generation is based on logical fault models and is done by algorithms for Automatic Test Pattern Generation (ATPG). ATPG is a computationally intensive task and efficient search algorithms have to be applied. However, the shrinking feature sizes and increased speed of today's designs lead more and more often to failures which are not covered by the classical fault models. High quality test generation has to be performed for guaranteeing the correctness of the manufactured designs.
However, the application of existing approaches for high-quality test generation causes large overhead which directly results in high test costs. Therefore, new approaches are needed. The development of novel efficient algorithms and techniques for high-quality test generation is - in collaboration with the Duke University (USA) - aim of this project. Special attention is paid to the application of formal methods which promise a high robustness.