FormalEST

The project is concerned with the formal generation of power-safe test patterns for the manufacturing test of digital circuits.

Contact: Rolf Drechsler

FormalEST – The test power consumption during the test of manufactured circuits is a severe problem leading to hot spots and false test results. The project is concerned with the development of new methods which are able generate power-safe tests and preventing chip damages or test escapes.

2016 – 2019

Corresponding person: Prof. Dr. Rolf Drechsler

Funded by the German Research Foundation (DFG) under contract number EG 290/5-1.