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Home « Team « Publications
» Publications of
Daniel Große
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BOOKS |
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» Quality-Driven SystemC Design
[Read more about this book!]
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Publisher: |
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Springer |
Author:
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Daniel Große, Rolf Drechsler |
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Hardcover |
Year:
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2010
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» EXplayN - Strategieoptimierung und Analyse ausgewählter Spielprobleme
[Read more about this book!]
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Publisher: |
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Shaker Verlag |
Author:
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Daniel Große, Andre Sülflow, Nicole Drechsler (Hrsg.) |
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gebunden |
Year:
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2008
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» SATRIX - Algorithmen für Boolesche Erfüllbarkeit
[Read more about this book!]
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Publisher: |
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Shaker Verlag |
Author:
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Daniel Große, Görschwin Fey, Rolf Drechsler (Hrsg.) |
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Gebunden |
Year:
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2007
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BOOK CONTRIBUTIONS |
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| » Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis |
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Author:
| Daniel Große, Görschwin Fey, Rolf Drechsler
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| Editor: | Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus |
| Booktitle: | Design and Test Technology for Dependable Systems-on-Chip |
| Publisher: | Information Science Reference |
| Sites: | 119-129 |
| Year: | 2011 |
| Format: | Hardcover |
| » SMT-based Stimuli Generation in the SystemC Verification Library |
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Author:
| Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler
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| Editor: | Dominique Borrione |
| Booktitle: | Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s: Selected Contributions on Specification, Design, and Verification from FDL 2009 |
| Publisher: | Springer |
| Sites: | 227-244 |
| Year: | 2010 |
| Format: | Hardcover |
| » Debugging Contradictory Constraints in Constraint-based Random Simulation |
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Author:
| Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
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| Editor: | Martin Radetzki |
| Booktitle: | Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL'08 |
| Publisher: | Springer |
| Sites: | 273-290 |
| Year: | 2009 |
| Format: | gebunden |
| » SWORD: A SAT like Prover Using Word Level Information |
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Author:
| Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
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| Editor: | Ricardo Reis, Vincent Mooney, Paul Hasler |
| Booktitle: | VLSI-SoC: Advanced Topics on Systems on a Chip:
A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip |
| Publisher: | Springer |
| Sites: | 175-192 |
| Year: | 2009 |
| Format: | Hardcover |
| » Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques |
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Author:
| Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler
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| Editor: | Eugenio Villar |
| Booktitle: | Embedded Systems Specification and Design Languages: Selected contributions from FDL'07 |
| Publisher: | Springer |
| Sites: | 73-86 |
| Year: | 2008 |
| Format: | gebunden |
| » Processor Verification |
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Author:
| Daniel Große, Robert Siegmund, Rolf Drechsler
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| Editor: | Paolo Ienne, Rainer Leupers |
| Booktitle: | Customizable Embedded Processors |
| Publisher: | Elsevier |
| Sites: | 281-302 |
| Year: | 2006 |
| Format: | gebunden |
| » System-level validation using formal techniques |
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Author:
| Rolf Drechsler, Daniel Große
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| Editor: | Bashir M. Al-Hashimi |
| Booktitle: | System-on-Chip: Next Generation Electronics |
| Publisher: | The IEE |
| Sites: | 715-745 |
| Year: | 2006 |
| Format: | gebunden |
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JOURNALS |
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» Automatic TLM Fault Localization for SystemC
[Link to the Homepage of this journal]
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Author:
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Hoang M. Le, Daniel Große, Rolf Drechsler |
| Journal: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 31, Number 8, pp. 1249-1262,
DOI: 10.1109/TCAD.2012.2188800
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Year:
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2012
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» Debugging Reversible Circuits
[Link to the Homepage of this journal]
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Author:
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Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler |
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INTEGRATION, the VLSI Journal |
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Volume 44, Number 1, pp. 51-61, JanuaryDOI: 10.1016/j.vlsi.2010.08.002 |
Year:
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2011
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» Towards Fully Automatic Synthesis of Embedded Software
[Link to the Homepage of this journal]
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Author:
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Ulrich Kühne, Daniel Große, Rolf Drechsler |
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IEEE Embedded Systems Letters |
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Volume 2, Number 3, pp. 53-57, September |
Year:
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2010
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» Exact Synthesis of Elementary Quantum Gate Circuits
[Link to the Homepage of this journal]
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Author:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Journal: |
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Multiple-Valued Logic and Soft Computing |
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Volume 15, Number 4, pp. 283-300 |
Year:
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2009
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» Exact Multiple Control Toffoli Network Synthesis with SAT Techniques
[Link to the Homepage of this journal]
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Author:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 28, Number 5, pp. 703-715, MayDOI: 10.1109/TCAD.2009.2017215 |
Year:
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2009
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» Analyzing Functional Coverage in Bounded Model Checking
[Link to the Homepage of this journal]
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Author:
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Daniel Große, Ulrich Kühne, Rolf Drechsler |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 27, Number 7, pp. 1305-1314, July |
Year:
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2008
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» BDD-based Verification of Scalable Designs
[Link to the Homepage of this journal]
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Author:
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Daniel Große, Rolf Drechsler |
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Facta Universitatis, Series: Electronics and Energetics |
| Details: |
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Volume 20, Number 3, pp. 367-379 |
Year:
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2007
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» System Level Validation Using Formal Techniques
[Link to the Homepage of this journal]
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Author:
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Rolf Drechsler, Daniel Große |
| Journal: |
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IEE Proceedings Computer & Digital Techniques, Special Issue on Embedded Microelectronic Systems: Status and Trends |
| Details: |
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Volume 152, Number 3, pp. 393-406, May |
Year:
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2005
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» Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC
[Link to the Homepage of this journal]
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Author:
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Daniel Große, Rolf Drechsler |
| Journal: |
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it - information technology |
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Number 4, pp. 219-226, August |
Year:
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2003
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» Heuristic Learning based on Genetic Programming
[Link to the Homepage of this journal]
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Author:
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Frank Schmiedle, Nicole Drechsler, Daniel Große and Rolf Drechsler |
| Journal: |
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Genetic Programming and Evolvable Machines |
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Volume 3, pp. 363-388, December |
Year:
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2002
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CONFERENCES |
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» Minimal Stimuli Generation in Simulation-based Verification
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Author:
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Shuo Yang, Robert Wille, Daniel Große and Rolf Drechsler |
| Conference: |
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Euromicro Conference on Digital System Design (DSD) |
Reference:
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| Santander, Spain, 2013
| Hyperlink:
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| [To the Site of this Conference]
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» Verifying SystemC using an Intermediate Verification Language and Symbolic Simulation
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Author:
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Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler |
| Conference: |
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Design Automation Conference (DAC) |
Reference:
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| Austin, Texas, 2013
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Synchronized Debugging across Different Abstraction Levels in System Design
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Author:
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Rolf Drechsler, Daniel Große, Hoang M. Le, André Sülflow |
| Conference: |
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embedded world Conference 2013 |
Reference:
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| Nürnberg, 2013
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Scalable Fault Localization for SystemC TLM Designs
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Author:
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Hoang M. Le, Daniel Große, Rolf Drechsler |
| Conference: |
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Design, Automation and Test in Europe (DATE'13) |
Reference:
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| pp. 35-38, Grenoble, France, 2013
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» From Requirements and Scenarios to ESL Design in SystemC
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Author:
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Hoang M. Le, Daniel Große, Rolf Drechsler |
| Conference: |
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International Symposium on Electronic System Design (ISED) |
Reference:
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| Kolkata, WB, India, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» The System Verification Methodology for
Advanced TLM Verification
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Author:
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Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler, Wolfgang Ecker, Volkan Esen |
| Conference: |
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International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) |
Reference:
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| pp. 313-322, Tampere, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Completeness-Driven Development
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Author:
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Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille |
| Conference: |
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International Conference on Graph Transformation |
Reference:
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| pp. 38-50, Bremen, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC
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Author:
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Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler |
| Conference: |
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International Symposium on System-on-Chip (SoC) |
Reference:
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| pp. 1-7, Tampere, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Localizing Features of ESL Models for Design Understanding
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Author:
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Marc Michael, Daniel Große, Rolf Drechsler |
| Conference: |
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Forum on specification & Design Languages (FDL) |
Reference:
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| Vienna, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Coverage-driven Stimuli Generation
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Author:
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Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler |
| Conference: |
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15th Euromicro Conference on Digital System Design (DSD) |
Reference:
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| Izmir, Turkey, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» A Guiding Coverage Metric for Formal Verification
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Author:
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Finn Haedicke, Daniel Große, Rolf Drechsler |
| Conference: |
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Design, Automation and Test in Europe (DATE) |
Reference:
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| Dresden, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Analyzing Dependability Measures at the Electronic System Level
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Author:
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Marc Michael, Daniel Große, Rolf Drechsler |
| Conference: |
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Forum on specification & Design Languages (FDL) |
Reference:
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| pp. 1-8, Oldenburg, 2011
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» TLM Protocol Compliance Checking at the Electronic System Level
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Author:
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Mohamed Bawadekji, Daniel Große, Rolf Drechsler |
| Conference: |
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14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Reference:
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| pp. 435-440, Cottbus, 2011
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Designing a RISC CPU in Reversible Logic
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Author:
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Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler |
| Conference: |
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41st International Symposium on Multiple-Valued Logic (ISMVL) |
Reference:
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| pp. 170-175, Tuusula, 2011
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Simulation-based Equivalence Checking between SystemC Models at different Levels of Abstraction
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Author:
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Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler |
| Conference: |
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Great Lakes Symposium on VLSI (GLSVLSI) |
Reference:
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| pp. 223-228, Lausanne, 2011
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Proving Transaction and System-level Properties of Untimed SystemC TLM Designs
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Author:
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Daniel Große, Hoang M. Le, Rolf Drechsler |
| Conference: |
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International Conference on
Formal Methods and Models for Codesign (MEMOCODE) |
Reference:
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| pp. 113-122, Grenoble, 2010
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» SMT-based Stimuli Generation in the SystemC Verification Library
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Author:
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Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler |
| Conference: |
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Forum on specification & Design Languages (FDL) |
Reference:
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| pp. 1-6, Sophia Antipolis, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» WoLFram - A Word Level Framework for Formal Verification
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Author:
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Andre Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler |
| Conference: |
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IEEE/IFIP International Symposium on Rapid System Prototyping (RSP) |
Reference:
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| pp. 11-17, Paris, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Contradictory Antecedent Debugging in Bounded Model Checking
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Author:
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Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
| Conference: |
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Great Lakes Symposium on VLSI (GLSVLSI) |
Reference:
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| pp. 173-176, Boston, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Equivalence Checking of Reversible Circuits
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Author:
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Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler |
| Conference: |
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39th International Symposium on Multiple-Valued Logic (ISMVL) |
Reference:
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| pp. 324-330, Naha, Okinawa, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Property Analysis and Design Understanding
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Author:
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Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Conference: |
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Design, Automation and Test in Europe (DATE)
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Reference:
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| pp. 1246-1249, Nice, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Debugging of Toffoli Networks
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Author:
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Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
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| Conference: |
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Design, Automation and Test in Europe (DATE) |
Reference:
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| pp. 1284-1289, Nice, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Reversible Logic Synthesis with Output Permutation
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Author:
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Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
| Conference: |
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22nd International Conference on VLSI Design |
Reference:
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| pp. 189-194, New Delhi, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Contradiction Analysis for Constraint-based Random Simulation
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Author:
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Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler |
| Conference: |
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Forum on specification & Design Languages (FDL) |
Reference:
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| pp. 130-135, Stuttgart, 2008
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability
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Author:
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Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler |
| Conference: |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Reference:
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| pp. 411-416, Montpellier, 2008
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» RevLib: An Online Resource for
Reversible Functions and Reversible Circuits
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Author:
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Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler |
| Conference: |
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38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Reference:
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| pp. 220-225, Dallas, 2008
RevLib is available at www.revlib.org
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Exact Synthesis of Elementary Quantum Gate
Circuits for Reversible Functions with Don’t Cares
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Author:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Conference: |
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38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Reference:
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| pp. 214-219, Dallas, 2008
Received IEEE Young Researcher Award
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Quantified Synthesis of Reversible Logic
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Author:
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Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große |
| Conference: |
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Design, Automation, and Test in Europe (DATE) |
Reference:
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| pp. 1015-1020, Munich, 2008
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Fast Exact Toffoli Network Synthesis of Reversible Logic
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Author:
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Robert Wille, Daniel Große |
| Conference: |
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IEEE International Conference on Computer Aided Design (ICCAD) |
Reference:
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| pp. 60-64, San Jose, 2007
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» SWORD: A SAT like Prover Using Word Level Information
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Author:
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Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler |
| Conference: |
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IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC) |
Reference:
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| pp. 88-93, Atlanta, 2007
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Measuring the Quality of a SystemC Testbench by using Code Coverage Technqiues
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Author:
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Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler |
| Conference: |
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Forum on specification & Design Languages (FDL) |
Reference:
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| pp. 146-151, Barcelona, 2007
Received Best Paper Award
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
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Author:
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Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Conference: |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07) |
Reference:
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| pp. 165-170, Porto Alegre, 2007
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL
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Author:
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Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler |
| Conference: |
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37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07) |
Reference:
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| Oslo, 2007
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Improvements for Constraint Solving in the SystemC Verification Library
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Author:
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Daniel Große, Rüdiger Ebendt, Rolf Drechsler |
| Conference: |
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Great Lakes Symposium on VLSI (GLSVLSI) |
Reference:
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| pp. 493-496, Stresa, 2007
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Exact SAT-based Toffoli Network Synthesis
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Author:
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Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler |
| Conference: |
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Great Lakes Symposium on VLSI (GLSVLSI) |
Reference:
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| pp. 96-101, Stresa, 2007
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Estimating Functional Coverage in Bounded Model Checking
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Author:
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Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Conference: |
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Design, Automation and Test in Europe (DATE) |
Reference:
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| pp. 1176-1181, Nice, 2007
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» HW/SW Co-Verification of Embedded Systems using Bounded Model Checking
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Author:
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Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Conference: |
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Great Lakes Symposium on VLSI (GLSVLSI) |
Reference:
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| pp. 43-48, Philadelphia, 2006
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks
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Author:
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Görschwin Fey, Daniel Große, Rolf Drechsler |
| Conference: |
|
Design, Automation and Test in Europe (DATE) |
Reference:
|
| pp. 1225-1226, Munich, 2006
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Acceleration of SAT-based Iterative Property Checking
|
|
|
|
Author:
|
|
Daniel Große, Rolf Drechsler |
| Conference: |
|
Correct Hardware Design and Verification Methods (CHARME) |
Reference:
|
| pp. 349-353, Saarbrücken, 2005
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» CheckSyC: An Efficient Property Checker for RTL SystemC Designs
|
|
|
|
Author:
|
|
Daniel Große, Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'05) |
Reference:
|
| pp. 4167-4170, Kobe, 2005
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Automated Verification For Train Control Systems
|
|
|
|
Author:
|
|
Jan Peleska, Daniel Große, Anne E. Haxthausen, Rolf Drechsler |
| Conference: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2004) |
Reference:
|
| pp. 252-265, Braunschweig, 2004
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Checkers for SystemC Designs
|
|
|
|
Author:
|
|
Daniel Große, Rolf Drechsler |
| Conference: |
|
Second ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2004) |
Reference:
|
| pp. 171-178, San Diego, 2004
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Efficient Automatic Visualization of SystemC Designs
|
|
|
|
Author:
|
|
Daniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst |
| Conference: |
|
Forum on Specification & Design Languages (FDL'03) |
Reference:
|
| pp. 646-657, Frankfurt, 2003
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Modeling Multi-Valued Circuits in SystemC
|
|
|
|
Author:
|
|
Daniel Große, Görschwin Fey and Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003) |
Reference:
|
| pp. 281-286, Tokyo, 2003
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
| PS:
|
| [view PS]
|
» Formal Verification of LTL Formulas for SystemC Designs
|
|
|
|
Author:
|
|
Daniel Große, Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'03) |
Reference:
|
| pp. V:245-V:248, Bangkok, 2003
| PDF:
|
| [view Pdf]
|
» Reachability Analysis for Formal Verification of SystemC
|
|
|
|
Author:
|
|
Rolf Drechsler and Daniel Große |
| Conference: |
|
Euromicro Symposium on Digital System Design (DSD'2002) |
Reference:
|
| pages 337-340, Dortmund, 2002
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
|
WORKSHOPS |
|
» Towards Automatic Scenario Generation from Coverage Information
|
|
|
|
Author:
|
|
Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler |
| Workshop: |
|
8th International Workshop on Automation of Software Test (AST) |
Reference:
|
| pp. 82-88, San Francisco, 2013
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» SystemC Verifikation mittels symbolischer Simulation einer Zwischensprache
|
|
|
|
Author:
|
|
Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler |
| Workshop: |
|
edaWorkshop |
Reference:
|
| pp. 53-58, Dresden, 2013
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» Behavior Driven Development for Circuit Design and Verification
|
|
|
|
Author:
|
|
Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler |
| Workshop: |
|
IEEE International Workshop on High-Level Design Validation and Test (HLDVT) |
Reference:
|
| Huntington Beach, USA, 2012
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» Design Understanding by Feature Localization on ESL
|
|
|
|
Author:
|
|
Marc Michael, Daniel Große, Rolf Drechsler |
| Workshop: |
|
9. GMM/ITG/GI-Workshop Cyber-Physical Systems – Enabling Multi-Nature Systems (CPMNS) |
Reference:
|
| pp. 19-24, Dresden, 2012
| Hyperlink:
|
| [Link to the Workshop]
|
» Compilation of Methodologies to Speed up the Verification Process
at System Level
|
|
|
|
Author:
|
|
Stephan Radke, Steffen Rülke, Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Müller, Wolfgang Ecker, Volkan Esen, Simon Hufnagel, Nico Bannow, Helmut Brazdrum, Peter Janssen, Hoang M. Le, Daniel Große, Rolf Drechsler, Erhard Fehlauer, Gernot Koch, Andreas Burger, Oliver Bringmann, Wolfgang Rosenstiel, Finn Haedicke, Ralph Görgen, Jan-Hendrik Oetjens |
| Workshop: |
|
edaWorkshop |
Reference:
|
| pp. 57-62, Hannover, 2012
| Hyperlink:
|
| [Link to the Workshop]
|
» SystemC-based ESL Verification Flow
Integrating Property Checking and Automatic
Debugging
|
|
|
|
Author:
|
|
Hoang M. Le, Daniel Große, Rolf Drechsler |
| Workshop: |
|
DATE Friday Workshop: OSCI and Accellera Core Technologies for the Next Generation of System-Level Design |
Reference:
|
| Dresden, 2012
| Hyperlink:
|
| [Link to the Workshop]
|
» CRAVE: An Advanced Constrained Random Verification Environment for SystemC
|
|
|
|
Author:
|
|
Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler |
| Workshop: |
|
15. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) |
Reference:
|
| Kaiserslautern, 2012
Software and benchmarks available at www.systemc-verification.org
| Hyperlink:
|
| [Link to the Workshop]
|
» Towards Proving TLM Properties with Local Variables
|
|
|
|
Author:
|
|
Hoang M. Le, Daniel Große, Rolf Drechsler |
| Workshop: |
|
7th International Workshop on Constraints in Formal Verification (CFV) |
Reference:
|
| San Jose, 2011
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» metaSMT: Focus on Your Application not on Solver Integration
|
|
|
|
Author:
|
|
Finn Haedicke, Stefan Frehse, Görschwin Fey, Daniel Große, Rolf Drechsler |
| Workshop: |
|
DIFTS'11: 1st International workshop on design and implementation of formal tools and systems |
Reference:
|
| pp. 22-29, Austin, USA, 2011
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines
|
|
|
|
Author:
|
|
Kim Grüttner, Andreas Herrholz, Ulrich Kühne, Daniel Große, Achim Rettberg, Wolfgang Nebel, Rolf Drechsler |
| Workshop: |
|
SORT 2011: 2nd IEEE Workshop on Self-Organizing Real-Time Systems |
Reference:
|
| pp. 181-188, Newport Beach, 2011
| Hyperlink:
|
| [Link to the Workshop]
|
» Protocol Compliance Checking of SystemC TLM Models
|
|
|
|
Author:
|
|
Mohamed Bawadekji, Daniel Große, Rolf Drechsler |
| Workshop: |
|
8. GMM/ITG/GI-Workshop Cyber-Physical Systems – Enabling Multi-Nature Systems (CPMNS) |
Reference:
|
| pp. 27-32, Bremen, 2011
| Hyperlink:
|
| [Link to the Workshop]
|
» Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction
|
|
|
|
Author:
|
|
Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
|
14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Reference:
|
| pp. 269-278, Oldenburg, 2011
| Hyperlink:
|
| [Link to the Workshop]
|
» Designing a RISC CPU in Reversible Logic
|
|
|
|
Author:
|
|
Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler |
| Workshop: |
|
14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Reference:
|
| pp. 249-258, Oldenburg, 2011
| Hyperlink:
|
| [Link to the Workshop]
|
» Automatic Fault Localization for SystemC TLM Designs
|
|
|
|
Author:
|
|
Hoang M. Le, Daniel Große, Rolf Drechsler |
| Workshop: |
|
11th International Workshop on Microprocessor Test and Verification (MTV) |
Reference:
|
| pp. 35-40, Austin, Texas, 2010
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» Towards Analyzing Functional Coverage in SystemC TLM Property Checking
|
|
|
|
Author:
|
|
Hoang M. Le, Daniel Große, Rolf Drechsler |
| Workshop: |
|
IEEE International Workshop on High-Level Design Validation and Test (HLDVT) |
Reference:
|
| pp. 67-74, Anaheim, 2010
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» Induction-based Formal Verification of SystemC TLM Designs
|
|
|
|
Author:
|
|
Daniel Große, Hoang M. Le, Rolf Drechsler |
| Workshop: |
|
10th International Workshop on Microprocessor Test and Verification (MTV) |
Reference:
|
| pp. 101-106, Austin, Texas, 2009
| Hyperlink:
|
| [Link to the Workshop]
|
» Equivalence Checking of Reversible Circuits
|
|
|
|
Author:
|
|
Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler |
| Workshop: |
|
12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Reference:
|
| 2009
| Hyperlink:
|
| [Link to the Workshop]
|
» Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow
|
|
|
|
Author:
|
|
Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Workshop: |
|
9th International Workshop on Microprocessor Test and Verification (MTV) |
Reference:
|
| pp. 88-93, Austin, Texas, 2008
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» Reversible Logic Synthesis with Output Permutation
|
|
|
|
Author:
|
|
Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
| Workshop: |
|
International Workshop on Boolean Problems |
Reference:
|
| Freiberg, 2008
| Hyperlink:
|
| [Link to the Workshop]
|
» Contradiction Analysis for Constraint-based Random Simulation
|
|
|
|
Author:
|
|
Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler |
| Workshop: |
|
Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS)
|
Reference:
|
| pp. 25-30, Dresden, 2008
| Hyperlink:
|
| [Link to the Workshop]
|
» Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking
|
|
|
|
Author:
|
|
Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
|
11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen
zur Modellierung und Verifikation von Schaltungen und Systemen" |
Reference:
|
| pp. 169-178, Freiburg, 2008
| Hyperlink:
|
| [Link to the Workshop]
|
» Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits
|
|
|
|
Author:
|
|
Andre Sülflow, Ulrich Kühne, Robert Wille, Daniel Große, Rolf Drechsler |
| Workshop: |
|
IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07) |
Reference:
|
| pp. 31-36, Beijing, P.R.China, 2007
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» Formal Verification on the Word Level using SAT-like Proof
Techniques
|
|
|
|
Author:
|
|
Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Reference:
|
| pp. 165-173, Erlangen, 2007
| Hyperlink:
|
| [Link to the Workshop]
|
» Exact Toffoli Network Synthesis of Reversible Logic using Boolean Satisfiability
|
|
|
|
Author:
|
|
Daniel Große, Xiaobo Chen, Rolf Drechsler |
| Workshop: |
|
Fifth IEEE Dallas Circuits and Systems Workshop |
Reference:
|
| pp. 51-54, Dallas, 2006
| Hyperlink:
|
| [Link to the Workshop]
|
» Complete Formal Verification of Multi Core Embedded Systems using Bounded Model Checking
|
|
|
|
Author:
|
|
Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Workshop: |
|
Fifth IEEE Dallas Circuits and Systems Workshop |
Reference:
|
| pp. 147-150, Dallas, 2006
| Hyperlink:
|
| [Link to the Workshop]
|
» HW/SW Co-Verification of a RISC CPU using Bounded Model Checking
|
|
|
|
Author:
|
|
Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
|
6th International Workshop on Microprocessor Test and Verification (MTV'05) |
Reference:
|
| pp. 133-137, Austin, 2005
| PDF:
|
| [view Pdf]
|
» Bounded Model Checking of Tram Control Systems
|
|
|
|
Author:
|
|
Sebastian Kinder, Daniel Große, Jan Peleska, Rolf Drechsler |
| Workshop: |
|
TRain Workshop @ SEFM2005 |
Reference:
|
| Koblenz, 2005
|
» Formale Verifikation des Befehlssatzes eines in SystemC modellierten Mikroprozessors
|
|
|
|
Author:
|
|
Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
|
Entwurfsmethoden für Nanometer VLSI Design |
Reference:
|
| pp. 308-312, Bonn, 2005
| PDF:
|
| [view Pdf]
|
» Acceleration of SAT-based Iterative Property Checking
|
|
|
|
Author:
|
|
Daniel Große, Rolf Drechsler |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Reference:
|
| München, 2005
| PDF:
|
| [view Pdf]
|
» Modellierung eines Mikroprozessors in SystemC
|
|
|
|
Author:
|
|
Daniel Große, Ulrich Kühne, Christian Genz, Frank Schmiedle, Bernd Becker, Rolf Drechsler, Paul Molitor |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Reference:
|
| München, 2005
| PDF:
|
| [view Pdf]
|
» SyCE: An Integrated Environment for System Design in SystemC
|
|
|
|
Author:
|
|
Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große |
| Workshop: |
|
16th IEEE International Workshop on Rapid System Prototyping (RSP) |
Reference:
|
| pp. 258-260, Montreal, 2005
| PDF:
|
| [view Pdf]
|
» ParSyC: An Efficient SystemC Parser
|
|
|
|
Author:
|
|
Görschwin Fey, Daniel Große, Tim Cassens, Christian Genz, Tim Warode, Rolf Drechsler |
| Workshop: |
|
12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2004) |
Reference:
|
| pp. 148-154, Kanazawa, 2004
| PDF:
|
| [view Pdf]
|
» BDD-Based Verification of Scalable Designs
|
|
|
|
Author:
|
|
Daniel Große, Rolf Drechsler |
| Workshop: |
|
IEEE International High Level Design Validation and Test Workshop (HLDVT'2003) |
Reference:
|
| pp. 123-128, San Francisco, 2003
| PDF:
|
| [view Pdf]
|
» Formale Verifikation von LTL-Formeln für SystemC-Beschreibungen
|
|
|
|
Author:
|
|
Daniel Große, Rolf Drechsler |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Reference:
|
| pp. 229-238, Bremen, 2003
| PDF:
|
| [view Pdf]
|
|
|
|
|
