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BOOKS

» Test Pattern Generation using Boolean Proof Engines
[Read more about this book!]



Publisher:


Springer
Author:

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille
Format:
Hardcover
Year:


2009





BOOK CONTRIBUTIONS


JOURNALS

» Incremental Solving Techniques for SAT-based ATPG
[Link to the Homepage of this journal]




Author:

Daniel Tille, Stephan Eggersglüß, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 29, Number 7, pp. 1125-1130, July
Year:


2010





» Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
[Link to the Homepage of this journal]




Author:

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille
Journal:
it - information technology
Details:
Volume 51, Number 2, pp. 102-111
Pdf download
Year:


2009





» On Acceleration of SAT-based ATPG for Industrial Designs
[Link to the Homepage of this journal]




Author:

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Daniel Tille
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 27, Number 7, pp. 1329-1333, July
Year:


2008






CONFERENCES



» Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test




Author:

Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen
Conference:
IEEE Asian Test Symposium (ATS)
Reference:

Hiroshima, Japan, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Automated Formal Verification of X Propagation with Respect to Testability Issues




Author:

Mehdi Dehbashi, Daniel Tille, Ulrike Pfannkuchen, Stephan Eggersglüß
Conference:
IEEE International Design and Test Symposium 2014 (IDT)
Reference:

pp. 106-111, Algiers, Algerien, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Improving CNF Representations in SAT-based ATPG for Industrial Circuits using BDDs




Author:

Daniel Tille, Stephan Eggersglüß, René Krenz-Bååth, Juergen Schloeffel, Rolf Drechsler
Conference:
15th IEEE European Test Symposium (ETS)
Reference:

pp. 176-181, Prag, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Efficient Test Generation with Maximal Crosstalk-Induced Noise using Unconstrained Aggressor Excitation




Author:

Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS)
Reference:

pp. 649-652, Paris, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Structural Heuristics for SAT-based ATPG




Author:

Daniel Tille, Stephan Eggersglüß, Hoang M. Le, Rolf Drechsler
Conference:
17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2009)
Reference:

pp. 77-82, Florianópolis, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Speeding up SAT-based ATPG using Dynamic Clause Activation




Author:

Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Conference:
18th Asian Test Symposium (ATS'09)
Reference:

pp. 177-182, Taichung, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» A Fast Untestability Proof for SAT-based ATPG




Author:

Daniel Tille, Rolf Drechsler
Conference:
12th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
Reference:

pp. 38-43, Liberec, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Experimental Studies on SAT-based ATPG for Gate Delay Faults




Author:

Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Conference:
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07)
Reference:

Oslo, 2007
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]


WORKSHOPS




» A Two-Stage SAT-based ATPG Approach with Reduced Switching Activity




Author:

Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Workshop:
Second International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR) 2009
Reference:

Sevilla, Spain, 2009
PDF:

[view Pdf]
Hyperlink:

[Link to the Workshop]



» A Fast Untestability Proof for SAT-based ATPG




Author:

Daniel Tille, Rolf Drechsler
Workshop:
21. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2009
Reference:

Bremen, 2009
PDF:

[view Pdf]
Hyperlink:

[Link to the Workshop]



» Robust Tests for Transition Faults with Long Propagation Paths Using Boolean Satisfiability




Author:

Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Workshop:
IEEE European Test Symposium (ETS), Informal Digest of Papers
Reference:

Lago Maggiore, 2008
PDF:

[view Pdf]
Hyperlink:

[Link to the Workshop]



» Incremental SAT Instance Generation for SAT-based ATPG




Author:

Daniel Tille, Rolf Drechsler
Workshop:
11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Reference:

pp. 68-73, Bratislava, 2008
PDF:

[view Pdf]
Hyperlink:

[Link to the Workshop]



» Improved Circuit-to-CNF Transformation for SAT-based ATPG




Author:

Daniel Tille, René Krenz-Bååth, Jürgen Schlöffel, Rolf Drechsler
Workshop:
20. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
Reference:

Wien, 2008
PDF:

[view Pdf]
Hyperlink:

[Link to the Workshop]



» Parallelisierung von SAT-basierter Testmustergenerierung




Author:

Daniel Tille, Robert Wille, Rolf Drechsler
Workshop:
21. Workshop der GI/ITG-Fachgruppe Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS 2007)
Reference:

pp. 213-217, Hamburg, 2007
Hyperlink:

[Link to the Workshop]



» Studies on Integrating SAT-based ATPG in an Industrial Environment




Author:

Daniel Tille, Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Workshop:
19. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
Reference:

Erlangen, 2007
PDF:

[view Pdf]
Hyperlink:

[Link to the Workshop]



» Instance Generation for SAT-based ATPG




Author:

Daniel Tille, Görschwin Fey, Rolf Drechsler
Workshop:
10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Reference:

Krakau, 2007
PDF:

[view Pdf]
Hyperlink:

[Link to the Workshop]

















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