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Home « Team « Publications
» Publications of
Gerhard W. Dueck
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BOOKS |
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BOOK CONTRIBUTIONS |
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JOURNALS |
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» Ancilla-free synthesis of large reversible functions using binary decision diagrams
[Link to the Homepage of this journal]
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Author:
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Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler |
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Journal of Symbolic Computation |
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accepted, preprint available at arXiv 1408.3955 |
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2015
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» Debugging Reversible Circuits
[Link to the Homepage of this journal]
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Author:
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Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler |
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INTEGRATION, the VLSI Journal |
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Volume 44, Number 1, pp. 51-61, JanuaryDOI: 10.1016/j.vlsi.2010.08.002 |
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2011
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» Exact Synthesis of Elementary Quantum Gate Circuits
[Link to the Homepage of this journal]
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Author:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
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Multiple-Valued Logic and Soft Computing |
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Volume 15, Number 4, pp. 283-300 |
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2009
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» Exact Multiple Control Toffoli Network Synthesis with SAT Techniques
[Link to the Homepage of this journal]
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Author:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 28, Number 5, pp. 703-715, MayDOI: 10.1109/TCAD.2009.2017215 |
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2009
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CONFERENCES |
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» Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits
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Author:
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Md. Mazder Rahman, Gerhard W. Dueck, Anupam Chattopadhyay, Robert Wille |
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46th International Symposium on Multiple-Valued Logic (ISMVL) |
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| Sapporo, Japan, 2016
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Reversible Circuit Rewriting with Simulated Annealing
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Author:
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Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, and Rolf Drechsler |
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IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) |
Reference:
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| Daejeon, Korea, 2015
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| [To the Site of this Conference]
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| [view Pdf]
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» Dynamic Template Matching with Mixed-polarity Toffoli Gates
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Author:
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Md Mazder Rahman, Mathias Soeken, Gerhard W. Dueck |
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45th International Symposium on Multiple-Valued Logic (ISMVL) |
Reference:
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| Waterloo, Canada, 2015
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Synthesizing Multiplier in Reversible Logic
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Author:
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Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
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13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Reference:
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| pp. 335-340, Vienna, 2010
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| [To the Site of this Conference]
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» Window Optimization of Reversible and Quantum Circuits
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Author:
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Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
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13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Reference:
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| pp. 431-435, Vienna, 2010
| Hyperlink:
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| [To the Site of this Conference]
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» Synthesizing Reversible Circuits for Irreversible Functions
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Author:
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D. Michael Miller, Robert Wille, Gerhard W. Dueck |
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Euromicro Conference on Digital System Design (DSD) |
Reference:
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| pp. 749-756, Patras, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Debugging of Toffoli Networks
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Author:
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Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
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Design, Automation and Test in Europe (DATE) |
Reference:
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| pp. 1284-1289, Nice, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Reversible Logic Synthesis with Output Permutation
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Author:
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Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
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22nd International Conference on VLSI Design |
Reference:
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| pp. 189-194, New Delhi, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» RevLib: An Online Resource for
Reversible Functions and Reversible Circuits
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Author:
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Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler |
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38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
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| pp. 220-225, Dallas, 2008
RevLib is available at www.revlib.org
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Exact Synthesis of Elementary Quantum Gate
Circuits for Reversible Functions with Don’t Cares
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Author:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
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38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Reference:
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| pp. 214-219, Dallas, 2008
Received IEEE Young Researcher Award
| Hyperlink:
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| [To the Site of this Conference]
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| [view Pdf]
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» Quantified Synthesis of Reversible Logic
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Author:
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Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große |
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Design, Automation, and Test in Europe (DATE) |
Reference:
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| pp. 1015-1020, Munich, 2008
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Exact SAT-based Toffoli Network Synthesis
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Author:
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Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler |
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Great Lakes Symposium on VLSI (GLSVLSI) |
Reference:
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| pp. 96-101, Stresa, 2007
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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WORKSHOPS |
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» Self-Inverse Functions and Palindromic Circuits
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Author:
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Mathias Soeken, Michael Kirkedal Thomsen, Gerhard W. Dueck, D. Michael Miller |
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Reed-Muller Workshop |
Reference:
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| Waterloo, Canada, 2015, pre-print available at arXiv:1502.05825
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| [Link to the Workshop]
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» Synthesising Reversible Circuits from Irreversible Specifications using Reed-Muller Spectral Techniques
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Author:
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D. Michael Miller, Gerhard W. Dueck, Robert Wille |
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Reed-Muller Workshop |
Reference:
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| Naha, Okinawa, 2009
| Hyperlink:
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| [Link to the Workshop]
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» Reversible Logic Synthesis with Output Permutation
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Author:
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Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
| Workshop: |
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International Workshop on Boolean Problems |
Reference:
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| Freiberg, 2008
| Hyperlink:
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| [Link to the Workshop]
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