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Home « Team « Publications
» Publications of
Görschwin Fey
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BOOKS |
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» Test Pattern Generation using Boolean Proof Engines
[Read more about this book!]
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Publisher: |
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Springer |
Author:
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Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille |
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Hardcover |
Year:
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2009
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» Robustness and Usability in Modern Design Flows
[Read more about this book!]
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Publisher: |
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Springer |
Author:
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Görschwin Fey, Rolf Drechsler |
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Hardcover |
Year:
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2008
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» SATRIX - Algorithmen für Boolesche Erfüllbarkeit
[Read more about this book!]
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Publisher: |
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Shaker Verlag |
Author:
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Daniel Große, Görschwin Fey, Rolf Drechsler (Hrsg.) |
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Gebunden |
Year:
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2007
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» Advanced BDD Optimization
[Read more about this book!]
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Publisher: |
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Springer Verlag |
Author:
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Rüdiger Ebendt, Görschwin Fey, Rolf Drechsler |
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Hardcover |
Year:
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2005
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» FunTaskIC - Eine integrierte Entwurfsumgebung für SystemC
[Read more about this book!]
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Publisher: |
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Shaker Verlag |
Author:
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Görschwin Fey, Rolf Drechsler (Hrsg.) |
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Gebunden |
Year:
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2005
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BOOK CONTRIBUTIONS |
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| » Evaluating Debugging Algorithms from a Qualitative Perspective |
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Author:
| Alexander Finder, Görschwin Fey
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| Editor: | Tom J. Kazmierski, Adam Morawiec |
| Booktitle: | System Specification and Design Languages: Selected Contributions from FDL 2010 |
| Publisher: | Springer |
| Sites: | 21-36 |
| Year: | 2012 |
| Format: | Hardcover |
| » Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis |
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Author:
| Daniel Große, Görschwin Fey, Rolf Drechsler
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| Editor: | Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus |
| Booktitle: | Design and Test Technology for Dependable Systems-on-Chip |
| Publisher: | Information Science Reference |
| Sites: | 119-129 |
| Year: | 2011 |
| Format: | Hardcover |
| » SWORD: A SAT like Prover Using Word Level Information |
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Author:
| Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
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| Editor: | Ricardo Reis, Vincent Mooney, Paul Hasler |
| Booktitle: | VLSI-SoC: Advanced Topics on Systems on a Chip:
A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip |
| Publisher: | Springer |
| Sites: | 175-192 |
| Year: | 2009 |
| Format: | Hardcover |
| » Automatic Test Pattern Generation |
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Author:
| Rolf Drechsler, Görschwin Fey
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| Editor: | Marco Bernardo, Alessandro Cimatti |
| Booktitle: | Formal Methods for Hardware Verification, LNCS 3965 |
| Publisher: | Springer |
| Sites: | 30-55 |
| Year: | 2006 |
| Format: | gebunden |
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JOURNALS |
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» Debug Automation for Logic Circuits Under Timing Variations
[Link to the Homepage of this journal]
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Author:
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Mehdi Dehbashi, Görschwin Fey |
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IEEE Design & Test of Computers |
| Details: |
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accepted |
Year:
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2013
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» Automated Design Debugging in a Testbench-Based Verification Environment
[Link to the Homepage of this journal]
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Author:
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Mehdi Dehbashi, André Sülflow, Görschwin Fey |
| Journal: |
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Embedded Hardware Design - Microprocessors and Microsystems (MICPRO) |
| Details: |
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Volume 37, Issue 2, pp. 206-217 |
Year:
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2013
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» Effective Robustness Analysis using Bounded Model Checking Techniques
[Link to the Homepage of this journal]
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Author:
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Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler |
| Journal: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 30, Number 8, pp. 1239-1252
DOI: 10.1109/TCAD.2011.2120950 |
Year:
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2011
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» Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen
[Link to the Homepage of this journal]
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Author:
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Görschwin Fey, Andre Sülflow, Stefan Frehse, Rolf Drechsler |
| Journal: |
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it-Information Technology |
| Details: |
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Volume 52, Number 4, pp. 216-223
PDF Download |
Year:
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2010
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» MONSOON: SAT-based ATPG for Path Delay Faults Using Multiple-Valued Logics
[Link to the Homepage of this journal]
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Author:
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Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Rolf Drechsler |
| Journal: |
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Journal of Electronic Testing: Theory and Applications |
| Details: |
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Volume 26, Number 3 / June, pp. 307-322
Pdf download (Preliminary Version)
The final publication is available at www.springerlink.com |
Year:
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2010
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» Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
[Link to the Homepage of this journal]
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Author:
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Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille |
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it - information technology |
| Details: |
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Volume 51, Number 2, pp. 102-111
Pdf download |
Year:
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2009
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» Advanced Verification by Automatic Property Generation
[Link to the Homepage of this journal]
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Author:
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Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke |
| Journal: |
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IET Computers & Digital Techniques |
| Details: |
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Volume 3, Issue 4, pp. 338-353, July |
Year:
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2009
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» On Acceleration of SAT-based ATPG for Industrial Designs
[Link to the Homepage of this journal]
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Author:
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Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Daniel Tille |
| Journal: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 27, Number 7, pp. 1329-1333, July |
Year:
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2008
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» On the Construction of Small Fully Testable Circuits with Low Depth
[Link to the Homepage of this journal]
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Author:
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Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler |
| Journal: |
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Embedded Hardware Design - Microprocessors and Microsystems (MICPRO) |
| Details: |
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Special Issue, Volume 32, Issues 5-6, pp. 263-269 |
Year:
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2008
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» Automatic Fault Localization for Property Checking
[Link to the Homepage of this journal]
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Author:
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Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler |
| Journal: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 27, Number 6, pp. 1138-1149, June |
Year:
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2008
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» Building Free Binary Decision Diagrams Using SAT Solvers
[Link to the Homepage of this journal]
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Author:
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Robert Wille, Görschwin Fey, Rolf Drechsler |
| Journal: |
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Facta Universitatis, Series: Electronics and Energetics |
| Details: |
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Volume 20, Number 3, pp. 381-394, |
Year:
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2007
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» An Integrated Approach for Combining BDDs and SAT Provers
[Link to the Homepage of this journal]
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Author:
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Rolf Drechsler, Görschwin Fey, Sebastian Kinder |
| Journal: |
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Facta Universitatis, Series: Electronics and Energetics
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| Details: |
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Volume 20, Number 3, pp. 415-436 |
Year:
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2007
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» Minimizing the Number of Paths in BDDs
- Theory and Algorithm
[Link to the Homepage of this journal]
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Author:
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Görschwin Fey, Rolf Drechsler |
| Journal: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 25, Number 1, pp. 4-11, January |
Year:
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2006
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» Project-Based Learning in Student Teams in Computer Science Education
[Link to the Homepage of this journal]
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Author:
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Andreas Breiter, Görschwin Fey, Rolf Drechsler |
| Journal: |
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Facta Universitatis, Series: Electronics and Energetics
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| Details: |
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Volume 18, Number 2, August, pp. 165-180. |
Year:
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2005
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» Synthesis of Fully Testable Circuits from BDDs
[Link to the Homepage of this journal]
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Author:
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Rolf Drechsler, Junhao Shi, Görschwin Fey |
| Journal: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 23, Number 3, March |
Year:
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2004
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CONFERENCES |
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» Debugging HDL Designs Based on Functional Equivalences with High-Level Specifications
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Author:
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Alexander Finder, Jan-Philipp Witte, Görschwin Fey |
| Conference: |
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16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Reference:
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| Karlovy Vary, Czech Republic, 2013
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Efficient Automated Speedpath Debugging
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Author:
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Mehdi Dehbashi, Görschwin Fey |
| Conference: |
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16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Reference:
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| pp. 48-53, Karlovy Vary, Czech Republic, 2013
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Reliability Analysis Reloaded: How Will We Survive?
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Author:
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Robert Aitken, Görschwin Fey, Zbigniew T. Kalbarczyk, Frank Reichenbach, Matteo Sonza Reorda |
| Conference: |
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Design, Automation and Test in Europe (DATE'13) |
Reference:
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| Grenoble, France, 2013
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Tuning Dynamic Data Flow Analysis to Support Design Understanding
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Author:
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Jan Malburg, Alexander Finder, Görschwin Fey |
| Conference: |
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Design, Automation and Test in Europe (DATE'13) |
Reference:
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| Grenoble, France, 2013
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Improving Fault Tolerance Utilizing Hardware-Software-Co-Synthesis
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Author:
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Heinz Riener, Stefan Frehse, Görschwin Fey |
| Conference: |
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Design, Automation and Test in Europe (DATE'13) |
Reference:
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| pp. 939-943, Grenoble, France, 2013
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» FoREnSiC - An Automatic Debugging Environment for C Programs
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Author:
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Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow
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| Conference: |
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Haifa Verification Conference (HVC) |
Reference:
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| Haifa, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Automated Post-Silicon Debugging of Failing
Speedpaths
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Author:
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Mehdi Dehbashi, Görschwin Fey |
| Conference: |
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21st IEEE Asian Test Symposium (ATS) |
Reference:
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| pp. 13-18, Niigata, Japan, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Complete and Effective Robustness Checking by Means of Interpolation
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Author:
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Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav and Rolf Drechsler |
| Conference: |
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Formal Methods in Computer-Aided Design (FMCAD'12) |
Reference:
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| Cambridge, UK, 2012, page 82-90
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Hardware-Software-Co-Synthese zur Verbesserung der Fehlertoleranz
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Author:
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Stefan Frehse, Heinz Riener, Görschwin Fey |
| Conference: |
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6. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE'12) |
Reference:
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| pp. 90-96, Bremen, Germany, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Application of Timing Variation Modeling to Speedpath Diagnosis
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Author:
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Mehdi Dehbashi, Görschwin Fey |
| Conference: |
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4th International Conference on System, Software, SoC and Silicon Debug (S4D) |
Reference:
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| pp. 34-37, Vienna, Austria, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Model-Based Diagnosis versus Error Explanation
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Author:
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Heinz Riener, Görschwin Fey |
| Conference: |
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10th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'12) |
Reference:
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| pp. 43-52, Arlington, Virginia, USA, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» On Modeling and Evaluation of Logic Circuits
Under Timing Variations
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Author:
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Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan |
| Conference: |
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15th Euromicro Conference on Digital System Design (DSD) |
Reference:
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| pp. 431-436, Izmir, Turkey, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Automated Debugging from Pre-Silicon to Post-Silicon
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Author:
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Mehdi Dehbashi, Görschwin Fey |
| Conference: |
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15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Reference:
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| pp. 324-329, Tallinn, Estonia, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Automated Feature Localization for Hardware Designs
using Coverage Metrics
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Author:
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Jan Malburg, Alexander Finder, Görschwin Fey |
| Conference: |
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Design Automation Conference (DAC) |
Reference:
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| pp. 941-946, San Francisco, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Functional Analysis of Circuits Under Timing
Variations
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Author:
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Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
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| Conference: |
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17th IEEE European Test Symposium (ETS) |
Reference:
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| pp. 177, Annecy, France, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Automated Post-Silicon Debugging of Design Bugs
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Author:
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Mehdi Dehbashi, Görschwin Fey |
| Conference: |
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3rd International Conference on System, Software, SoC and Silicon Debug (S4D) |
Reference:
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| pp. 67-71, Munich, Germany, 2011
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Hochoptimierter Ablauf zur Robustheitsprüfung
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Author:
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Stefan Frehse, Finn Haedicke, Melanie Diepenbeck, Görschwin Fey, Rolf Drechsler |
| Conference: |
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GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) |
Reference:
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| Hamburg-Harburg, 2011
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Automated Design Debugging in a Testbench-Based Verification Environment
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Author:
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Mehdi Dehbashi, André Sülflow, Görschwin Fey |
| Conference: |
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14th Euromicro Conference on Digital System Design (DSD) |
Reference:
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| pp. 479-486, Oulu, Finland, 2011
Best Paper Candidate
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Orchestrated Multi-level Information Flow Analysis to Understand SoCs
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Author:
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Görschwin Fey |
| Conference: |
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48th Design Automation Conference (DAC)
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Reference:
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| San Diego, USA, 2011
Promotion video on YouTube
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Latency Analysis for Sequential Circuits
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Author:
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Alexander Finder, André Sülflow, Görschwin Fey |
| Conference: |
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16th IEEE European Test Symposium (ETS) |
Reference:
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| pp. 129-134, Trondheim, 2011
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Automatic Property Generation for the Formal Verification of Bus Bridges
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Author:
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Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler |
| Conference: |
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14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Reference:
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| pp. 417-422, Cottbus, 2011
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Polynomial Datapath Optimization using Constraint Solving and Formal Modelling
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Author:
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Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler |
| Conference: |
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IEEE/ACM International Conference on Computer Aided Design (ICCAD) |
Reference:
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| San Jose, 2010
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Evaluating Debugging Algorithms from a Qualitative Perspective
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Author:
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Alexander Finder, Görschwin Fey |
| Conference: |
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Forum on specification & Design Languages (FDL) |
Reference:
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| pp. 37-42, Southampton, 2010
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Kompositionelle Formale Robustheitsprüfung
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Author:
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Stefan Frehse, Görschwin Fey |
| Conference: |
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GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) |
Reference:
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| Wildbad Kreuth, 2010
| Hyperlink:
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| [To the Site of this Conference]
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» RobuCheck: A Robustness Checker for Digital Circuits
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Author:
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Stefan Frehse, Görschwin Fey, Andre Sülflow and Rolf Drechsler
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| Conference: |
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Euromicro Conference on Digital System Design (DSD) |
Reference:
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| pp. 226-231, Lille, 2010
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» A Better-Than-Worst-Case Robustness Measure
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Author:
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Stefan Frehse, Görschwin Fey, Rolf Drechsler |
| Conference: |
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13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Reference:
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| pp. 78-83, Vienna, 2010
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Using QBF to Increase Accuracy of SAT-Based Debugging
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Author:
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Andre Sülflow, Görschwin Fey, Rolf Drechsler |
| Conference: |
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IEEE International Symposium on Circuits and Systems (ISCAS) |
Reference:
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| pp.641-644, Paris, 2010
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Anwendungsbezogene Analyse der Robustheit von Digitalen Schaltungen
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Author:
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Andre Sülflow, Stefan Frehse, Görschwin Fey, Rolf Drechsler |
| Conference: |
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GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) |
Reference:
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| pp. 45-52, Stuttgart, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Deterministc Algorithms for ATPG under Leakage Constraints
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Author:
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Görschwin Fey |
| Conference: |
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18th Asian Test Symposium (ATS'09) |
Reference:
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| Taichung, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» SAT-Based ATPG Testing of Inter- and Intra-Gate Bridging Faults
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Author:
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Toru Nakura, Yutaro Tatemura, Görschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada |
| Conference: |
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European Conference on Circuit Theory and Design |
Reference:
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| Antalya, 2009
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» Robustness Check for Multiple Faults using Formal Techniques
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Author:
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Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler |
| Conference: |
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Euromicro Conference on Digital System Design (DSD) |
Reference:
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| pp. 85-90, Patras, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Computing Bounds for Fault Tolerance using Formal Techniques
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Author:
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Görschwin Fey, Andre Sülflow, Rolf Drechsler |
| Conference: |
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Design Automation Conference (DAC) |
Reference:
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| pp. 190-195, San Francisco, USA, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» WoLFram - A Word Level Framework for Formal Verification
|
|
|
|
Author:
|
|
Andre Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler |
| Conference: |
|
IEEE/IFIP International Symposium on Rapid System Prototyping (RSP) |
Reference:
|
| pp. 11-17, Paris, 2009
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Evaluation of Cardinality Constraints on SMT-based Debugging
|
|
|
|
Author:
|
|
Andre Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler |
| Conference: |
|
39th International Symposium on Multiple-Valued Logic (ISMVL) |
Reference:
|
| pp. 298-303, Naha, Okinawa, 2009
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Increasing the Accuracy of SAT-based Debugging
|
|
|
|
Author:
|
|
Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler |
| Conference: |
|
Design, Automation and Test in Europe (DATE) |
Reference:
|
| pp. 1326-1332, Nice, 2009
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Formaler Nachweis der Fehlertoleranz von Schaltkreisen
|
|
|
|
Author:
|
|
Görschwin Fey, Andre Sülflow, Stefan Frehse, Ulrich Kühne, Rolf Drechsler |
| Conference: |
|
GMM/GI/ITG-Fachtagung: Zuverlässigkeit und Entwurf (ZuE 2008) |
Reference:
|
| pp. 75-82, Ingolstadt, 2008
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Targeting Leakage Constraints during ATPG
|
|
|
|
Author:
|
|
Görschwin Fey, Sathoshi Komatsu, Yasuo Furukawa, Masahiro Fujita |
| Conference: |
|
Asian Test Symposium (ATS) |
Reference:
|
| pp. 225-230, 2008
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking
|
|
|
|
Author:
|
|
Robert Wille, Görschwin Fey, Marc Messing, Gerhard
Angst, Lothar Linhard, Rolf Drechsler |
| Conference: |
|
Euromicro Conference on Digital System Design (DSD) |
Reference:
|
| pp. 542-549, Parma, 2008
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Using Unsatisfiable Cores to Debug Multiple Design Errors
|
|
|
|
Author:
|
|
Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
| Conference: |
|
IEEE Great Lakes Symposium on VLSI (GLSVLSI'08) |
Reference:
|
| pp. 77-82, Orlando, 2008
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» A Basis for Formal Robustness Checking
|
|
|
|
Author:
|
|
Görschwin Fey, Rolf Drechsler
|
| Conference: |
|
International Symposium on Quality of Electronic Design (ISQED) |
Reference:
|
| San Jose, 2008
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Automatic Generation of Complex Properties for Hardware Designs
|
|
|
|
Author:
|
|
Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler Steffen Rülke |
| Conference: |
|
Design, Automation, and Test in Europe (DATE) |
Reference:
|
| Munich, 2008
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» SWORD: A SAT like Prover Using Word Level Information
|
|
|
|
Author:
|
|
Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler |
| Conference: |
|
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC) |
Reference:
|
| pp. 88-93, Atlanta, 2007
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» On the Construction of Small Fully Testable Circuits with Low Depth
|
|
|
|
Author:
|
|
Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler |
| Conference: |
|
Euromicro Conference on Digital System Design (DSD)
Architectures, Methods and Tools |
Reference:
|
| Lübeck, 2007
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
|
|
|
|
Author:
|
|
Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel |
| Conference: |
|
Fifth ACM-IEEE International Conference on
Formal Methods and Models for Codesign (MEMOCODE'2007) |
Reference:
|
| pp. 181-187, Nice, 2007
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Experimental Studies on SAT-based ATPG for Gate Delay Faults
|
|
|
|
Author:
|
|
Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
| Conference: |
|
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07) |
Reference:
|
| Oslo, 2007
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» SAT-based ATPG for Path Delay Faults in Sequential Circuits
|
|
|
|
Author:
|
|
Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'07) |
Reference:
|
| pp. 3671-3674, New Orleans, 2007
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Reusing Learned Information in SAT-based ATPG
|
|
|
|
Author:
|
|
Görschwin Fey, Tim Warode, Rolf Drechsler |
| Conference: |
|
20th International Conference on VLSI Design |
Reference:
|
| Bangalore, 2007
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Automatic Fault Localization for Property Checking
|
|
|
|
Author:
|
|
Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
| Conference: |
|
Haifa Verification Conference |
Reference:
|
| Haifa, 2006
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Efficiency of Multiple-Valued Encoding in SAT-based ATPG
|
|
|
|
Author:
|
|
Görschwin Fey, Junhao Shi, Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Multiple-Valued Logic (ISMVL '06) |
Reference:
|
| Singapore, 2006
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» On the Relation Between Simulation-based and SAT-based Diagnosis
|
|
|
|
Author:
|
|
Görschwin Fey, Sean Safarpour, Andreas Veneris, Rolf Drechsler |
| Conference: |
|
Design, Automation and Test in Europe (DATE) |
Reference:
|
| pp. 1139-1144, Munich, 2006
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks
|
|
|
|
Author:
|
|
Görschwin Fey, Daniel Große, Rolf Drechsler |
| Conference: |
|
Design, Automation and Test in Europe (DATE) |
Reference:
|
| pp. 1225-1226, Munich, 2006
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» An Integrated Approach for Combining BDD and SAT Provers
|
|
|
|
Author:
|
|
Rolf Drechsler, Görschwin Fey, Sebastian Kinder |
| Conference: |
|
International Conference on VLSI Design |
Reference:
|
| Hyderabad, 2006
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Experimental Studies on SAT-based Test Pattern Generation for Industrial Circuits
|
|
|
|
Author:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke |
| Conference: |
|
International Conference on ASIC (ASICON 2005)
|
Reference:
|
| pp. 967-970, Shanghai, 2005
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» PASSAT: Efficient SAT-based Test Pattern Generation
|
|
|
|
Author:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
| Conference: |
|
IEEE Annual Symposium on VLSI (ISVLSI '05) |
Reference:
|
| pp.212-217, Tampa, Florida, 2005
| Hyperlink:
|
| [To the Site of this Conference]
| PS:
|
| [view PS]
|
» Controlling the Memory During Manipulation of Word-Level Decision Diagrams
|
|
|
|
Author:
|
|
Sebastian Kinder, Görschwin Fey, Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL 2005) |
Reference:
|
| pp. 250-255, Calgary, 2005
| Hyperlink:
|
| [To the Site of this Conference]
| PS:
|
| [view PS]
|
» Utilizing Don't Care States in SAT-based Bounded Sequential Problems
|
|
|
|
Author:
|
|
Sean Safarpour, Görschwin Fey, Andreas Veneris, Rolf Drechsler |
| Conference: |
|
Great Lakes Symposium on VLSI (GLSVLSI'05) |
Reference:
|
| Chicago, 2005
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Bridging Fault Testability of BDD Circuits
|
|
|
|
Author:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler |
| Conference: |
|
Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005) |
Reference:
|
| pp. 188-191 Shanghai, 2005
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» BDD Circuit Optimization for Path Delay Fault Testability
|
|
|
|
Author:
|
|
Görschwin Fey, Junhao Shi, Rolf Drechsler |
| Conference: |
|
Euromicro Symposium on Digital System Design (DSD'2004) |
Reference:
|
| pp. 168-172, Rennes, 2004
| Hyperlink:
|
| [To the Site of this Conference]
| PS:
|
| [view PS]
|
» Algorithms for Taylor Expansion Diagrams
|
|
|
|
Author:
|
|
Görschwin Fey, Rolf Drechsler, Maciej Ciesielski |
| Conference: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2004) |
Reference:
|
| pp. 235-240, Toronto, 2004
| Hyperlink:
|
| [To the Site of this Conference]
| PS:
|
| [view PS]
|
» Cost-Efficient Block Verification for a UMTS Up-Link
Chip-Rate Coprocessor
|
|
|
|
Author:
|
|
Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey |
| Conference: |
|
IEEE Design, Automation and Test in Europe
|
Reference:
|
| Vol. I, pp. 162-167, Paris, 2004
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» Improving Simulation-Based Verification by Means of Formal Methods
|
|
|
|
Author:
|
|
Görschwin Fey, Rolf Drechsler |
| Conference: |
|
Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
|
Reference:
|
| pp. 640-643, Yokohama, 2004
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
|
» BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
|
|
|
|
Author:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler |
| Conference: |
|
Twelfth Asian Test Symposium (ATS03)
|
Reference:
|
| p.290-293,
Xi'an, 2003
| Hyperlink:
|
| [To the Site of this Conference]
| PS:
|
| [view PS]
|
» Finding Good Counter-Examples to Aid Design Verification
|
|
|
|
Author:
|
|
Görschwin Fey, Rolf Drechsler |
| Conference: |
|
First ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2003) |
Reference:
|
| pp. 51-52, Mont Saint-Michel, 2003
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
| PS:
|
| [view PS]
|
» MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits
|
|
|
|
Author:
|
|
Rolf Drechsler, Junhao Shi and Görschwin Fey |
| Conference: |
|
IEEE Great Lakes Symposium on VLSI (GLSV'03) |
Reference:
|
| p. 80-83, Washington, 2003
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
| PS:
|
| [view PS]
|
» Modeling Multi-Valued Circuits in SystemC
|
|
|
|
Author:
|
|
Daniel Große, Görschwin Fey and Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003) |
Reference:
|
| pp. 281-286, Tokyo, 2003
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
| PS:
|
| [view PS]
|
» Using Games for Benchmarking and Representing the Complete Solution Space Using Symbolic Techniques
|
|
|
|
Author:
|
|
Görschwin Fey, Sebastian Kinder and Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003) |
Reference:
|
| pp. 361-366, Tokyo, 2003
| PS:
|
| [view PS]
|
» SPIHT implemented in a XC4000 device
|
|
|
|
Author:
|
|
Jörg Ritter, Görschwin Fey and Paul Molitor |
| Conference: |
|
IEEE The 45rd Midwest Symposium on Circuits and Systems (MWSCAS'2002) |
Reference:
|
| volume I, pages 239-242, Tulsa, 2002
| PDF:
|
| [view Pdf]
|
» Utilizing BDDs for disjoint SOP minimization
|
|
|
|
Author:
|
|
Görschwin Fey and Rolf Drechsler |
| Conference: |
|
IEEE The 45rd Midwest Symposium on Circuits and Systems (MWSCAS'2002) |
Reference:
|
| volume II, pages 306-309, Tulsa, 2002
| PS:
|
| [view PS]
|
» Minimizing the Number of Paths in BDDs
|
|
|
|
Author:
|
|
Görschwin Fey and Rolf Drechsler |
| Conference: |
|
15th Symposium on Integrated Circuits and System Design |
Reference:
|
| pages 359-364, Porto Alegre, 2002
| Hyperlink:
|
| [To the Site of this Conference]
| PDF:
|
| [view Pdf]
| PS:
|
| [view PS]
|
|
WORKSHOPS |
|
» Yet a Better Error Explanation Algorithm
|
|
|
|
Author:
|
|
Heinz Riener, Görschwin Fey |
| Workshop: |
|
16. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen
zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'13) |
Reference:
|
| pp.193-194, Rostock, Germany, 2013
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» Towards Debug Automation for Timing Bugs at RTL
|
|
|
|
Author:
|
|
Mehdi Dehbashi, Görschwin Fey |
| Workshop: |
|
25. GI/GMM/ITG Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ) |
Reference:
|
| Dresden, Germany, 2013
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» Verification of Embedded Systems Using Modeling and Implementation Languages
|
|
|
|
Author:
|
|
Mathias Soeken, Heinz Riener, Robert Wille, Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
International Workshop on Metamodelling and Code Generation for Embedded Systems (MeCoEs'12) |
Reference:
|
| pp. 67-72, Tampere, Finland, 2012
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» Model-Based Diagnosis versus Error Explanation
|
|
|
|
Author:
|
|
Heinz Riener, Görschwin Fey |
| Workshop: |
|
International Workshop on System Level-Design of Automotive Electronics/Software (SLDAES'12) in conjunction with 49th Design Automation Conference (DAC'12) |
Reference:
|
| San Francisco, USA, 2012
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» FAuST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation
|
|
|
|
Author:
|
|
Heinz Riener, Görschwin Fey |
| Workshop: |
|
19th International SPIN Workshop on Model Checking of Software (SPIN'12) |
Reference:
|
| pp. 234-240, Oxford, United Kingdoms, 2012
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» Functional Analysis of Circuits Under Timing
Variations
|
|
|
|
Author:
|
|
Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan |
| Workshop: |
|
edaWorkshop |
Reference:
|
| Hannover, Germany, 2012
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» Automated Debugging from Pre-Silicon to Post-Silicon
|
|
|
|
Author:
|
|
Mehdi Dehbashi, Görschwin Fey |
| Workshop: |
|
24. GI/GMM/ITG Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
|
Reference:
|
| Cottbus, Germany, 2012
| Hyperlink:
|
| [Link to the Workshop]
|
» Automated Feature Localization for Hardware Designs using Coverage Metrics
|
|
|
|
Author:
|
|
Jan Malburg, Alexander Finder, Görschwin Fey |
| Workshop: |
|
15. Workshop Methoden und Beschreibungssprachen
zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) |
Reference:
|
| Kaiserslautern, 2012
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» metaSMT: Focus on Your Application not on Solver Integration
|
|
|
|
Author:
|
|
Finn Haedicke, Stefan Frehse, Görschwin Fey, Daniel Große, Rolf Drechsler |
| Workshop: |
|
DIFTS'11: 1st International workshop on design and implementation of formal tools and systems |
Reference:
|
| pp. 22-29, Austin, USA, 2011
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» Test Case Generation from Mutants using Model Checking Techniques
|
|
|
|
Author:
|
|
Heinz Riener, Roderick Bloem, Görschwin Fey |
| Workshop: |
|
IEEE Fourth International Conference on Software Testing, Verification and Validation Workshops (ICSTW'11) |
Reference:
|
| pp 388 - 397, Berlin, Germany, 2011
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» Towards Automatic Property Generation for the Formal Verification of Bus Bridges
|
|
|
|
Author:
|
|
Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Reference:
|
| Oldenburg, 2011
| Hyperlink:
|
| [Link to the Workshop]
|
» Latency Analysis for Sequential Circuits
|
|
|
|
Author:
|
|
Alexander Finder, André Sülflow, Görschwin Fey |
| Workshop: |
|
23. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2011 |
Reference:
|
| Passau, 2011
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» Towards Unifying Localization and Explanation for Automated Debugging
|
|
|
|
Author:
|
|
Görschwin Fey, André Sülflow, Rolf Drechsler |
| Workshop: |
|
11th International Workshop on Microprocessor Test and Verification (MTV) |
Reference:
|
| pp. 3-8, Austin, Texas, 2010
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» Evaluating Debugging Algorithms from a Qualitative Perspective
|
|
|
|
Author:
|
|
Alexander Finder, Görschwin Fey |
| Workshop: |
|
International Workshop on Boolean Problems |
Reference:
|
| Freiberg, 2010
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» RobuCheck: A Robustness Checker for Digital Circuits
|
|
|
|
Author:
|
|
Stefan Frehse, Görschwin Fey, Andre Sülflow and Rolf Drechsler
|
| Workshop: |
|
The First International Workshop on Dynamic Aspects
in Dependability Models for Fault-Tolerant Systems (DYADEM-FTS) |
Reference:
|
| Valencia, 2010
| Hyperlink:
|
| [Link to the Workshop]
|
» A Better-Than-Worst-Case Robustness Measure
|
|
|
|
Author:
|
|
Stefan Frehse,
Görschwin Fey,
Rolf Drechsler |
| Workshop: |
|
22. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2010 |
Reference:
|
| Paderborn, 2010
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» Using QBF to Increase the Accuracy of SAT-Based Debugging
|
|
|
|
Author:
|
|
Andre Sülflow, Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
International Workshop on Constraints in Formal Verification (CFV) |
Reference:
|
| Grenoble, France, 2009
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
|
» Robustness Check for Multiple Faults using Formal Techniques
|
|
|
|
Author:
|
|
Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler |
| Workshop: |
|
Constraints in Formal Verification (CFV) |
Reference:
|
| Grenoble, France, 2009
| PDF:
|
| [view Pdf]
| Hyperlink:
|
| [Link to the Workshop]
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» FormED: A Formal Environment for Debugging
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Author:
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Andre Sülflow, Robert Wille, Christian Genz, Görschwin Fey, Rolf Drechsler |
| Workshop: |
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University Booth at Design, Automation and Test in Europe (DATE09) |
Reference:
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| Nizza, 2009
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| [view Pdf]
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| [Link to the Workshop]
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» Algorithms for ATPG under Leakage Constraints
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Author:
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Görschwin Fey |
| Workshop: |
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21. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2009 |
Reference:
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| Bremen, 2009
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| [view Pdf]
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| [Link to the Workshop]
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» Increasing the Accuracy of SAT-based Debugging
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Author:
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Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
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12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Reference:
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| pp. 47-56, Berlin, 2009
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| [view Pdf]
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| [Link to the Workshop]
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» Computing Bounds for Fault Tolerance using Formal Techniques
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Author:
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Andre Sülflow, Görschwin Fey, Stefan Frehse, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
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IEEE Workshop on Design for Reliability and Variability (DRV) |
Reference:
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| Santa Clara, USA, 2008
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| [view Pdf]
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| [Link to the Workshop]
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» Experimental Studies on SMT-based Debugging
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Author:
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Andre Sülflow, Görschwin Fey, Rolf Drechsler |
| Workshop: |
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IEEE 9th Workshop on RTL and High Level Testing (WRTLT'08) |
Reference:
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| pp. 93-98, Japan, 2008
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| [view Pdf]
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| [Link to the Workshop]
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» Effiziente automatische Generierung von Assertions für industrielle Hardware-Designs
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Author:
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Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke |
| Workshop: |
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Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS) |
Reference:
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| Dresden, 2008
| Hyperlink:
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| [Link to the Workshop]
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» Targeting Leakage Constraints during ATPG
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Author:
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Görschwin Fey, Satoshi Komatsu, Yasuo Furukawa, Masahiro Fujita
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| Workshop: |
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IEEE International Workshop on Silicon Debug and Diagnosis |
Reference:
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| San Diego, 2008
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| [view Pdf]
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| [Link to the Workshop]
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» Debugging Design Errors by Using Unsatisfiable Cores
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Author:
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Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
| Workshop: |
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11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen
zur Modellierung und Verifikation von Schaltungen und Systemen" |
Reference:
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| pp. 159-168, Freiburg, 2008
| PDF:
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| [view Pdf]
| Hyperlink:
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| [Link to the Workshop]
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» Formal Robustness Checking
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Author:
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Görschwin Fey, Rolf Drechsler |
| Workshop: |
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Workshop on Constraints in Formal Verification, 2007 |
Reference:
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| Bremen, 2007
| PDF:
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| [view Pdf]
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| [Link to the Workshop]
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» Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
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Author:
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Rolf Drechsler, Görschwin Fey, Jürgen Schlöffel |
| Workshop: |
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edaWorkshop 2007 |
Reference:
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| Hannover, 2007
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| [Link to the Workshop]
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» Building Free Binary Decision Diagrams Using SAT Solvers
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Author:
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Robert Wille, Görschwin Fey, Rolf Drechsler |
| Workshop: |
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8th Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM2007) |
Reference:
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| Oslo, 2007
| Hyperlink:
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| [Link to the Workshop]
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» SAT-based ATPG for Path Delay Fault in Industrial Circuits
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Author:
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Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel |
| Workshop: |
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IEEE European Test Symposium (ETS), Informal Digest of Papers |
Reference:
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| Freiburg, 2007
| Hyperlink:
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| [Link to the Workshop]
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» Estimating the Quality of AND-EXOR Optimization Results
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Author:
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Sebastian Kinder, Görschwin Fey and Rolf Drechsler |
| Workshop: |
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8th Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM2007) |
Reference:
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| Oslo, 2007
| Hyperlink:
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| [Link to the Workshop]
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» Studies on Integrating SAT-based ATPG in an Industrial Environment
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Author:
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Daniel Tille, Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
| Workshop: |
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19. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
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Reference:
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| Erlangen, 2007
| PDF:
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| [view Pdf]
| Hyperlink:
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| [Link to the Workshop]
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» Instance Generation for SAT-based ATPG
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Author:
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Daniel Tille, Görschwin Fey, Rolf Drechsler |
| Workshop: |
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10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems |
Reference:
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| Krakau, 2007
| PDF:
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| [view Pdf]
| Hyperlink:
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| [Link to the Workshop]
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» Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse
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Author:
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Andre Sülflow, Görschwin Fey, Rolf Drechsler |
| Workshop: |
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GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Reference:
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| pp. 101-110, Erlangen, 2007
| PDF:
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| [view Pdf]
| Hyperlink:
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| [Link to the Workshop]
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» Formal Verification on the Word Level using SAT-like Proof
Techniques
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Author:
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Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler |
| Workshop: |
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GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Reference:
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| pp. 165-173, Erlangen, 2007
| Hyperlink:
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| [Link to the Workshop]
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» Efficiency of Multi-Valued Encoding in SAT-based ATPG
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Author:
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Görschwin Fey, Junhao Shi , Rolf Drechsler |
| Workshop: |
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18. Workshop „Testmethoden und Zuverlässigkeit von Schaltungen und Systemen“
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Reference:
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| Titisee, 2006
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» SAT-Based Calculation of Source Code Coverage for BMC
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Author:
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Görschwin Fey, Rolf Drechsler |
| Workshop: |
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GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Reference:
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| Dresden, 2006
| PDF:
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| [view Pdf]
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» SyCE: An Integrated Environment for System Design in SystemC
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Author:
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Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große |
| Workshop: |
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16th IEEE International Workshop on Rapid System Prototyping (RSP) |
Reference:
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| pp. 258-260, Montreal, 2005
| PDF:
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| [view Pdf]
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» PASSAT: Efficient SAT-based Test Pattern Generation
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Author:
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Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
| Workshop: |
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IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Reference:
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| Sopron, 2005
| PS:
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| [view PS]
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» Efficient Hierarchical System Debugging for Property Checking
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Author:
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Görschwin Fey, Rolf Drechsler |
| Workshop: |
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IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Reference:
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| Sopron, 2005
| PDF:
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| [view Pdf]
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» ParSyC: An Efficient SystemC Parser
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Author:
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Görschwin Fey, Daniel Große, Tim Cassens, Christian Genz, Tim Warode, Rolf Drechsler |
| Workshop: |
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12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2004) |
Reference:
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| pp. 148-154, Kanazawa, 2004
| PDF:
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| [view Pdf]
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» Design Understanding by Automatic Property Generation
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Author:
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Rolf Drechsler, Görschwin Fey |
| Workshop: |
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12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2004) |
Reference:
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| pp.274-281, Kanazawa, 2004
| PDF:
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| [view Pdf]
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» Experimental Studies on Test Pattern Generation for BDD Circuits
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Author:
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Junhao Shi, Görschwin Fey, Rolf Drechsler |
| Workshop: |
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International Workshop on Boolean Problems (IWSBP) |
Reference:
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| pp. 71-76, Freiberg, 2004
| PDF:
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| [view Pdf]
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» Visualization of Diagnosis Results for Design Debugging
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Author:
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Görschwin Fey, Rolf Drechsler |
| Workshop: |
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13th International Workshop on Post-Binary ULSI Systems |
Reference:
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| pp. 1-2, Toronto, 2004
| PS:
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| [view PS]
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» Disjoint Sum of Product Minimization by Evolutionary Algorithms
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Author:
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Nicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler |
| Workshop: |
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1st European Workshop on Hardware Optimisation Techniques (EvoHOT) |
Reference:
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| Applications of Evolutionary Computing: EvoWorkshops 2004, LNCS 3005, p. 198-207, Coimbra, 2004
| PDF:
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| [view Pdf]
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» An Approach to Formal Verification of Reconfigurable Systems
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Author:
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Görschwin Fey, Rolf Drechsler, Muazzam Ali |
| Workshop: |
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1st IFIP WG 10.5 Workshop on "Frontiers in Automotive Electronics"
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Reference:
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| Darmstadt, 2003
| PS:
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| [view PS]
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» BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
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Author:
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Junhao Shi, Görschwin Fey and Rolf Drechsler |
| Workshop: |
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IEEE European Test Workshop (ETW'03) |
Reference:
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| pp. 109-110, Maastricht, 2003
| PDF:
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| [view Pdf]
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» BDD Circuit Optimization for Path Delay Fault-Testability
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Author:
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Görschwin Fey, Junhao Shi, Rolf Drechsler |
| Workshop: |
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15th ITG/GMM/GI Workshop Test methods and Reliability of Circuits and Systems |
Reference:
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| Timmendorfer Strand, 2003
| PS:
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| [view PS]
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» A Hybrid Approach Combining Symbolic and Structural Techniques for Disjoint SOP Minimization
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Author:
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Görschwin Fey, Rolf Drechsler |
| Workshop: |
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11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2003) |
Reference:
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| pp. 54-60, Hiroshima, 2003
| PS:
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| [view PS]
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» Cost-efficient Formal Block Verification for ASIC Design
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Author:
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K. Winkelmann, J. Trylus, D. Stoffel, Görschwin Fey |
| Workshop: |
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GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Reference:
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| Bremen, 2003, pages 184-188
| PDF:
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| [view Pdf]
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» Minimizing the Number of Paths in BDDs
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Author:
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Görschwin Fey, Rolf Derchsler |
| Workshop: |
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International Workshop on Boolean Problems |
Reference:
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| Freiberg, 2002, pages 149 - 156
| PDF:
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| [view Pdf]
| PS:
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| [view PS]
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