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Home « Team « Publications
» Publications of
Mathias Soeken
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BOOKS |
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» Auf dem Weg zum Quantencomputer - Entwurf reversibler Logik
[Read more about this book!]
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Publisher: |
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Shaker Verlag |
Author:
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Rolf Drechsler, Mathias Soeken, Robert Wille (Hrsg.) |
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gebunden |
Year:
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2012
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BOOK CONTRIBUTIONS |
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JOURNALS |
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» RevKit: An Open Source Toolkit for the Design of Reversible Circuits
[Link to the Homepage of this journal]
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Author:
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Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler |
| Journal: |
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Reversible Computation 2011 (Series: Lecture Notes in Computer Science) |
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Volume 7165, Third International Workshop, RC 2011, Revised Papers |
Year:
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2012
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» RevKit: A Toolkit for Reversible Circuit Design
[Link to the Homepage of this journal]
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Author:
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Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler |
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Multiple-Valued Logic and Soft Computing |
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Volume 18, Number 1, pp. 55-65 |
Year:
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2012
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CONFERENCES |
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» White Dots do Matter: Rewriting Reversible Logic Circuits
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Author:
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Mathias Soeken, Michael Kirkedal Thomsen |
| Conference: |
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Reversible Computation |
Reference:
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| Victoria, Canada, 2013
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| [To the Site of this Conference]
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» Reducing the Depth of Quantum Circuits Using Additional Lines
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Author:
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Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler |
| Conference: |
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Reversible Computation |
Reference:
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| Victoria, Canada, 2013
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Hardware-Software Co-Visualization: Developing Systems in the Holodeck
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Author:
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Rolf Drechsler, Mathias Soeken |
| Conference: |
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16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Reference:
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| Karlovy Vary, Czech Republic, 2013
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Debugging of Reversible Circuits using πDDs
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Author:
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Laura Tague, Mathias Soeken, Shin-ichi Minato, Rolf Drechsler |
| Conference: |
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43rd International Symposium on Multiple-Valued Logic (ISMVL) |
Reference:
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| Toyama, 2013
| Hyperlink:
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| [To the Site of this Conference]
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» Exact Template Matching Using Boolean Satisfiability
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Author:
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Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler |
| Conference: |
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43rd International Symposium on Multiple-Valued Logic (ISMVL) |
Reference:
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| Toyama, 2013
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Determining Relevant Model Elements for the Verification of UML/OCL Specifications
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Author:
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Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler |
| Conference: |
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Design, Automation and Test in Europe (DATE) |
Reference:
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| Grenoble, France, 2013
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Towards a Generic Verification Methodology for System Models
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Author:
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Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler |
| Conference: |
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Design, Automation and Test in Europe (DATE) |
Reference:
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| Grenoble, France, 2013
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Improving the Mapping of Reversible Circuits to Quantum Circuits Using Multiple Target Lines
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Author:
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Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler |
| Conference: |
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Asia and South Pacific Design Automation Conference (ASP-DAC) |
Reference:
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| Yokohama, Japan, 2013
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Towards Dialog Systems for Assisted Natural Language Processing in the Design of Embedded Systems
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Author:
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Rolf Drechsler, Mathias Soeken, Robert Wille |
| Conference: |
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IEEE Design and Test Symposium 2012 (IDT) |
Reference:
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| Doha, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Completeness-Driven Development
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Author:
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Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille |
| Conference: |
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International Conference on Graph Transformation |
Reference:
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| pp. 38-50, Bremen, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Formal Specification Level: Towards Verification-driven Design Based on Natural Language Processing
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Author:
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Rolf Drechsler, Mathias Soeken, Robert Wille |
| Conference: |
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Forum on specification & Design Languages (FDL) |
Reference:
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| pp. 53-58, Vienna, Austria, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Circuit Line Minimization in the HDL-based Synthesis of Reversible Logic
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Author:
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Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler |
| Conference: |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Reference:
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| pp. 213-218, Amherst, USA, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Assisted Behavior Driven Development Using Natural Language Processing
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Author:
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Mathias Soeken, Robert Wille, Rolf Drechsler |
| Conference: |
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50th International Conference on Objects, Models, Components, Patterns (TOOLS) |
Reference:
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| pp. 269-287, Prague, Czech Republic, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits
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Author:
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Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler |
| Conference: |
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42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Reference:
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| 2012, Victoria
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» A Synthesis Flow for Sequential Reversible Circuits
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Author:
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Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler |
| Conference: |
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42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Reference:
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| 2012, Victoria
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines
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Author:
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Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler |
| Conference: |
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42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Reference:
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| Victoria, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Eliminating Invariants in UML/OCL Models
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Author:
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Mathias Soeken, Robert Wille, Rolf Drechsler
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| Conference: |
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Design, Automation and Test in Europe (DATE) |
Reference:
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| pp. 1142-1145, Dresden, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Debugging of Inconsistent UML/OCL Models
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Author:
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Robert Wille, Mathias Soeken, Rolf Drechsler
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| Conference: |
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Design, Automation and Test in Europe (DATE) |
Reference:
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| pp. 1078-1083, Dresden, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Synthesis of Reversible Circuits with Minimal Lines for Large Functions
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Author:
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Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler |
| Conference: |
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Asia and South Pacific Design Automation Conference (ASP-DAC) |
Reference:
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| pp. 85-92, Sydney, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Encoding OCL Data Types for SAT-based Verification of UML/OCL Models
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Author:
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Mathias Soeken, Robert Wille, Rolf Drechsler |
| Conference: |
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5th International Conference on Tests & Proofs (TAP) |
Reference:
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| pp. 152-170, Zurich, 2011
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Automatic Property Generation for the Formal Verification of Bus Bridges
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Author:
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Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler |
| Conference: |
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14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Reference:
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| pp. 417-422, Cottbus, 2011
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Designing a RISC CPU in Reversible Logic
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Author:
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Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler |
| Conference: |
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41st International Symposium on Multiple-Valued Logic (ISMVL) |
Reference:
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| pp. 170-175, Tuusula, 2011
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Verifying Dynamic Aspects of UML Models
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Author:
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Mathias Soeken, Robert Wille, Rolf Drechsler |
| Conference: |
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Design, Automation and Test in Europe (DATE) |
Reference:
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| pp. 1077-1082, Grenoble, 2011
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Reducing the Number of Lines in Reversible Circuits
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Author:
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Robert Wille, Mathias Soeken, Rolf Drechsler |
| Conference: |
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Design Automation Conference (DAC) |
Reference:
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| pp. 647-652, Anaheim, 2010
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Window Optimization of Reversible and Quantum Circuits
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Author:
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Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Conference: |
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13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Reference:
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| pp. 431-435, Vienna, 2010
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Verifying UML/OCL Models Using Boolean Satisfiability
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Author:
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Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler |
| Conference: |
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Design, Automation and Test in Europe (DATE) |
Reference:
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| pp. 1341-1344, Dresden, 2010
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability
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Author:
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Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler |
| Conference: |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Reference:
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| pp. 411-416, Montpellier, 2008
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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WORKSHOPS |
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» lips: An IDE for Model Driven Engineering Based on Natural Language Processing
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Author:
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Oliver Keszöcze, Mathias Soeken, Eugen Kuksa, Rolf Drechsler |
| Workshop: |
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Workshop on Natural Language Analysis in Software Engineering (NaturaLiSE) |
Reference:
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| pp. 31-38, San Francisco, 2013
| PDF:
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| [view Pdf]
| Hyperlink:
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| [Link to the Workshop]
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» Towards Automatic Scenario Generation from Coverage Information
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Author:
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Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler |
| Workshop: |
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8th International Workshop on Automation of Software Test (AST) |
Reference:
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| pp. 82-88, San Francisco, 2013
| PDF:
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| [view Pdf]
| Hyperlink:
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| [Link to the Workshop]
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» Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen
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Author:
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Mathias Soeken, Robert Wille, Eugen Kuksa, Rolf Drechsler |
| Workshop: |
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16. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Reference:
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| Rostock, 2013
| Hyperlink:
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| [Link to the Workshop]
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» Verification of Embedded Systems Using Modeling and Implementation Languages
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Author:
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Mathias Soeken, Heinz Riener, Robert Wille, Görschwin Fey, Rolf Drechsler |
| Workshop: |
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International Workshop on Metamodelling and Code Generation for Embedded Systems (MeCoEs'12) |
Reference:
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| pp. 67-72, Tampere, Finland, 2012
| PDF:
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| [view Pdf]
| Hyperlink:
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| [Link to the Workshop]
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» Behavior Driven Development for Circuit Design and Verification
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Author:
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Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler |
| Workshop: |
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IEEE International Workshop on High-Level Design Validation and Test (HLDVT) |
Reference:
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| Huntington Beach, USA, 2012
| PDF:
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| [view Pdf]
| Hyperlink:
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| [Link to the Workshop]
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» Towards Embedding of Large Functions for Reversible Logic
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Author:
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Mathias Soeken, Robert Wille, Laura Tague, D. Michael Miller, Rolf Drechsler |
| Workshop: |
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International Workshop on Boolean Problems |
Reference:
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| Freiberg, 2012
| Hyperlink:
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| [Link to the Workshop]
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» Using πDDs in the Design for Reversible Circuits
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Author:
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Mathias Soeken, Robert Wille, Shin-Ichi Minato, Rolf Drechsler |
| Workshop: |
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Workshop on Reversible Computation |
Reference:
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| Kopenhagen, 2012
| Hyperlink:
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| [Link to the Workshop]
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» Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams
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Author:
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Julia Seiter, Mathias Soeken, Robert Wille, Rolf Drechsler |
| Workshop: |
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Workshop on Reversible Computation |
Reference:
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| Kopenhagen, 2012
| Hyperlink:
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| [Link to the Workshop]
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» Towards Automatic Determination of Problem Bounds for Object Instantiation in Static Model Verification
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Author:
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Mathias Soeken, Robert Wille, Rolf Drechsler |
| Workshop: |
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Model-Driven Engineering, Verification, And Validation (MoDeVVa) |
Reference:
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| Wellington, 2011
| Hyperlink:
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| [Link to the Workshop]
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» Synthesis of Reversible Circuits with Minimal Lines for Large Functions
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Author:
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Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler |
| Workshop: |
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Workshop on Reversible Computation |
Reference:
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| pp. 59-70, Gent, 2011
| Hyperlink:
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| [Link to the Workshop]
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» Customized Design Flows for Reversible Circuits Using RevKit
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Author:
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Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler |
| Workshop: |
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Workshop on Reversible Computation |
Reference:
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| pp. 91-96, Gent, 2011
| Hyperlink:
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| [Link to the Workshop]
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» Designing a RISC CPU in Reversible Logic
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Author:
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Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler |
| Workshop: |
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14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Reference:
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| pp. 249-258, Oldenburg, 2011
| Hyperlink:
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| [Link to the Workshop]
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» Towards Automatic Property Generation for the Formal Verification of Bus Bridges
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Author:
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Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler |
| Workshop: |
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14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Reference:
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| Oldenburg, 2011
| Hyperlink:
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| [Link to the Workshop]
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» Hierarchical Synthesis of Reversible Circuits Using Positive and Negative Davio Decomposition
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Author:
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Mathias Soeken, Robert Wille, Rolf Drechsler |
| Workshop: |
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5th International Design & Test Workshop (IDT) |
Reference:
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| pp. 143-148, Abu Dhabi, 2010
| PDF:
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| [view Pdf]
| Hyperlink:
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| [Link to the Workshop]
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» RevKit: A Toolkit for Reversible Circuit Design
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Author:
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Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler |
| Workshop: |
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Workshop on Reversible Computation |
Reference:
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| pp. 69-72, Bremen, 2010
| PDF:
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| [view Pdf]
| Hyperlink:
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| [Link to the Workshop]
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» Hierarchical Synthesis of Reversible Circuits Using Positive and Negative Davio Decomposition
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Author:
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Mathias Soeken, Robert Wille, Rolf Drechsler |
| Workshop: |
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Workshop on Reversible Computation |
Reference:
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| pp. 55-58, Bremen, 2010
| Hyperlink:
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| [Link to the Workshop]
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» Verifying UML/OCL Models Using Boolean Satisfiability
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Author:
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Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler |
| Workshop: |
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13. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Reference:
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| pp 57-66, Dresden, 2010
| Hyperlink:
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| [Link to the Workshop]
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