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Home « Team « Publications
» Publications of
Nils Przigoda
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BOOKS |
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BOOK CONTRIBUTIONS |
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JOURNALS |
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» Towards a Verification Flow Across Abstraction Levels:
Verifying Implementations Against Their Formal Specification
[Link to the Homepage of this journal]
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Author:
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Pablo Gonzalez-de-Aledo, Nils Przigoda, Robert Wille, Rolf Drechsler, Pablo Sanchez |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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36(3):475-488, DOI: 10.1109/TCAD.2016.2611494
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Year:
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2017
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» Verifying the Structure and Behavior in UML/OCL Models Using Satisfiability Solvers
[Link to the Homepage of this journal]
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Author:
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Nils Przigoda, Mathias Soeken, Robert Wille, Rolf Drechsler |
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IET Cyber-Physical Systems: Theory & Applications |
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Volume 1, Issue 1, December 2016, pp. 49-59
DOI: 10.1049/iet-cps.2016.0022
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2016
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» Analyzing Inconsistencies in UML/OCL Models
[Link to the Homepage of this journal]
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Author:
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Nils Przigoda, Robert Wille, Rolf Drechsler |
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Journal of Circuits, Systems and Computers |
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Volume 25, Issue 03, March 2016DOI: 10.1142/S0218126616400211 |
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2016
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» Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits
[Link to the Homepage of this journal]
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Author:
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Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler |
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Multiple-Valued Logic and Soft Computing |
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Volume 21, Number 5-6, 2013, pp. 627-640 |
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2013
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CONFERENCES |
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» More than true or false: Native Support of Irregular Values in the Automatic Validation & Verification of UML/OCL Models
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Author:
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Nils Przigoda, Philipp Niemann, Judith Peters, Frank Hilken, Robert Wille, Rolf Drechsler |
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15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) |
Reference:
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| Vienna, Austria, 2017
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| [To the Site of this Conference]
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» Clocks vs. Instants Relations: Verifying CCSL Time Constraints in UML/MARTE Models
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Author:
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Judith Peters, Nils Przigoda, Robert Wille, Rolf Drechsler |
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14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) |
Reference:
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| Indian Institute of Technology, Kanpur, India, 2016
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» Frame Conditions in Symbolic Representations of UML/OCL Models
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Author:
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Nils Przigoda, Jonas Gomes Filho, Philipp Niemann, Robert Wille, Rolf Drechsler |
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14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) |
Reference:
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| Indian Institute of Technology, Kanpur, India, 2016
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» Towards a Model-Based Verification Methodology
for Complex Swarm Systems
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Author:
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Jonas Gomes Filho, Nils Przigoda, Robert Wille, Rolf Drechsler |
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International Symposium on Electronic System Design (ISED) |
Reference:
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| Patna, Indien, 2016
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» Ground Setting Properties for an Efficient Translation of OCL in SMT-based Model Finding
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Author:
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Nils Przigoda, Robert Wille, Rolf Drechsler |
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ACM/IEEE 19th International Conference on Model Driven Engineering Languages and Systems (MoDELS) |
Reference:
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| Saint Malo, Brittany, France, 2016
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» Fault Detection in Parity Preserving Reversible Circuits
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Author:
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Nils Przigoda, Gerhard Dueck, Robert Wille, Rolf Drechsler |
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46th International Symposium on Multiple-Valued Logic (ISMVL) |
Reference:
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| Sapporo, Japan, 2016
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» Checking Concurrent Behavior in UML/OCL Models
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Author:
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Nils Przigoda, Christoph Hilken, Robert Wille, Jan Peleska, Rolf Drechsler |
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ACM/IEEE 18th International Conference on Model Driven Engineering Languages and Systems (MoDELS) |
Reference:
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| Ottawa, Kanada, 2015
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» Leveraging the Analysis for Invariant Independence in Formal System Models
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Author:
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Nils Przigoda, Robert Wille, Rolf Drechsler |
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Euromicro Conference on Digital System Design (DSD) |
Reference:
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| Funchal, Madeira, Portugal, 2015
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» Verification-driven Design Across Abstraction Levels - A Case Study
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Author:
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Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, Rolf Drechsler |
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Euromicro Conference on Digital System Design (DSD) |
Reference:
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| Funchal, Madeira, Portugal, 2015
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» Contradiction Analysis for Inconsistent Formal Models
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Author:
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Nils Przigoda, Robert Wille, Rolf Drechsler |
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IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15) |
Reference:
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| Belgrade, Serbia, 2015
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» A Generic Representation of CCSL Time Constraints for UML/MARTE Models
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Author:
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Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler |
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Design Automation Conference (DAC) |
Reference:
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| San Francisco, 2015
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» A Compact and Efficient SAT Encoding for Quantum Circuits
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Author:
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Robert Wille, Nils Przigoda, Rolf Drechsler |
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IEEE Africon |
Reference:
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| Mauritius, 2013
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» Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines
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Author:
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Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler |
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42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Reference:
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| pp. 69-74, Victoria, Canada, 2012
| Hyperlink:
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» Synthesis of Reversible Circuits with Minimal Lines for Large Functions
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Author:
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Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler |
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Asia and South Pacific Design Automation Conference (ASP-DAC) |
Reference:
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| pp. 85-92, Sydney, 2012
| Hyperlink:
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WORKSHOPS |
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» Integrating an SMT-based Model Finder into USE
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Author:
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Nils Przigoda, Frank Hilken, Judith Peters, Robert Wille, Martin Gogolla, Rolf Drechsler |
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Workshop on Model-Driven Engineering, Verification, and Validation (MoDeVVa) |
Reference:
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| Saint-Malo, France, 2016
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» Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses
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Author:
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Nils Przigoda, Judith Peters, Mathias Soeken, Robert Wille, Rolf Drechsler |
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Workshop on Model-Driven Engineering, Verification, and Validation (MoDeVVa) |
Reference:
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| Ottawa, Canada, 2015
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» Verbesserung der Fehlersuche in inkonsistenten formalen Modellen
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Author:
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Nils Przigoda, Robert Wille, Rolf Drechsler |
| Workshop: |
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18. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'15) |
Reference:
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| Chemnitz, Germany, 2015
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| [Link to the Workshop]
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» Synthesis of Reversible Circuits with Minimal Lines for Large Functions
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Author:
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Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler |
| Workshop: |
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Workshop on Reversible Computation |
Reference:
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| pp. 59-70, Gent, 2011
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| [Link to the Workshop]
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