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Home « Team « Publications
» Publications of
Robert Wille
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BOOKS |
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BOOK CONTRIBUTIONS |
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| » Debugging Contradictory Constraints in Constraint-based Random Simulation |
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Author:
| Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
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| Editor: | Martin Radetzki |
| Booktitle: | Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL'08 |
| Publisher: | Springer |
| Sites: | 273-290 |
| Year: | 2009 |
| Format: | gebunden |
| » SWORD: A SAT like Prover Using Word Level Information |
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Author:
| Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
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| Editor: | Ricardo Reis, Vincent Mooney, Paul Hasler |
| Booktitle: | VLSI-SoC: Advanced Topics on Systems on a Chip:
A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip |
| Publisher: | Springer |
| Sites: | 175-192 |
| Year: | 2009 |
| Format: | Hardcover |
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JOURNALS |
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» Exact Synthesis of Elementary Quantum Gate Circuits
[Link to the Homepage of this journal]
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Author:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
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Multiple-Valued Logic and Soft Computing |
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Volume 15, Number 4, pp. 283-300 |
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2009
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» Exact Multiple Control Toffoli Network Synthesis with SAT Techniques
[Link to the Homepage of this journal]
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Author:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Journal: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 28, Number 5, pp. 703-715, May |
Year:
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2009
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» Building Free Binary Decision Diagrams Using SAT Solvers
[Link to the Homepage of this journal]
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Author:
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Robert Wille, Görschwin Fey, Rolf Drechsler |
| Journal: |
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Facta Universitatis, Series: Electronics and Energetics |
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Volume 20, Number 3, pp. 381-394, |
Year:
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2007
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CONFERENCES |
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» Verifying UML/OCL Models Using Boolean Satisfiability
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Author:
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Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler |
| Conference: |
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Design, Automation and Test in Europe (DATE) |
Reference:
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| Dresden, 2010
| Hyperlink:
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| [To the Site of this Conference]
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» SMT-based Stimuli Generation in the SystemC Verification Library
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Author:
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Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler |
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Forum on specification & Design Languages (FDL) |
Reference:
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| Sophia Antipolis, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Synthesizing Reversible Circuits for Irreversible Functions
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Author:
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D. Michael Miller, Robert Wille, Gerhard W. Dueck |
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Euromicro Conference on Digital System Design (DSD) |
Reference:
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| pp. 749-756, Patras, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» BDD-based Synthesis of Reversible Logic for Large Functions
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Author:
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Robert Wille, Rolf Drechsler |
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Design Automation Conference (DAC) |
Reference:
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| pp. 270-275, San Francisco, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Contradictory Antecedent Debugging in Bounded Model Checking
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Author:
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Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
| Conference: |
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Great Lakes Symposium on VLSI (GLSVLSI) |
Reference:
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| pp. 173-176, Boston, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Evaluation of Cardinality Constraints on SMT-based Debugging
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Author:
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Andre Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler |
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39th International Symposium on Multiple-Valued Logic (ISMVL) |
Reference:
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| pp. 298-303, Naha, Okinawa, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Equivalence Checking of Reversible Circuits
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Author:
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Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler |
| Conference: |
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39th International Symposium on Multiple-Valued Logic (ISMVL) |
Reference:
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| pp. 324-330, Naha, Okinawa, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Debugging of Toffoli Networks
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Author:
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Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
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| Conference: |
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Design, Automation and Test in Europe (DATE) |
Reference:
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| pp. 1284-1289, Nice, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Reversible Logic Synthesis with Output Permutation
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Author:
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Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
| Conference: |
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22nd International Conference on VLSI Design |
Reference:
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| pp. 189-194, New Delhi, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking
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Author:
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Robert Wille, Görschwin Fey, Marc Messing, Gerhard
Angst, Lothar Linhard, Rolf Drechsler |
| Conference: |
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Euromicro Conference on Digital System Design (DSD) |
Reference:
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| pp. 542-549, Parma, 2008
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Contradiction Analysis for Constraint-based Random Simulation
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Author:
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Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler |
| Conference: |
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Forum on specification & Design Languages (FDL) |
Reference:
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| pp. 130-135, Stuttgart, 2008
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability
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Author:
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Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler |
| Conference: |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Reference:
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| pp. 411-416, Montpellier, 2008
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» RevLib: An Online Resource for
Reversible Functions and Reversible Circuits
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Author:
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Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler |
| Conference: |
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38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Reference:
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| pp. 220-225, Dallas, 2008
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Exact Synthesis of Elementary Quantum Gate
Circuits for Reversible Functions with Don’t Cares
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Author:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Conference: |
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38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Reference:
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| pp. 214-219, Dallas, 2008
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Quantified Synthesis of Reversible Logic
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Author:
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Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große |
| Conference: |
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Design, Automation, and Test in Europe (DATE) |
Reference:
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| pp. 1015-1020, Munich, 2008
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Fast Exact Toffoli Network Synthesis of Reversible Logic
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Author:
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Robert Wille, Daniel Große |
| Conference: |
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IEEE International Conference on Computer Aided Design (ICCAD) |
Reference:
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| pp. 60-64, San Jose, 2007
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» SWORD: A SAT like Prover Using Word Level Information
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Author:
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Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler |
| Conference: |
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IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC) |
Reference:
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| pp. 88-93, Atlanta, 2007
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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WORKSHOPS |
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» Reducing Reversible Circuit Cost by Adding Lines
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Author:
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D. Michael Miller, Robert Wille, Rolf Drechsler |
| Workshop: |
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International Workshop on Logic Synthesis (IWLS) |
Reference:
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| Berkeley, 2009
| Hyperlink:
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| [Link to the Workshop]
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» Synthesis of Reversible Functions Beyond Gate Count and Quantum Cost
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Author:
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Robert Wille, Mehdi Saeedi, Rolf Drechsler |
| Workshop: |
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International Workshop on Logic Synthesis (IWLS) |
Reference:
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| Berkeley, 2009
| PDF:
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| [view Pdf]
| Hyperlink:
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| [Link to the Workshop]
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» Synthesizing Reversible Logic: An Overview
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Author:
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Robert Wille, Rolf Drechsler |
| Workshop: |
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Reed-Muller Workshop |
Reference:
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| Naha, Okinawa, 2009
| Hyperlink:
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| [Link to the Workshop]
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» Synthesising Reversible Circuits from Irreversible Specifications using Reed-Muller Spectral Techniques
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Author:
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D. Michael Miller, Gerhard W. Dueck, Robert Wille |
| Workshop: |
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Reed-Muller Workshop |
Reference:
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| Naha, Okinawa, 2009
| Hyperlink:
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| [Link to the Workshop]
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» FormED: A Formal Environment for Debugging
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Author:
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Andre Sülflow, Robert Wille, Christian Genz, Görschwin Fey, Rolf Drechsler |
| Workshop: |
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University Booth at Design, Automation and Test in Europe (DATE09) |
Reference:
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| Nizza, 2009
| PDF:
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| [view Pdf]
| Hyperlink:
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| [Link to the Workshop]
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» Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic
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Author:
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Robert Wille, Rolf Drechsler |
| Workshop: |
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Reversible Computation |
Reference:
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| York, 2009
| Hyperlink:
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| [Link to the Workshop]
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» Equivalence Checking of Reversible Circuits
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Author:
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Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler |
| Workshop: |
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12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Reference:
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| 2009
| Hyperlink:
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| [Link to the Workshop]
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» Reversible Logic Synthesis with Output Permutation
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Author:
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Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
| Workshop: |
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International Workshop on Boolean Problems |
Reference:
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| Freiberg, 2008
| Hyperlink:
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| [Link to the Workshop]
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» Contradiction Analysis for Constraint-based Random Simulation
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Author:
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Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler |
| Workshop: |
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Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS)
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Reference:
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| pp. 25-30, Dresden, 2008
| Hyperlink:
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| [Link to the Workshop]
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» Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking
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Author:
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Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
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11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen
zur Modellierung und Verifikation von Schaltungen und Systemen" |
Reference:
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| pp. 169-178, Freiburg, 2008
| Hyperlink:
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| [Link to the Workshop]
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» Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits
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Author:
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Andre Sülflow, Ulrich Kühne, Robert Wille, Daniel Große, Rolf Drechsler |
| Workshop: |
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IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07) |
Reference:
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| pp. 31-36, Beijing, P.R.China, 2007
| PDF:
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| [view Pdf]
| Hyperlink:
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| [Link to the Workshop]
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» Parallelisierung von SAT-basierter Testmustergenerierung
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Author:
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Daniel Tille, Robert Wille, Rolf Drechsler |
| Workshop: |
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21. Workshop der GI/ITG-Fachgruppe Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS 2007) |
Reference:
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| pp. 213-217, Hamburg, 2007
| Hyperlink:
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| [Link to the Workshop]
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» Building Free Binary Decision Diagrams Using SAT Solvers
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Author:
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Robert Wille, Görschwin Fey, Rolf Drechsler |
| Workshop: |
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8th Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM2007) |
Reference:
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| Oslo, 2007
| Hyperlink:
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| [Link to the Workshop]
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» Formal Verification on the Word Level using SAT-like Proof
Techniques
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Author:
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Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler |
| Workshop: |
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GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Reference:
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| pp. 165-173, Erlangen, 2007
| Hyperlink:
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| [Link to the Workshop]
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