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» Publications of Robert Wille



BOOKS

» Exact Design of Digital Microfluidic Biochips
[Read more about this book!]



Publisher:


Springer
Author:

Oliver Keszöcze, Robert Wille, Rolf Drechsler
Format:
Gebunden
Year:


2018




» Automatic Methods for the Refinement of System Models
[Read more about this book!]



Publisher:


Springer International Publishing
Author:

Julia Seiter, Robert Wille, Rolf Drechsler
Format:
Taschenbuch
Year:


2016




» Languages, Design Methods, and Tools for Electronic System Design
[Read more about this book!]



Publisher:


Springer International Publishing (Verlag)
Author:

Rolf Drechsler, Robert Wille (Hrsg.)
Format:
Buch | Hardcover
Year:


2016




» Synthese- und Optimierungsverfahren für zukünftige Computerparadigmen
[Read more about this book!]



Publisher:


Shaker Verlag
Author:

Robert Wille, Oliver Keszöcze, Rolf Drechsler (Hrsg.)
Format:
gebunden
Year:


2015




» Auf dem Weg zum Quantencomputer - Entwurf reversibler Logik
[Read more about this book!]



Publisher:


Shaker Verlag
Author:

Rolf Drechsler, Mathias Soeken, Robert Wille (Hrsg.)
Format:
gebunden
Year:


2012




» Towards a Design Flow for Reversible Logic
[Read more about this book!]



Publisher:


Springer
Author:

Robert Wille, Rolf Drechsler
Format:
Gebunden
Year:


2010





BOOK CONTRIBUTIONS
» An Efficient Nearest Neighbor Design for 2D Quantum Circuits
Design and Testing of Reversible Logic Author:

A. Bhattacharjee, C. Bandyopadhyay, B. Mondal, Robert Wille, Rolf Drechsler, H. Rahaman

Editor:Ashutosh Kumar SinghMasahiro FujitaAnand Mohan
Booktitle:Design and Testing of Reversible Logic
Publisher:Springer
Sites:Pages 215-231
Year:2020
Format:gebunden



» Exploiting Electronic Design Automation for Checking Legal Regulations: A Vision
Bigpicture: Languages, Design Methods, and Tools for Electronic System Design Author:

Oliver Keszöcze, Robert Wille

Editor:Frank Oppenheimer, Julio Luis Medina Pasaje
Booktitle:Languages, Design Methods, and Tools for Electronic System Design
Publisher:Springer
Sites:101—112
Year:2016
Format:gebunden



» Formal Specification Level
Bigpicture: Models, Methods, and Tools for Complex Chip Design: Selected Contributions from FDL 2012 Author:

Rolf Drechsler, Mathias Soeken, Robert Wille

Editor:Jan Haase
Booktitle:Models, Methods, and Tools for Complex Chip Design: Selected Contributions from FDL 2012
Publisher:Springer
Sites:37-52
Year:2014
Format:Hardcover



» SyReC: A Programming Language for Synthesis of Reversible Circuits
Bigpicture: System Specification and Design Languages: Selected Contributions from FDL 2010 Author:

Robert Wille, Sebastian Offermann, Rolf Drechsler

Editor:Tom J. Kazmierski, Adam Morawiec
Booktitle:System Specification and Design Languages: Selected Contributions from FDL 2010
Publisher:Springer
Sites:207-222
Year:2012
Format:Hardcover



» SMT-based Stimuli Generation in the SystemC Verification Library
Bigpicture: Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s: Selected Contributions on Specification, Design, and Verification from FDL 2009 Author:

Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler

Editor:Dominique Borrione
Booktitle:Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s: Selected Contributions on Specification, Design, and Verification from FDL 2009
Publisher:Springer
Sites:227-244
Year:2010
Format:Hardcover



» Ein Entwurfsablauf für Reversible Schaltkreise
Bigpicture: Ausgezeichnete Informatikdissertationen 2009 Author:

Robert Wille

Editor:S. Hölldobler et al.
Booktitle:Ausgezeichnete Informatikdissertationen 2009
Publisher:GI
Sites:291-300
Year:2010
Format:Paperback



» Synthesis of Boolean Functions in Reversible Logic
Bigpicture: Progress in Applications of Boolean Functions (Synthesis Lectures on Digital Circuits and Systems) Author:

Robert Wille, Rolf Drechsler

Editor:Tsutomu Sasao, Jon T. Butler, Mitchell Thornton
Booktitle:Progress in Applications of Boolean Functions (Synthesis Lectures on Digital Circuits and Systems)
Publisher:Morgan and Claypool Publishers
Sites:75-92
Year:2010
Format:Paperback



» Debugging Contradictory Constraints in Constraint-based Random Simulation
Bigpicture: Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL'08 Author:

Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler

Editor:Martin Radetzki
Booktitle:Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL'08
Publisher:Springer
Sites:273-290
Year:2009
Format:gebunden



» SWORD: A SAT like Prover Using Word Level Information
Bigpicture: VLSI-SoC: Advanced Topics on Systems on a Chip:
A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip Author:

Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler

Editor:Ricardo Reis, Vincent Mooney, Paul Hasler
Booktitle:VLSI-SoC: Advanced Topics on Systems on a Chip: A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip
Publisher:Springer
Sites:175-192
Year:2009
Format:Hardcover





JOURNALS

» Overcoming the Trade-off Between Accuracy and Compactness in Decision Diagrams for Quantum Computation
[Link to the Homepage of this journal]




Author:

Philipp Niemann, Alwin Zulehner, Rolf Drechsler, Robert Wille
Journal:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Details:
URL: https://doi.org/TCAD.2020.2977603, DOI: 10.1109/TCAD.2020.2977603
Year:


2020





» On the Impact of the Synchronization Constraint and Interconnections in Quantum-dot Cellular Automata
[Link to the Homepage of this journal]




Author:

Frank Sill Torres, Pedro A. Silva, Geraldo Fontes, Marcel Walter, José Augusto M. Nacif, Ricardo Santos Ferreira, Omar Paranaiba Vilela Neto, Jeferson F. Chaves, Robert Wille, Philipp Niemann, Daniel Große, Rolf Drechsler
Journal:
Microprocessors and Microsystems (MICPRO)
Details:
accepted
Year:


2020





» Reversible Circuits: IC/IP Piracy Attacksand Countermeasures
[Link to the Homepage of this journal]




Author:

Samah Mohamed Saeed, Alwin Zulehner, Robert Wille, Rolf Drechsler and Ramesh Karri
Journal:
IEEE Transactions On Very Large Scale Integration (VLSI) Systems
Details:
Seite 1-13
Year:


2019





» Near Zero-Energy Computation Using Quantum-dot Cellular Automata




Author:

Frank Sill Torres, Robert Wille, Philipp Niemann, Rolf Drechsler
Journal:
Journal on Emerging Technologies in Computing Systems (JETC)
Details:
Vol. 16, No. 1, https://dl.acm.org/doi/abs/10.1145/3365394, 2019
Year:


2019





» Placement & Routing for Tile-based Field-coupled Nanocomputing Circuits is NP-complete
[Link to the Homepage of this journal]




Author:

Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler
Journal:
Journal on Emerging Technologies in Computing Systems (JETC)
Details:
Volume 15, Issue 3, Number 29, April 2019. DOI: 10.1145/3312661
Year:


2019





» Determining Application-specific Knowledge for Improving Robustness of Sequential Circuits
[Link to the Homepage of this journal]




Author:

Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler
Journal:
IEEE Transactions On Very Large Scale Integration (VLSI) Systems
Details:
Volume 27, Number 4, Pages. 875-887, April 2019. DOI: 10.1109/TVLSI.2018.2890601
Year:


2019





» An Automated Approach for Generating and Checking Control Logic for Reversible Hardware Description Language-Based Designs
[Link to the Homepage of this journal]




Author:

Robert Wille, Oliver Keszöcze, Larts Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
Journal:
Journal of Low Power Electronics
Details:
Volume 13, Number 4, Pages 633-641
Year:


2017





» An Energy-aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata
[Link to the Homepage of this journal]




Author:

Frank Sill Torres, Robert Wille, Philipp Niemann, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
vol. 37, no. 12, pp. 3031-3041, December 2018.
DOI: 10.1109/TCAD.2018.2789782
Year:


2018





» Frame Conditions in the Automatic Validation and Verification of UML/OCL Models: A Symbolic Formulation of modifies only Statements
[Link to the Homepage of this journal]




Author:

Nils Przigoda, Philipp Niemann, Jonas Gomes Filho, Robert Wille, Rolf Drechsler
Journal:
Computer Languages, Systems & Structures
Details:
Volume 54, December 2018, Pages 512-527
DOI: 10.1016/j.cl.2017.11.002
Year:


2018





» Synthesis of optical circuits using binary decision diagrams
[Link to the Homepage of this journal]




Author:

Arighna Deb, Robert Wille, Oliver Keszöcze, Saeideh Shirinzadeh, Rolf Drechsler
Journal:
Integration, the VLSI Journal
Details:
Volume 59, September 2017, Pages 42–51
Year:


2017





» Towards a Verification Flow Across Abstraction Levels:
Verifying Implementations Against Their Formal Specification

[Link to the Homepage of this journal]




Author:

Pablo Gonzalez-de-Aledo, Nils Przigoda, Robert Wille, Rolf Drechsler, Pablo Sanchez
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
36(3):475-488, DOI: 10.1109/TCAD.2016.2611494
Year:


2017





» Verifying the Structure and Behavior in UML/OCL Models Using Satisfiability Solvers
[Link to the Homepage of this journal]




Author:

Nils Przigoda, Mathias Soeken, Robert Wille, Rolf Drechsler
Journal:
IET Cyber-Physical Systems: Theory & Applications
Details:
Volume 1, Issue 1, December 2016, pp. 49-59
DOI: 10.1049/iet-cps.2016.0022
Year:


2016





» Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits
[Link to the Homepage of this journal]




Author:

Arighna Deb, Robert Wille, Oliver Keszöcze, Stefan Hillmich, Rolf Drechsler
Journal:
Journal on Emerging Technologies in Computing Systems (JETC)
Details:
Volume 13, Issue 1
Year:


2016





» Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability
[Link to the Homepage of this journal]




Author:

Arighna Deb, Debesh K. Das, Hafizur Rahaman, Robert Wille, Rolf Drechsler, Bhargab B. Bhattacharya
Journal:
Journal on Emerging Technologies in Computing Systems (JETC)
Details:
Volume 12 Issue 4, Article No. 34
Year:


2016





» Analyzing Inconsistencies in UML/OCL Models
[Link to the Homepage of this journal]




Author:

Nils Przigoda, Robert Wille, Rolf Drechsler
Journal:
Journal of Circuits, Systems and Computers
Details:
Volume 25, Issue 03, March 2016
DOI: 10.1142/S0218126616400211
Year:


2016





» SyReC: A Hardware Description Language for the Specification and Synthesis of Reversible Circuits
[Link to the Homepage of this journal]




Author:

Robert Wille, Eleonora Schonborn, Mathias Soeken, Rolf Drechsler
Journal:
INTEGRATION, the VLSI Journal
Details:
53(3):39-53
Year:


2016





» Scalable One-Pass Synthesis for Digital Microfluidic Biochips
[Link to the Homepage of this journal]




Author:

Robert Wille, Oliver Keszöcze, Tobias Boehnisch, Alexander Kroker, Rolf Drechsler
Journal:
IEEE Design & Test of Computers
Details:
Volume 32, Issue 66, Pages 41—50
Year:


2015





» QMDDs: Efficient Quantum Function Representation and Manipulation
[Link to the Homepage of this journal]




Author:

Philipp Niemann, Robert Wille, D. Michael Miller, Mitchell A. Thornton, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 35, Number 1, pp. 86-99
DOI: 10.1109/TCAD.2015.2459034
Year:


2016





» Embedding of Large Boolean Functions for Reversible Logic
[Link to the Homepage of this journal]




Author:

Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler
Journal:
Journal on Emerging Technologies in Computing Systems (JETC)
Details:
Volume 12, Issue 4
Preprint available at arXiv 1408.3586
Year:


2015





» Exact Reordering of Circuit Lines for Nearest Neighbor Quantum Architectures
[Link to the Homepage of this journal]




Author:

Robert Wille, Aaron Lye, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 33, Number 12, pp. 1818-1831
DOI: 10.1109/TCAD.2014.2356463
Year:


2014





» Special Issue on Reversible Computation
[Link to the Homepage of this journal]




Author:

Robert Wille, Rolf Drechsler, Mehdi . B. Tahoori (editors)
Journal:
Journal on Emerging Technologies in Computing Systems (JETC)
Details:
Volume 11, Number 2
Year:


2014





» Considering Nearest Neighbor Constraints of Quantum Circuits at the Reversible Circuit Level




Author:

Robert Wille, Aaron Lye, Rolf Drechsler
Journal:
Quantum Information Processing
Details:
DOI: http://dx.doi.org/10.1007/s11128-013-0642-5
Year:


2013





» Trading Off Circuit Lines and Gate Costs in the Synthesis of Reversible Logic
[Link to the Homepage of this journal]




Author:

Robert Wille, Mathias Soeken, D. Michael Miller, Rolf Drechsler
Journal:
INTEGRATION, the VLSI Journal
Details:
Volume 47, Number 2, pp. 284-294, DOI: 10.1016/j.vlsi.2013.08.002
Year:


2014





» Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits
[Link to the Homepage of this journal]




Author:

Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler
Journal:
Multiple-Valued Logic and Soft Computing
Details:
Volume 21, Number 5-6, 2013, pp. 627-640
Year:


2013





» RevKit: An Open Source Toolkit for the Design of Reversible Circuits
[Link to the Homepage of this journal]




Author:

Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Journal:
Reversible Computation 2011 (Series: Lecture Notes in Computer Science)
Details:
Volume 7165, Third International Workshop, RC 2011, Revised Papers, pp. 64-76
Year:


2012





» Special Issue on Reversible Computation
[Link to the Homepage of this journal]




Author:

Rolf Drechsler, Irek Ulidowski, Robert Wille (editors)
Journal:
Multiple-Valued Logic and Soft Computing
Details:
Volume 18, Number 1
Year:


2012





» RevKit: A Toolkit for Reversible Circuit Design
[Link to the Homepage of this journal]




Author:

Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Journal:
Multiple-Valued Logic and Soft Computing
Details:
Volume 18, Number 1, pp. 55-65
Year:


2012





» Synthesis of Quantum Circuits for Linear Nearest Neighbor Architectures
[Link to the Homepage of this journal]




Author:

Mehdi Saeedi, Robert Wille, Rolf Drechsler
Journal:
Quantum Information Processing
Details:
Volume 10, Number 3, pp. 355-377
DOI: 10.1007/s11128-010-0201-2
Year:


2011





» Debugging Reversible Circuits
[Link to the Homepage of this journal]




Author:

Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
Journal:
INTEGRATION, the VLSI Journal
Details:
Volume 44, Number 1, pp. 51-61, January
DOI: 10.1016/j.vlsi.2010.08.002
Year:


2011





» BDD-Based Synthesis of Reversible Logic
[Link to the Homepage of this journal]




Author:

Robert Wille, Rolf Drechsler
Journal:
International Journal of Applied Metaheuristic Computing (IJAMC)
Details:
Volume 1, Number 4, pp. 25-41
Year:


2010





» Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic
[Link to the Homepage of this journal]




Author:

Robert Wille, Rolf Drechsler
Journal:
Electronic Notes in Theoretical Computer Science
Details:
Volume 253, Number 6, pp. 57-70
DOI: 10.1016/j.entcs.2010.02.006
Year:


2010





» Synthese reversibler Logik
[Link to the Homepage of this journal]




Author:

Robert Wille, Rolf Drechsler
Journal:
it-Information Technology
Details:
Volume 52, Number 1, pp. 30-38
PDF Download
Year:


2010





» Exact Synthesis of Elementary Quantum Gate Circuits
[Link to the Homepage of this journal]




Author:

Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Journal:
Multiple-Valued Logic and Soft Computing
Details:
Volume 15, Number 4, pp. 283-300
Year:


2009





» Exact Multiple Control Toffoli Network Synthesis with SAT Techniques
[Link to the Homepage of this journal]




Author:

Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 28, Number 5, pp. 703-715, May
DOI: 10.1109/TCAD.2009.2017215
Year:


2009





» Building Free Binary Decision Diagrams Using SAT Solvers
[Link to the Homepage of this journal]




Author:

Robert Wille, Görschwin Fey, Rolf Drechsler
Journal:
Facta Universitatis, Series: Electronics and Energetics
Details:
Volume 20, Number 3, pp. 381-394,
Year:


2007






CONFERENCES



» ToPoliNano and fiction: Design Tools for Field-coupled Nanocomputing




Author:

Umberto Garlando, Marcel Walter, Robert Wille, Fabrizio Riente, Frank Sill Torres, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Portorož, Slowenien, 2020
Hyperlink:

[To the Site of this Conference]



» Bail on Balancing: An Alternative Approach to the Physical Design of Field-coupled Nanocomputing Circuits




Author:

Marcel Walter, Robert Wille, Frank Sill Torres, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Limassol, Cyprus, 2020
Best Paper Candidate
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Verification for Field-coupled Nanocomputing Circuits




Author:

Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

San Francisco, USA, 2020
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Efficient Implementation of Nearest Neighbor Quantum Circuits Using Clustering with Genetic Algorithm




Author:

Anirban Bhattacharjee, Chandan Bandyopadhyay, Angshu Mukherjee, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Conference:
50th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Miyazaki, Japan, 2020
Hyperlink:

[To the Site of this Conference]



» Integer Overflow Detection in Hardware Designs at the Specification Level




Author:

Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
Conference:
8th International Conference on Model-Driven Engineering and Software Development (MODELSWARD)
Reference:

Valetta, Malta, 2020
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Towards Automatic Hardware Synthesis from Formal Specification to Implementation




Author:

Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Beijing, China, 2020
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-coupled Nanotechnologies




Author:

Robert Wille, Marcel Walter, Frank Sill Torres, Daniel Große, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Miami, Florida, USA, 2019
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Improved Look-ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum Circuits




Author:

Anirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler and Hafizur Rahaman
Conference:
International Conference on VLSI Design (VLSI Design)
Reference:

Florida, USA, 2019
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» One Additional Qubit is Enough: Encoded Embeddings for Boolean Components in Quantum Circuits




Author:

Alwin Zulehner, Philipp Niemann, Rolf Drechsler, Robert Wille
Conference:
49th IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Fredericton, NB, Canada, 2019
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Accuracy and Compactness in Decision Diagrams for Quantum Computation




Author:

Alwin Zulehner, Philipp Niemann, Rolf Drechsler, Robert Wille
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Florence, Italy, 2019
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Better Late Than Never: Verification of Embedded Systems After Deployment




Author:

Martin Ring, Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Florence, Italy, 2019
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Scalable Design for Field-coupled Nanocomputing Circuits




Author:

Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
Conference:
24th Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Tokyo, Japan, 2019
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» IC/IP Piracy Assessment of Reversible Logic




Author:

Samah Mohamed Saeed, Xiaotong Cui, Alwin Zulehner,, Robert Wille, Rolf Drechsler, Kaijie Wu, Ramesh Karri
Conference:
International Conference on Computer-Aided Design (ICCAD)
Reference:

San Diego, 2018
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Automatic Design of Microfluidic Devices: An Overview of Platforms and Corresponding Design Tasks




Author:

Robert Wille, Bing Li, Rolf Drechsler and Ulf Schlichtmann
Conference:
In Forum on specification & Design Languages (FDL), München, 2018
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata




Author:

Frank Sill Torres, Robert Wille, Marcel Walter, Philipp Niemann, Daniel Große, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

pp. 649-656, Prague, Czech Republic, 2018
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Synchronization of Clocked Field-Coupled Circuits




Author:

Frank Sill Torres, Marcel Walter, Robert Wille, Daniel Große, Rolf Drechsler
Conference:
IEEE International Conference on Nanotechnology (Nano)
Reference:

Cork, Ireland, 2018
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» A Novel Approach for Nearest Neighbor Realization of 2D Quantum Circuits




Author:

Anirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Hong Kong SAR, China, 2018
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Synthesis of Reversible Circuits Using Conventional Hardware Description Languages




Author:

Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Conference:
IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Linz, Austria, 2018
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Improved Synthesis of Clifford+T Quantum Functionality




Author:

Philipp Niemann, Robert Wille, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 597-600, Dresden, Germany, 2018
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» An Exact Method for Design Exploration of Quantum-dot Cellular Automata




Author:

Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 503-508, Dresden, Germany, 2018
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Analyzing Frame Conditions in UML/OCL Models: Consistency, Equivalence, and Independence




Author:

Philipp Niemann, Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
6th International Conference on Model-Driven Engineering and Software Development (MODELSWARD)
Reference:

pp. 139-151, Funchal, Portugal, 2018
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips




Author:

Oliver Keszöcze, Mohamed Ibrahim, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
Conference:
International Conference on VLSI Design (VLSID)
Reference:

Pune, Indien, 2018
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Towards Lightweight Satisfiability Solvers for Self-Verification




Author:

Fritjof Bornebusch, Robert Wille, Rolf Drechsler
Conference:
7th International Symposium on Embedded Computing and System Design (ISED)
Reference:

Durgapur, Indien, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» More than true or false: Native Support of Irregular Values in the Automatic Validation & Verification of UML/OCL Models




Author:

Nils Przigoda, Philipp Niemann, Judith Peters, Frank Hilken, Robert Wille, Rolf Drechsler
Conference:
15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Reference:

pp. 77-86, Vienna, Austria, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Dedicated Synthesis for MZI-based Optical Circuits based on AND-Inverter Graphs




Author:

Arighna Deb, Robert Wille, Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

Irvine, USA, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» BioViz: An Interactive Visualization Engine for Digital Microfluidic Biochips




Author:

Jannis Stoppe, Oliver Keszöcze, Maximilian Luenert, Robert Wille, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Bochum, Germany, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Towards VHDL-based Design of Reversible Circuits




Author:

Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Kolkata, India, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Efficient Construction of QMDDs for Irreversible, Reversible and Quantum Functions




Author:

Philipp Niemann, Alwin Zulehner, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 214-231, Kolkata, India, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» OR-Inverter Graphs for the Synthesis of Optical Circuits




Author:

Arighna Deb, Robert Wille, Rolf Drechsler
Conference:
47th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Novi Sad, Serbia, 2017
Hyperlink:

[To the Site of this Conference]



» Extensions to the Reversible Hardware Description Language SyReC




Author:

Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Conference:
47th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Novi Sad, Serbia, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Enhancing Robustness of Sequential Circuits Using Application-specific Knowledge and Formal Methods




Author:

Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler
Conference:
22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Chiba/Tokyo, Japan, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exact Routing for Micro-Electrode-Dot-Array Digital Microfluidic Biochips




Author:

Oliver Keszöcze, Zipeng Li, Andreas Grimmer, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
Conference:
22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Chiba/Tokyo, Japan, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Clocks vs. Instants Relations: Verifying CCSL Time Constraints in UML/MARTE Models




Author:

Judith Peters, Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Reference:

Indian Institute of Technology, Kanpur, India, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Frame Conditions in Symbolic Representations of UML/OCL Models




Author:

Nils Przigoda, Jonas Gomes Filho, Philipp Niemann, Robert Wille, Rolf Drechsler
Conference:
14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Reference:

pp. 65-70, Indian Institute of Technology, Kanpur, India, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Generating and Checking Control Logic in the HDL-based Design of Reversible Circuits




Author:

Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
Conference:
International Symposium on Electronic System Design (ISED)
Reference:

Patna, Indien, 2016
Hyperlink:

[To the Site of this Conference]



» An Improved Gate Library for Logic Synthesis of Optical Circuits




Author:

Shuchisman Burman, Kamalika Datta, Robert Wille, Indranil Sengupta, Rolf Drechsler
Conference:
International Symposium on Electronic System Design (ISED)
Reference:

Patna, Indien, 2016
Hyperlink:

[To the Site of this Conference]



» Towards a Model-Based Verification Methodology for Complex Swarm Systems




Author:

Jonas Gomes Filho, Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
International Symposium on Electronic System Design (ISED)
Reference:

Patna, Indien, 2016
Hyperlink:

[To the Site of this Conference]



» Ground Setting Properties for an Efficient Translation of OCL in SMT-based Model Finding




Author:

Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
ACM/IEEE 19th International Conference on Model Driven Engineering Languages and Systems (MoDELS)
Reference:

Saint Malo, Brittany, France, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs




Author:

Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Bologna, Italy, 2016
Hyperlink:

[To the Site of this Conference]



» Towards a Catalog of Structural and Behavioral Verification Tasks for UML/OCL Models




Author:

Frank Hilken, Philipp Niemann, Martin Gogolla, Robert Wille
Conference:
Modellierung
Reference:

pp. 117-124, Karlsruhe, Germany, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Fault Detection in Parity Preserving Reversible Circuits




Author:

Nils Przigoda, Gerhard Dueck, Robert Wille, Rolf Drechsler
Conference:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Sapporo, Japan, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Re-writing HDL Descriptions for Line-aware Synthesis of Reversible Circuits




Author:

Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Conference:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Sapporo, Japan, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation




Author:

Laxmidhar Biswal, Chandan Bandyopadhyay, Anupam Chattopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Conference:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Sapporo, Japan, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Logic Synthesis for Quantum State Generation




Author:

Philipp Niemann, Rhitam Datta, Robert Wille
Conference:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 247-252, Sapporo, Japan, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits




Author:

Md. Mazder Rahman, Gerhard W. Dueck, Anupam Chattopadhyay, Robert Wille
Conference:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Sapporo, Japan, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Synthesis of Approximate Coders for On-chip Interconnects Using Reversible Logic




Author:

Robert Wille, Oliver Keszöcze, Stefan Hillmich, Marcel Walter, Alberto Garcia-Ortiz
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Dresden, Germany, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exploiting Inherent Characteristics of Reversible Circuits for Faster Combinational Equivalence Checking




Author:

Luca Amaru, Pierre-Emmanuel Gaillardon, Robert Wille, Giovanni De Micheli
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Dresden, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Look-ahead Schemes for Nearest Neighbor Optimization of 1D and 2D Quantum Circuits




Author:

Robert Wille, Oliver Keszöcze, Marcel Walter, Patrick Rohrs, Anupam Chattopadhyay, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Macao, China, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library




Author:

Laxmidhar Biswal, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Conference:
International Conference on VLSI Design (VLSI Design)
Reference:

Kolkata, India, 2016
Hyperlink:

[To the Site of this Conference]



» Reversible Computation: An Alternative Computation Paradigm for Low Power Applications




Author:

Rolf Drechsler, Robert Wille
Conference:
International Green and Sustainable Computing Conference (IGSC)
Reference:

Las Vegas, USA, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Checking Concurrent Behavior in UML/OCL Models




Author:

Nils Przigoda, Christoph Hilken, Robert Wille, Jan Peleska, Rolf Drechsler
Conference:
ACM/IEEE 18th International Conference on Model Driven Engineering Languages and Systems (MoDELS)
Reference:

Ottawa, Kanada, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Extracting Frame Conditions from Operation Contracts




Author:

Philipp Niemann, Frank Hilken, Martin Gogolla, Robert Wille
Conference:
ACM/IEEE 18th International Conference on Model Driven Engineering Languages and Systems (MoDELS)
Reference:

pp. 266-275, Ottawa, Canada, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» A General and Exact Routing Methodology for Digital Microfluidic Biochips




Author:

Oliver Keszöcze, Robert Wille, Krishnendu Chakrabarty Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

Austin, USA, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Formal Methods for Emerging Technologies




Author:

Robert Wille, Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

Austin, USA, 2015
Hyperlink:

[To the Site of this Conference]



» Leveraging the Analysis for Invariant Independence in Formal System Models




Author:

Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Funchal, Madeira, Portugal, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Verification-driven Design Across Abstraction Levels - A Case Study




Author:

Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Funchal, Madeira, Portugal, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Envisioning Self-Verification of Electronic Systems




Author:

Rolf Drechsler, Martin Fränzle, Robert Wille
Conference:
Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
Reference:

Bremen, Germany, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Towards Line-aware Realizations of Expressions for HDL-based Synthesis of Reversible Circuits




Author:

Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Grenoble, France, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Synthesis of Quantum Circuits for Dedicated Physical Machine Descriptions




Author:

Philipp Niemann, Saikat Basu, Amlan Chakrabarti, Niraj K. Jha, Robert Wille
Conference:
Reversible Computation
Reference:

pp. 248-264, Grenoble, France, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Towards a Cost Metric for Nearest Neighbor Constraints in Reversible Circuits




Author:

Abhoy Kole, Kamalika Datta, Indranil Sengupta, Robert Wille
Conference:
Reversible Computation
Reference:

Grenoble, France, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» From UML/OCL to Base Models: Transformation Concepts for Generic Validation and Verification




Author:

Frank Hilken, Philipp Niemann, Martin Gogolla, Robert Wille
Conference:
International Conference on Model Transformation (ICMT)
Reference:

pp. 149-165, L’Aquila, Italy, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Contradiction Analysis for Inconsistent Formal Models




Author:

Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15)
Reference:

Belgrade, Serbia, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» A Generic Representation of CCSL Time Constraints for UML/MARTE Models




Author:

Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

San Francisco, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization




Author:

Arighna Deb, Robert Wille, Rolf Drechsler, Debesh Das
Conference:
45th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Waterloo, Canada, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» An Examination of the NCV-v1 Quantum Library Based on Minimal Circuits




Author:

Arman Allahyari-Abhari, Robert Wille, Rolf Drechsler
Conference:
45th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Waterloo, Canada, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Automated Feature Localization for Dynamically Generated SystemC Designs




Author:

Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE'15)
Reference:

Grenoble, France, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Assisted Generation of Frame Conditions for Formal Models




Author:

Philipp Niemann, Frank Hilken, Martin Gogolla, Robert Wille
Conference:
Design, Automation and Test in Europe (DATE'15)
Reference:

pp. 309-312, Grenoble, France, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» A Unified Formulation of Behavioral Semantics for SysML Models




Author:

Christoph Hilken, Jan Peleska, Robert Wille
Conference:
International Conference on Model-Driven Engineering and Software Development
Reference:

Angers, France, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» BDD-based Synthesis for All-optical Mach-Zehnder Interferometer Circuits




Author:

Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Conference:
International Conference on VLSI Design (VLSI Design)
Reference:

Bengaluru, India, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Determining the Minimal Number of SWAP Gates for Multi-dimensional Nearest Neighbor Quantum Circuits




Author:

Aaron Lye, Robert Wille, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Chiba/Tokyo, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Reverse BDD-based Synthesis for Splitter-free Optical Circuits




Author:

Robert Wille, Oliver Keszöcze, Clemens Hopfmuller, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Chiba/Tokyo, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exact Routing for Digital Microfluidic Biochips with Temporary Blockages




Author:

Oliver Keszöcze, Robert Wille, Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

San Jose, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Automated and Quality-driven Requirements Engineering




Author:

Rolf Drechsler, Mathias Soeken, Robert Wille,
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

San Jose, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Automatic Refinement Checking for Formal System Models




Author:

Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Munich, Germany, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Verifying Consistency between Activity Diagrams and Their Corresponding OCL Contracts




Author:

Christoph Hilken, Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Munich, Germany, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» (Semi-)Automatic Translation of Legal Regulations to Formal Representations: Expanding the Horizon of EDA Applications




Author:

Oliver Keszöcze, Betina Keiner, Matthias Richter, Gottfried Antpöhler, Robert Wille
Conference:
Special Session at the Forum on specification & Design Languages (FDL'14)
Reference:

Munich, Germany, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Improving Coverage of Simulation-based Verification by Dedicated Stimuli Generation




Author:

Shuo Yang, Robert Wille, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

pp. 599-606, Verona, Italy, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Determining Cases of Scenarios to Improve Coverage in Simulation-based Verication




Author:

Shuo Yang, Robert Wille, Rolf Drechsler
Conference:
Symposium on Integrated Circuits and System Design (SBCCI)
Reference:

Aracaju, Brazil, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Validating SystemC Implementations Against Their Formal Specifications




Author:

Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference:
Symposium on Integrated Circuits and System Design (SBCCI)
Reference:

Aracaju, Brazil, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Filmstripping and Unrolling: A Comparison of Verification Approaches for UML and OCL Behavioral Models




Author:

Frank Hilken, Philipp Niemann, Martin Gogolla, Robert Wille
Conference:
8th International Conference on Tests & Proofs (TAP)
Reference:

pp. 99-116, York, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Generating SystemC Implementations for Clock Constraints specified in UML/MARTE CCSL




Author:

Judith Peters, Robert Wille, Rolf Drechsler
Conference:
International Conference on Engineering of Complex Computer Systems (ICECCS)
Reference:

pp. 116-125, Tianjin, China, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exact One-pass Synthesis of Digital Microfluidic Biochips




Author:

Oliver Keszöcze, Robert Wille, Tsung-Yi Ho, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

San Francisco, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Equivalence Checking in Multi-level Quantum Systems




Author:

Philipp Niemann, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 201-215, Kyoto, Japan, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» RevVis: Visualization of Structures and Properties in Reversible Circuits




Author:

Robert Wille, Jannis Stoppe, Eleonora Schönborn, Kamalika Datta, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Kyoto, Japan, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Optimizing DD-based Synthesis of Reversible Circuits using Negative Control Lines




Author:

Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Conference:
IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 129-134, Warschau, Polen, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Optimal SWAP Gate Insertion for Nearest Neighbor Quantum Circuits




Author:

Robert Wille, Aaron Lye, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 489-494, Singapore, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Efficient Synthesis of Quantum Circuits Implementing Clifford Group Operations




Author:

Philipp Niemann, Robert Wille, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 483-488, Singapore, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Improved SAT-based ATPG: More Constraints, Better Compaction




Author:

Stephan Eggersglüß, Robert Wille, Rolf Drechsler
Conference:
IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
Reference:

pp. 85-90, San Jose, USA, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» A Compact and Efficient SAT Encoding for Quantum Circuits




Author:

Robert Wille, Nils Przigoda, Rolf Drechsler
Conference:
IEEE Africon
Reference:

Mauritius, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exploiting Reversibility in the Complete Simulation of Reversible Circuits




Author:

Robert Wille, Simon Stelter, Rolf Drechsler
Conference:
IEEE Africon
Reference:

Mauritius, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Cone of Influence Analysis at the Electronic System Level Using Machine Learning




Author:

Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Santander, Spain, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Minimal Stimuli Generation in Simulation-based Verification




Author:

Shuo Yang, Robert Wille, Daniel Große and Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Santander, Spain, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» The SyReC Hardware Description Language: Enabling Scalable Synthesis of Reversible Circuits




Author:

Robert Wille, Rolf Drechsler
Conference:
International Midwest Symposium on Circuits and Systems (MWSCAS)
Reference:

Columbus, USA, 2013
Hyperlink:

[To the Site of this Conference]



» Data Extraction from SystemC Designs using Debug Symbols and the SystemC API




Author:

Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Natal, Brazil, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» On the “Q” in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-structure




Author:

Philipp Niemann, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 125-140, Victoria, Canada, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exploiting Negative Control Lines in the Optimization of Reversible Circuits




Author:

Kamalika Datta, Gaurav Rathi, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 209-220, Victoria, Canada, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure




Author:

Arighna Deb, Debesh Kumar Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 182-195, Victoria, Canada, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Reducing the Depth of Quantum Circuits Using Additional Lines




Author:

Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 221-233, Victoria, Canada, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits




Author:

Robert Wille, Hongyan Zhang, Rolf Drechsler
Conference:
43rd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 29-34, Toyama, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exact Template Matching Using Boolean Satisfiability




Author:

Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler
Conference:
43rd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 328-333, Toyama, Japan, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Determining Relevant Model Elements for the Verification of UML/OCL Specifications




Author:

Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1189-1192, Grenoble, France, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Towards a Generic Verification Methodology for System Models




Author:

Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1193-1196, Grenoble, France, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Improving the Mapping of Reversible Circuits to Quantum Circuits Using Multiple Target Lines




Author:

Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 145-150. Yokohama, Japan, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Towards Dialog Systems for Assisted Natural Language Processing in the Design of Embedded Systems




Author:

Rolf Drechsler, Mathias Soeken, Robert Wille
Conference:
IEEE Design and Test Symposium 2012 (IDT)
Reference:

Doha, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Synthesis of Reversible Circuits Using Decision Diagrams




Author:

Rolf Drechsler, Robert Wille
Conference:
International Symposium on Electronic System Design (ISED)
Reference:

pp. 1-5, Kolkata, WB, India, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Completeness-Driven Development




Author:

Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille
Conference:
International Conference on Graph Transformation
Reference:

pp. 38-50, Bremen, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Formal Specification Level: Towards Verification-driven Design Based on Natural Language Processing




Author:

Rolf Drechsler, Mathias Soeken, Robert Wille
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 53-58, Vienna, Austria, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Circuit Line Minimization in the HDL-based Synthesis of Reversible Logic




Author:

Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

pp. 213-218, Amherst, USA, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Coverage-driven Stimuli Generation




Author:

Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler
Conference:
15th Euromicro Conference on Digital System Design (DSD)
Reference:

Izmir, Turkey, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology




Author:

Rolf Drechsler, Robert Wille
Conference:
International Symposium on VLSI Design and Test (VDAT)
Reference:

Shibpur, India, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Assisted Behavior Driven Development Using Natural Language Processing




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference:
50th International Conference on Objects, Models, Components, Patterns (TOOLS)
Reference:

pp. 269-287, Prague, Czech Republic, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Realizing Reversible Circuits Using a New Class of Quantum Gates




Author:

Zahra Sasanian, Robert Wille, Michael Miller
Conference:
Design Automation Conference (DAC)
Reference:

San Francisco, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits




Author:

Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler
Conference:
42nd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 173-178, Victoria, Canada, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» A Synthesis Flow for Sequential Reversible Circuits




Author:

Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler
Conference:
42nd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 299-304, Victoria, Canada, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines




Author:

Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler
Conference:
42nd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 69-74, Victoria, Canada, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis




Author:

Robert Wille, Rolf Drechsler, Christof Oswald, Alberto Garcia-Ortiz
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Dresden, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Eliminating Invariants in UML/OCL Models




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1142-1145, Dresden, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Debugging of Inconsistent UML/OCL Models




Author:

Robert Wille, Mathias Soeken, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1078-1083, Dresden, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Synthesis of Reversible Circuits with Minimal Lines for Large Functions




Author:

Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 85-92, Sydney, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Improved Fault Diagnosis for Reversible Circuits




Author:

Hongyan Zhang, Robert Wille, Rolf Drechsler
Conference:
Asian Test Symposium (ATS)
Reference:

New Delhi, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Efficient Realization of Control Logic in Reversible Circuits




Author:

Sebastian Offermann, Robert Wille, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Oldenburg, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Determining Minimal Testsets for Reversible Circuits Using Boolean Satisfiability




Author:

Hongyan Zhang, Stefan Frehse, Robert Wille, Rolf Drechsler
Conference:
10th IEEE Africon
Reference:

Livingstone, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» VisSAT: Visualization of SAT Solver Internals for Computer Aided Hardware Verification




Author:

Robert Wille, André Sülflow, Rolf Drechsler
Conference:
International Conference on Modeling, Simulation and Visualization Methods (MSV)
Reference:

pp. 36-39, Las Vegas, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization




Author:

Robert Wille, Hongyan Zhang, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

pp. 120-125, Chennai, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» An Introduction to Reversible Circuit Design




Author:

Robert Wille
Conference:
Saudi International Electronics, Communications and Photonics Conference (SIECPC)
Reference:

Riyadh, 2011
Hyperlink:

[To the Site of this Conference]



» Encoding OCL Data Types for SAT-based Verification of UML/OCL Models




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference:
5th International Conference on Tests & Proofs (TAP)
Reference:

pp. 152-170, Zurich, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Designing a RISC CPU in Reversible Logic




Author:

Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
Conference:
41st International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 170-175, Tuusula, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits




Author:

Rolf Drechsler, Robert Wille
Conference:
41st International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 78-85, Tuusula, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Elementary Quantum Gate Realizations for Multiple-Control Toffoli Gates




Author:

D. Michael Miller, Robert Wille, Z. Sasanian
Conference:
41st International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 288-293, Tuusula, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Verifying Dynamic Aspects of UML Models




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1077-1082, Grenoble, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Determining the Minimal Number of Lines for Large Reversible Circuits




Author:

Robert Wille, Oliver Keszöcze, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1204—1207, Grenoble, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» SyReC: A Programming Language for Synthesis of Reversible Circuits




Author:

Robert Wille, Sebastian Offermann, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 184-189, Southampton, 2010
Received Best Paper Award
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Reducing the Number of Lines in Reversible Circuits




Author:

Robert Wille, Mathias Soeken, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

pp. 647-652, Anaheim, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Graph Transformation Units Guided by a SAT Solver




Author:

Hans-Jörg Kreowski, Susanne Kuske, Robert Wille
Conference:
International Conference on Graph Transformations (ICGT)
Reference:

pp. 27-42, Enschede, 2010
Hyperlink:

[To the Site of this Conference]



» Synthesizing Multiplier in Reversible Logic




Author:

Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Conference:
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 335-340, Vienna, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Window Optimization of Reversible and Quantum Circuits




Author:

Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Conference:
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 431-435, Vienna, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Enhancing Debugging of Multiple Missing Control Errors in Reversible Logic




Author:

Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 465-470, Rhode Island, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Efficient Simulation-based Debugging of Reversible Logic




Author:

Stefan Frehse, Robert Wille, Rolf Drechsler
Conference:
40th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 156-161, Barcelona, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Reducing Reversible Circuit Cost by Adding Lines




Author:

D. Michael Miller, Robert Wille, Rolf Drechsler
Conference:
40th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 217-222, Barcelona, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Verifying UML/OCL Models Using Boolean Satisfiability




Author:

Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1341-1344, Dresden, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» SMT-based Stimuli Generation in the SystemC Verification Library




Author:

Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 1-6, Sophia Antipolis, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Synthesizing Reversible Circuits for Irreversible Functions




Author:

D. Michael Miller, Robert Wille, Gerhard W. Dueck
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

pp. 749-756, Patras, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» BDD-based Synthesis of Reversible Logic for Large Functions




Author:

Robert Wille, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

pp. 270-275, San Francisco, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Contradictory Antecedent Debugging in Bounded Model Checking




Author:

Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 173-176, Boston, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Evaluation of Cardinality Constraints on SMT-based Debugging




Author:

Andre Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler
Conference:
39th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 298-303, Naha, Okinawa, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Equivalence Checking of Reversible Circuits




Author:

Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
Conference:
39th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 324-330, Naha, Okinawa, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Debugging of Toffoli Networks




Author:

Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1284-1289, Nice, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Reversible Logic Synthesis with Output Permutation




Author:

Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler
Conference:
22nd International Conference on VLSI Design
Reference:

pp. 189-194, New Delhi, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking




Author:

Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

pp. 542-549, Parma, 2008
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Contradiction Analysis for Constraint-based Random Simulation




Author:

Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 130-135, Stuttgart, 2008
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability




Author:

Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

pp. 411-416, Montpellier, 2008
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» RevLib: An Online Resource for Reversible Functions and Reversible Circuits




Author:

Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler
Conference:
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Reference:

pp. 220-225, Dallas, 2008
RevLib is available at www.revlib.org
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don’t Cares




Author:

Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Conference:
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Reference:

pp. 214-219, Dallas, 2008
Received IEEE Young Researcher Award
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Quantified Synthesis of Reversible Logic




Author:

Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große
Conference:
Design, Automation, and Test in Europe (DATE)
Reference:

pp. 1015-1020, Munich, 2008
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Fast Exact Toffoli Network Synthesis of Reversible Logic




Author:

Robert Wille, Daniel Große
Conference:
IEEE International Conference on Computer Aided Design (ICCAD)
Reference:

pp. 60-64, San Jose, 2007
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» SWORD: A SAT like Prover Using Word Level Information




Author:

Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
Conference:
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC)
Reference:

pp. 88-93, Atlanta, 2007
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]


WORKSHOPS




» SAT-based Exact Physical Design for Field-coupled Nanocomputing Technologies




Author:

Marcel Walter, Winston Haaswijk, Robert Wille, Frank Sill Torres, Rolf Drechsler
Workshop:
International Workshop on Logic & Synthesis (IWLS)
Reference:

San Francisco, USA, 2020
Hyperlink:

[Link to the Workshop]



» fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits




Author:

Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
Workshop:
International Workshop on Logic & Synthesis (IWLS)
Reference:

Lausanne, Switzerland, 2019
Hyperlink:

[Link to the Workshop]



» Optimizing Ts in the Synthesis of Clifford+T Quantum Circuits




Author:

Philipp Niemann, Robert Wille, Rolf Drechsler
Workshop:
2nd International Workshop on Quantum Compilation (IWQC, co-located with ICCAD)
Reference:

San Diego, CA, USA, 2018
Hyperlink:

[Link to the Workshop]



» Integrating an SMT-based Model Finder into USE




Author:

Nils Przigoda, Frank Hilken, Judith Peters, Robert Wille, Martin Gogolla, Rolf Drechsler
Workshop:
Workshop on Model-Driven Engineering, Verification, and Validation (MoDeVVa)
Reference:

Saint-Malo, France, 2016
Hyperlink:

[Link to the Workshop]



» Synthesis of Optical Circuits with Contradictory Optimization Objectives




Author:

Arighna Deb, Robert Wille, Oliver Keszöcze, Stefan Hillmich, Rolf Drechsler
Workshop:
The 2nd International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS Workshop)
Reference:

Dresden, Germany, 2016
Hyperlink:

[Link to the Workshop]



» Visualizing Microfluidic Biochips Interactively




Author:

Jannis Stoppe, Oliver Keszöcze, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Design Automation for Understanding Hardware Designs (DUHDE)
Reference:

Dresden, Germany, 2016
Hyperlink:

[Link to the Workshop]



» Extraktion von Frame Conditions aus Operation Contracts




Author:

Philipp Niemann, Frank Hilken, Martin Gogolla, Robert Wille
Workshop:
Software Engineering (SE)
Reference:

Vienna, Austria, 2016
Hyperlink:

[Link to the Workshop]



» Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses




Author:

Nils Przigoda, Judith Peters, Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Model-Driven Engineering, Verification, and Validation (MoDeVVa)
Reference:

Ottawa, Canada, 2015
Hyperlink:

[Link to the Workshop]



» Quo Vadis, Reversible Circuit Design? Towards Scaling Design and Synthesis of Reversible Circuits




Author:

Eleonora Schönborn, Robert Wille, Rolf Drechsler
Workshop:
Reed-Muller Workshop
Reference:

Waterloo, Canada, 2015
Hyperlink:

[Link to the Workshop]



» Verbesserung der Fehlersuche in inkonsistenten formalen Modellen




Author:

Nils Przigoda, Robert Wille, Rolf Drechsler
Workshop:
18. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'15)
Reference:

Chemnitz, Germany, 2015
Hyperlink:

[Link to the Workshop]



» Towards a Base Model for UML and OCL Verification




Author:

Frank Hilken, Philipp Niemann, Robert Wille, Martin Gogolla
Workshop:
Model-Driven Engineering, Verification, and Validation (MoDeVVa)
Reference:

Valencia, Spain, 2014
Hyperlink:

[Link to the Workshop]



» Towards a Multi-dimensional and Dynamic Visualization for ESL Designs




Author:

Jannis Stoppe, Marc Michael, Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
DATE Friday Workshop: Design Automation for Understanding Hardware Designs
Reference:

Dresden, Germany, 2014
Hyperlink:

[Link to the Workshop]



» Law-based Verification for Complex Swarm Systems




Author:

Rolf Drechsler, Hoang M. Le, Mathias Soeken, Robert Wille
Workshop:
International Workshop on the Swarm at the Edge of the Cloud
Reference:

Montreal, Canada
Hyperlink:

[Link to the Workshop]



» Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen




Author:

Mathias Soeken, Robert Wille, Eugen Kuksa, Rolf Drechsler
Workshop:
16. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference:

Rostock, 2013
Hyperlink:

[Link to the Workshop]



» Verification of Embedded Systems Using Modeling and Implementation Languages




Author:

Mathias Soeken, Heinz Riener, Robert Wille, Görschwin Fey, Rolf Drechsler
Workshop:
International Workshop on Metamodelling and Code Generation for Embedded Systems (MeCoEs'12)
Reference:

pp. 67-72, Tampere, Finland, 2012
PDF:

[view Pdf]
Hyperlink:

[Link to the Workshop]



» Towards Increasing Test Compaction Abilities of SAT-based ATPG through Fault Detection Constraints




Author:

Stephan Eggersglüß, Melanie Diepenbeck, Robert Wille, Rolf Drechsler
Workshop:
IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12)
Reference:

Niigata, Japan, 2012
PDF:

[view Pdf]
Hyperlink:

[Link to the Workshop]



» Towards Embedding of Large Functions for Reversible Logic




Author:

Mathias Soeken, Robert Wille, Laura Tague, D. Michael Miller, Rolf Drechsler
Workshop:
International Workshop on Boolean Problems
Reference:

Freiberg, 2012
Hyperlink:

[Link to the Workshop]



» Using πDDs in the Design for Reversible Circuits




Author:

Mathias Soeken, Robert Wille, Shin-Ichi Minato, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Reference:

Kopenhagen, 2012
Hyperlink:

[Link to the Workshop]



» Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams




Author:

Julia Seiter, Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Reference:

Kopenhagen, 2012
Hyperlink:

[Link to the Workshop]



» Towards Automatic Determination of Problem Bounds for Object Instantiation in Static Model Verification




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
Model-Driven Engineering, Verification, And Validation (MoDeVVa)
Reference:

Wellington, 2011
Hyperlink:

[Link to the Workshop]



» Synthesis of Reversible Circuits with Minimal Lines for Large Functions




Author:

Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Reference:

pp. 59-70, Gent, 2011
Hyperlink:

[Link to the Workshop]



» Customized Design Flows for Reversible Circuits Using RevKit




Author:

Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Reference:

pp. 91-96, Gent, 2011
Hyperlink:

[Link to the Workshop]



» Improving ESOP-based Synthesis of Reversible Logic Using Evolutionary Algorithms




Author:

Rolf Drechsler, Alexander Finder, Robert Wille
Workshop:
6th European Workshop on Hardware Optimization Techniques (EvoHOT)
Reference:

Applications of Evolutionary Computation, LNCS 6625, pp. 151-161, Turin, 2011
PDF:

[view Pdf]
Hyperlink:

[Link to the Workshop]



» Designing a RISC CPU in Reversible Logic




Author:

Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
Workshop:
14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference:

pp. 249-258, Oldenburg, 2011
Hyperlink:

[Link to the Workshop]



» SAT-based ATPG for Reversible Circuits




Author:

Hongyan Zhang, Robert Wille, Rolf Drechsler
Workshop:
5th International Design & Test Workshop (IDT)
Reference:

pp. 149-154, Abu Dhabi, 2010
Hyperlink:

[Link to the Workshop]



» Hierarchical Synthesis of Reversible Circuits Using Positive and Negative Davio Decomposition




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
5th International Design & Test Workshop (IDT)
Reference:

pp. 143-148, Abu Dhabi, 2010
PDF:

[view Pdf]
Hyperlink:

[Link to the Workshop]



» RevKit: A Toolkit for Reversible Circuit Design




Author:

Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Reference:

pp. 69-72, Bremen, 2010
PDF:

[view Pdf]
Hyperlink:

[Link to the Workshop]



» Hierarchical Synthesis of Reversible Circuits Using Positive and Negative Davio Decomposition




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Reference:

pp. 55-58, Bremen, 2010
Hyperlink:

[Link to the Workshop]



» SyReC: A Programming Language for Synthesis of Reversible Circuits




Author:

Robert Wille, Sebastian Offermann, Rolf Drechsler
Workshop:
International Workshop on Logic Synthesis (IWLS)
Reference:

Irvine, 2010
Hyperlink:

[Link to the Workshop]



» VisSAT: Visualization of SAT Solver Internals




Author:

Robert Wille, Andre Sülflow, Christian Genz, Rolf Drechsler
Workshop:
University Booth at Design, Automation and Test in Europe (DATE10)
Reference:

Dresden, 2010
PDF:

[view Pdf]
Hyperlink:

[Link to the Workshop]



» SyReC: A Programming Language for Synthesis of Reversible Circuits




Author:

Robert Wille, Sebastian Offermann, Rolf Drechsler
Workshop:
13. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference:

Dresden, 2010
Hyperlink:

[Link to the Workshop]



» Verifying UML/OCL Models Using Boolean Satisfiability




Author:

Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler
Workshop:
13. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference:

pp 57-66, Dresden, 2010
Hyperlink:

[Link to the Workshop]



» Reducing Reversible Circuit Cost by Adding Lines




Author:

D. Michael Miller, Robert Wille, Rolf Drechsler
Workshop:
International Workshop on Logic Synthesis (IWLS)
Reference:

Berkeley, 2009
Hyperlink:

[Link to the Workshop]



» Synthesis of Reversible Functions Beyond Gate Count and Quantum Cost




Author:

Robert Wille, Mehdi Saeedi, Rolf Drechsler
Workshop:
International Workshop on Logic Synthesis (IWLS)
Reference:

Berkeley, 2009
PDF:

[view Pdf]
Hyperlink:

[Link to the Workshop]



» Synthesizing Reversible Logic: An Overview




Author:

Robert Wille, Rolf Drechsler
Workshop:
Reed-Muller Workshop
Reference:

Naha, Okinawa, 2009
Hyperlink:

[Link to the Workshop]



» Synthesising Reversible Circuits from Irreversible Specifications using Reed-Muller Spectral Techniques




Author:

D. Michael Miller, Gerhard W. Dueck, Robert Wille
Workshop:
Reed-Muller Workshop
Reference:

Naha, Okinawa, 2009
Hyperlink:

[Link to the Workshop]



» FormED: A Formal Environment for Debugging




Author:

Andre Sülflow, Robert Wille, Christian Genz, Görschwin Fey, Rolf Drechsler
Workshop:
University Booth at Design, Automation and Test in Europe (DATE09)
Reference:

Nizza, 2009
PDF:

[view Pdf]
Hyperlink:

[Link to the Workshop]



» Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic




Author:

Robert Wille, Rolf Drechsler
Workshop:
Reversible Computation
Reference:

York, 2009
Hyperlink:

[Link to the Workshop]



» Equivalence Checking of Reversible Circuits




Author:

Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
Workshop:
12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference:

2009
Hyperlink:

[Link to the Workshop]



» Reversible Logic Synthesis with Output Permutation




Author:

Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler
Workshop:
International Workshop on Boolean Problems
Reference:

Freiberg, 2008
Hyperlink:

[Link to the Workshop]



» Contradiction Analysis for Constraint-based Random Simulation




Author:

Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
Workshop:
Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS)
Reference:

pp. 25-30, Dresden, 2008
Hyperlink:

[Link to the Workshop]



» Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking




Author:

Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
Workshop:
11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference:

pp. 169-178, Freiburg, 2008
Hyperlink:

[Link to the Workshop]



» Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits




Author:

Andre Sülflow, Ulrich Kühne, Robert Wille, Daniel Große, Rolf Drechsler
Workshop:
IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07)
Reference:

pp. 31-36, Beijing, P.R.China, 2007
PDF:

[view Pdf]
Hyperlink:

[Link to the Workshop]



» Parallelisierung von SAT-basierter Testmustergenerierung




Author:

Daniel Tille, Robert Wille, Rolf Drechsler
Workshop:
21. Workshop der GI/ITG-Fachgruppe Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS 2007)
Reference:

pp. 213-217, Hamburg, 2007
Hyperlink:

[Link to the Workshop]



» Building Free Binary Decision Diagrams Using SAT Solvers




Author:

Robert Wille, Görschwin Fey, Rolf Drechsler
Workshop:
8th Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM2007)
Reference:

Oslo, 2007
Hyperlink:

[Link to the Workshop]



» Formal Verification on the Word Level using SAT-like Proof Techniques




Author:

Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler
Workshop:
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Reference:

pp. 165-173, Erlangen, 2007
Hyperlink:

[Link to the Workshop]

















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