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BOOKS

» Computer: Wie funktionieren Smartphone, Tablet & Co.?
[Read more about this book!]



Publisher:


Springer
Author:

Rolf Drechsler, Andrea Fink, Jannis Stoppe
Format:
Taschenbuch
Year:


2017




» Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
[Read more about this book!]



Publisher:


Shaker Verlag
Author:

Daniel Große, Rolf Drechsler
Format:
Gebunden
Year:


2017




» Automatic Methods for the Refinement of System Models
[Read more about this book!]



Publisher:


Springer International Publishing
Author:

Julia Seiter, Robert Wille, Rolf Drechsler
Format:
Taschenbuch
Year:


2016




» Reversible and Quantum Circuits
[Read more about this book!]



Publisher:


Springer
Author:

Nabila Abdessaied, Rolf Drechsler
Format:
eBook, Hardcover
Year:


2016




» Languages, Design Methods, and Tools for Electronic System Design
[Read more about this book!]



Publisher:


Springer International Publishing (Verlag)
Author:

Rolf Drechsler, Robert Wille (Hrsg.)
Format:
Buch | Hardcover
Year:


2016




» Synthese- und Optimierungsverfahren für zukünftige Computerparadigmen
[Read more about this book!]



Publisher:


Shaker Verlag
Author:

Robert Wille, Oliver Keszöcze, Rolf Drechsler (Hrsg.)
Format:
gebunden
Year:


2015




» Formal Modeling and Verification of Cyber-Physical Systems
[Read more about this book!]



Publisher:


Springer
Author:

Rolf Drechsler, Ulrich Kühne (Hrsg.)
Format:
eBook, Softcover
Year:


2015




» Formal Specification Level
[Read more about this book!]



Publisher:


Springer
Author:

Mathias Soeken, Rolf Drechsler
Format:
eBook, Hardcover
Year:


2014




» Aspekte der Technischen Informatik
[Read more about this book!]



Publisher:


MV-Wissenschaft
Author:

Rolf Drechsler (Hrsg.)
Format:
Softcover
Year:


2014




» Auf dem Weg zum Quantencomputer - Entwurf reversibler Logik
[Read more about this book!]



Publisher:


Shaker Verlag
Author:

Rolf Drechsler, Mathias Soeken, Robert Wille (Hrsg.)
Format:
gebunden
Year:


2012




» High Quality Test Pattern Generation and Boolean Satisfiability
[Read more about this book!]



Publisher:


Springer
Author:

Stephan Eggersglüß, Rolf Drechsler
Format:
Hardcover
Year:


2012




» Applications of Evolutionary Computation Applications of Evolutionary Computation
[Read more about this book!]



Publisher:


Springer
Author:

Cecilia Di Chio, Anthony Brabazon, Gianni A. Di Caro, Rolf Drechsler, Muddassar Farooq, Jörn Grahl, Gary Greenfield, Christian Prins, Juan Romero und Giovanni Squillero, et al.
Format:
Gebunden
Year:


2011




» Towards a Design Flow for Reversible Logic
[Read more about this book!]



Publisher:


Springer
Author:

Robert Wille, Rolf Drechsler
Format:
Gebunden
Year:


2010




» Debugging at the Electronic System Level
[Read more about this book!]



Publisher:


Springer
Author:

Frank Rogin, Rolf Drechsler
Format:
Gebunden
Year:


2010




» Quality-Driven SystemC Design
[Read more about this book!]



Publisher:


Springer
Author:

Daniel Große, Rolf Drechsler
Format:
Hardcover
Year:


2010




» Test Pattern Generation using Boolean Proof Engines
[Read more about this book!]



Publisher:


Springer
Author:

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille
Format:
Hardcover
Year:


2009




» Robustness and Usability in Modern Design Flows
[Read more about this book!]



Publisher:


Springer
Author:

Görschwin Fey, Rolf Drechsler
Format:
Hardcover
Year:


2008




» Applications of Evolutionary Computing
[Read more about this book!]



Publisher:


Springer
Author:

M. Giacobini, A. Brabazon, S. Cagnoni, G. A. DiCaro, Rolf Drechsler, A. Ekart, A. I. Esparcia-Alcazar, M. Farooq, A. Fink, J. McCormack, M. O'Neill, J. Romero, F. Rothlauf, G. Squillero, S. Uyar, S. Yang
Format:
Gebunden
Year:


2008




» Applications of Evolutionary Computing
[Read more about this book!]



Publisher:


Springer
Author:

M. Giacobini, A. Brabazon, S. Cagoni, G.A. Di Caro, Rolf Drechsler, M. Farooq, A. Fink, E. Lutton, P. Machado, S. Minner, M. O'Neill, J. Romero, F. Rothlauf, G. Squillero, H. Takagi, A.S. Uyar, S. Yang
Format:
Gebunden
Year:


2007




» SATRIX - Algorithmen für Boolesche Erfüllbarkeit
[Read more about this book!]



Publisher:


Shaker Verlag
Author:

Daniel Große, Görschwin Fey, Rolf Drechsler (Hrsg.)
Format:
Gebunden
Year:


2007




» Applications of Evolutionary Computing
[Read more about this book!]



Publisher:


Springer
Author:

F. Rothlauf, J. Branke, S. Cagnoni, E. Costa, C. Cotta, Rolf Drechsler, E. Lutton, P. Machado, J.H. Moore, J. Romero, G.D. Smith, G. Squillero, H. Takagi (Eds.)
Format:
Gebunden
Year:


2006




» Advanced BDD Optimization
[Read more about this book!]



Publisher:


Springer Verlag
Author:

Rüdiger Ebendt, Görschwin Fey, Rolf Drechsler
Format:
Hardcover
Year:


2005




» Technische Informatik - Eine Einführung
[Read more about this book!]



Publisher:


Pearson Studium
Author:

Bernd Becker, Rolf Drechsler, Paul Molitor
Format:
Gebunden
Year:


2005




» Applications of Evolutionary Computing
[Read more about this book!]



Publisher:


Springer
Author:

Franz Rothlauf, Jürgen Branke, Stefano Cagnoni, David W. Corne, Rolf Drechsler, Yaochu Jin, Penousal Machado, Elena Marchiori, Juan Romero, George D. Smith, Giovanni Squillero
Format:
Gebunden
Year:


2005




» FunTaskIC - Eine integrierte Entwurfsumgebung für SystemC
[Read more about this book!]



Publisher:


Shaker Verlag
Author:

Görschwin Fey, Rolf Drechsler (Hrsg.)
Format:
Gebunden
Year:


2005




» Applications of Evolutionary Computing
[Read more about this book!]



Publisher:


Springer
Author:

G.R. Raidl, S. Cagnoni, J. Branke, D.W. Corne, Rolf Drechsler, Y. Jin, C.G. Johnson, P. Machado, E. Marchiori,F. Rothlauf, G.D. Smith, G. Squillero
Format:
Gebunden
Year:


2004




» Advanced Formal Verification
[Read more about this book!]



Publisher:


Kluwer Academic Publishers
Author:

Rolf Drechsler
Format:
Gebunden
Year:


2004




» Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
[Read more about this book!]



Publisher:


Shaker Verlag
Author:

Rolf Drechsler
Format:
Gebunden
Year:


2003




» Evolutionary Algorithms for Embedded System Design
[Read more about this book!]



Publisher:


Kluwer Academic Publishers
Author:

Rolf Drechsler, Nicole Drechsler
Format:
Gebunden
Year:


2002




» Software-Engineering und Hardware-Design
[Read more about this book!]



Publisher:


Carl Hanser Verlag
Author:

Axel Sikora, Rolf Drechsler
Format:
Gebunden
Year:


2002




» Towards One-Pass Synthesis
[Read more about this book!]



Publisher:


Kluwer Academic Publishers
Author:

Rolf Drechsler, Wolfgang Günther
Format:
Hardcover
Year:


2002




» Spectral Techniques in VLSI CAD
[Read more about this book!]



Publisher:


Kluwer Academic Publishers
Author:

Mitchell A. Thornton, Rolf Drechsler, D. Michel Miller
Format:
Hardcover
Year:


2001




» Formal Verification of Circuits
[Read more about this book!]



Publisher:


Kluwer Academic Publishers
Author:

Rolf Drechsler
Format:
Hardcover
Year:


2000




» Evolutionary Algorithms for VLSI CAD
[Read more about this book!]



Publisher:


Kluwer Academic Publishers
Author:

Rolf Drechsler
Format:
Hardcover
Year:


1998




» Binary Decision Diagrams: Theory and Implementations
[Read more about this book!]



Publisher:


Kluwer Academic Publisher
Author:

Rolf Drechsler, Bernd Becker
Format:
Hardcover
Year:


1998




» Graphenbasierte Funktionsdarstellung
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Publisher:


B.G. Teubner
Author:

Rolf Drechsler, Bernd Becker
Format:
Gebunden
Year:


1998




» Functional Decision Diagrams und ihre Anwendung
[Read more about this book!]



Publisher:


Modell Verlag
Author:

Rolf Drechsler
Format:
Gebunden
Year:


1996





BOOK CONTRIBUTIONS
» Logic Synthesis for Majority based In-Memory Computing
Bigpicture: Advances in Memristors, Memristive Devices and Systems Author:

Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler

Editor:Sundarapandian Vaidyanathan, Christos Volos
Booktitle:Advances in Memristors, Memristive Devices and Systems
Publisher:Springer
Sites:425 - 448
Year:2017
Format:Hardcover



» Formal Verification of SystemC-based Cyber Components
Bigpicture: Industrial Internet of Things: Cybermanufacturing Systems Author:

Daniel Große, Hoang M. Le, Rolf Drechsler

Editor:Sabina Jeschke, Christian Brecher, Houbing Song, Danda B. Rawat
Booktitle:Industrial Internet of Things: Cybermanufacturing Systems
Publisher:Springer
Sites:137-167
Year:2016
Format:Hardcover



» A framework for reversible circuit complexity
Bigpicture: Problems and New Solutions in the Boolean Domain Author:

Mathias Soeken, Nabila Abdessaied, Rolf Drechsler

Editor:Bernd Steinbach
Booktitle:Problems and New Solutions in the Boolean Domain
Publisher:Cambridge Scholars Publishing
Sites:327 - 341
Year:2016
Format:Paperback



» Formal Specification Level
Bigpicture: Models, Methods, and Tools for Complex Chip Design: Selected Contributions from FDL 2012 Author:

Rolf Drechsler, Mathias Soeken, Robert Wille

Editor:Jan Haase
Booktitle:Models, Methods, and Tools for Complex Chip Design: Selected Contributions from FDL 2012
Publisher:Springer
Sites:37-52
Year:2014
Format:Hardcover



» SyReC: A Programming Language for Synthesis of Reversible Circuits
Bigpicture: System Specification and Design Languages: Selected Contributions from FDL 2010 Author:

Robert Wille, Sebastian Offermann, Rolf Drechsler

Editor:Tom J. Kazmierski, Adam Morawiec
Booktitle:System Specification and Design Languages: Selected Contributions from FDL 2010
Publisher:Springer
Sites:207-222
Year:2012
Format:Hardcover



» Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis
Bigpicture: Design and Test Technology for Dependable Systems-on-Chip Author:

Daniel Große, Görschwin Fey, Rolf Drechsler

Editor:Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus
Booktitle:Design and Test Technology for Dependable Systems-on-Chip
Publisher:Information Science Reference
Sites:119-129
Year:2011
Format:Hardcover



» SMT-based Stimuli Generation in the SystemC Verification Library
Bigpicture: Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s: Selected Contributions on Specification, Design, and Verification from FDL 2009 Author:

Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler

Editor:Dominique Borrione
Booktitle:Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s: Selected Contributions on Specification, Design, and Verification from FDL 2009
Publisher:Springer
Sites:227-244
Year:2010
Format:Hardcover



» Synthesis of Boolean Functions in Reversible Logic
Bigpicture: Progress in Applications of Boolean Functions (Synthesis Lectures on Digital Circuits and Systems) Author:

Robert Wille, Rolf Drechsler

Editor:Tsutomu Sasao, Jon T. Butler, Mitchell Thornton
Booktitle:Progress in Applications of Boolean Functions (Synthesis Lectures on Digital Circuits and Systems)
Publisher:Morgan and Claypool Publishers
Sites:75-92
Year:2010
Format:Paperback



» Non-Clausal SAT and ATPG
Bigpicture: Handbook of Satisfiability Author:

Rolf Drechsler, Tommi Junttila and Ilkka Niemelä

Editor:A. Biere, M. Heule, H. van Maaren, T. Walsh
Booktitle:Handbook of Satisfiability
Publisher:IOS Press
Sites:655-693
Year:2009
Format:gebunden



» Debugging Contradictory Constraints in Constraint-based Random Simulation
Bigpicture: Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL'08 Author:

Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler

Editor:Martin Radetzki
Booktitle:Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL'08
Publisher:Springer
Sites:273-290
Year:2009
Format:gebunden



» SWORD: A SAT like Prover Using Word Level Information
Bigpicture: VLSI-SoC: Advanced Topics on Systems on a Chip:
A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip Author:

Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler

Editor:Ricardo Reis, Vincent Mooney, Paul Hasler
Booktitle:VLSI-SoC: Advanced Topics on Systems on a Chip: A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip
Publisher:Springer
Sites:175-192
Year:2009
Format:Hardcover



» An Integrated SystemC Debugging Environment
Bigpicture: Embedded Systems Specification and Design Languages: Selected contributions from FDL'07 Author:

Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke

Editor:Eugenio Villar
Booktitle:Embedded Systems Specification and Design Languages: Selected contributions from FDL'07
Publisher:Springer
Sites:59-71
Year:2008
Format:gebunden



» Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques
Bigpicture: Embedded Systems Specification and Design Languages: Selected contributions from FDL'07 Author:

Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler

Editor:Eugenio Villar
Booktitle:Embedded Systems Specification and Design Languages: Selected contributions from FDL'07
Publisher:Springer
Sites:73-86
Year:2008
Format:gebunden



» Exact BDD Minimization for Path-Related Objective Functions
Bigpicture: VLSI-SoC: From Systems to Silicon Author:

Rüdiger Ebendt, Rolf Drechsler

Editor:Ricardo Reis, Ada Osseiran, Hans-Jörg Pleiderer
Booktitle:VLSI-SoC: From Systems to Silicon
Publisher:Springer
Sites:299-315
Year:2007
Format:gebunden



» Stuck-At-Fault Testability of SPP Three-Level Logic Forms
VLSI-SOC: From Systems to Chips Author:

V. Ciriani, A. Bernasconi, Rolf Drechsler

Editor:M. Glesner, R. Reis, L. Indrusiak, V. Mooney, H. Eveking
Booktitle:VLSI-SOC: From Systems to Chips
Publisher:Springer
Sites:299-313
Year:2006
Format:gebunden



» Exploration of Sequential Depth by Evolutionary Algorithms
VLSI-SOC: From Systems to Chips Author:

Nicole Drechsler, Rolf Drechsler

Editor:M. Glesner, R. Reis, L. Indrusiak, V. Mooney, H. Eveking
Booktitle:VLSI-SOC: From Systems to Chips
Publisher:Springer Boston
Sites:73-83
Year:2006
Format:gebunden



» Processor Verification
Bigpicture: Customizable Embedded Processors Author:

Daniel Große, Robert Siegmund, Rolf Drechsler

Editor:Paolo Ienne, Rainer Leupers
Booktitle:Customizable Embedded Processors
Publisher:Elsevier
Sites:281-302
Year:2006
Format:gebunden



» Automatic Test Pattern Generation
Bigpicture: Formal Methods for Hardware Verification, LNCS 3965 Author:

Rolf Drechsler, Görschwin Fey

Editor:Marco Bernardo, Alessandro Cimatti
Booktitle:Formal Methods for Hardware Verification, LNCS 3965
Publisher:Springer
Sites:30-55
Year:2006
Format:gebunden



» System-level validation using formal techniques
Bigpicture: System-on-Chip: Next Generation Electronics Author:

Rolf Drechsler, Daniel Große

Editor:Bashir M. Al-Hashimi
Booktitle:System-on-Chip: Next Generation Electronics
Publisher:The IEE
Sites:715-745
Year:2006
Format:gebunden





JOURNALS

» A PLiM computer for the IoT
[Link to the Homepage of this journal]




Author:

Mathias Soeken, Pierre-Emmanuel Gaillardon, Saeideh Shirinzadeh, Rolf Drechsler, Giovanni De Micheli
Journal:
Computer
Details:
50(6):35-40, DOI: 10.1109/MC.2017.173
Year:


2017





» Towards a Verification Flow Across Abstraction Levels:
Verifying Implementations Against Their Formal Specification

[Link to the Homepage of this journal]




Author:

Pablo Gonzalez-de-Aledo, Nils Przigoda, Robert Wille, Rolf Drechsler, Pablo Sanchez
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
36(3):475-488, DOI: 10.1109/TCAD.2016.2611494
Year:


2017





» Verifying the Structure and Behavior in UML/OCL Models Using Satisfiability Solvers
[Link to the Homepage of this journal]




Author:

Nils Przigoda, Mathias Soeken, Robert Wille, Rolf Drechsler
Journal:
IET Cyber-Physical Systems: Theory & Applications
Details:
Volume 1, Issue 1, December 2016, pp. 49-59
DOI: 10.1049/iet-cps.2016.0022
Year:


2016





» metaSMT: Focus On Your Application And Not On Solver Integration
[Link to the Homepage of this journal]




Author:

Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey
Journal:
International Journal of Software Tools for Technology Transfer
Details:
Regular Paper, pp 1-17, DOI10.1007/s10009-016-0426-1 Link
Year:


2016





» Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits
[Link to the Homepage of this journal]




Author:

Arighna Deb, Robert Wille, Oliver Keszöcze, Stefan Hillmich, Rolf Drechsler
Journal:
Journal on Emerging Technologies in Computing Systems (JETC)
Details:
Volume 13, Issue 1
Year:


2016





» Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability
[Link to the Homepage of this journal]




Author:

Arighna Deb, Debesh K. Das, Hafizur Rahaman, Robert Wille, Rolf Drechsler, Bhargab B. Bhattacharya
Journal:
Journal on Emerging Technologies in Computing Systems (JETC)
Details:
Volume 12 Issue 4, Article No. 34
Year:


2016





» On Optimization-based ATPG and its Application for Highly Compacted Test Sets
[Link to the Homepage of this journal]




Author:

Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Vol. 35(12), pp. 2104-2117
Year:


2016





» Time-resolved detection of diffusion limited temperature gradients inside single isolated burning droplets using Rainbow Refractometry
[Link to the Homepage of this journal]




Author:

Christopher Rosebrock, Saeideh Shirinzadeh, Mathias Soeken, Norbert Riefler, Thomas Wriedt, Rolf Drechsler, Lutz Mädler
Journal:
Combustion and Flame
Details:
Volume 168, June 2016, Pages 255–269
Year:


2016





» Complexity of Reversible Circuits and their Quantum Implementations
[Link to the Homepage of this journal]




Author:

Nabila Abdessaied, Matthew Amy, Rolf Drechsler, Mathias Soeken
Journal:
Theoretical Computer Science
Details:
Volume 618, (March 2016), pp. 85–106. DOI:10.1016/j.tcs.2016.01.011
Year:


2016





» Analyzing Inconsistencies in UML/OCL Models
[Link to the Homepage of this journal]




Author:

Nils Przigoda, Robert Wille, Rolf Drechsler
Journal:
Journal of Circuits, Systems and Computers
Details:
Volume 25, Issue 03, March 2016
DOI: 10.1142/S0218126616400211
Year:


2016





» Atomic distributions in crystal structures solved by Boolean satisfiability techniques
[Link to the Homepage of this journal]




Author:

Mathias Soeken, Rolf Drechsler, Reinhard X. Fischer
Journal:
Zeitschrift für Kristallographie - Crystalline Materials
Details:
Z. Kristallogr. 2016; 231(2): 107–111
Year:


2015





» SyReC: A Hardware Description Language for the Specification and Synthesis of Reversible Circuits
[Link to the Homepage of this journal]




Author:

Robert Wille, Eleonora Schonborn, Mathias Soeken, Rolf Drechsler
Journal:
INTEGRATION, the VLSI Journal
Details:
53(3):39-53
Year:


2016





» Analyzing SystemC Designs: SystemC Analysis Approaches for Varying Applications
[Link to the Homepage of this journal]




Author:

Jannis Stoppe, Rolf Drechsler
Journal:
Sensors
Details:
Volume (issue) 15(5), pages 10399-10421
Year:


2015





» Scalable One-Pass Synthesis for Digital Microfluidic Biochips
[Link to the Homepage of this journal]




Author:

Robert Wille, Oliver Keszöcze, Tobias Boehnisch, Alexander Kroker, Rolf Drechsler
Journal:
IEEE Design & Test of Computers
Details:
Volume 32, Issue 66, Pages 41—50
Year:


2015





» QMDDs: Efficient Quantum Function Representation and Manipulation
[Link to the Homepage of this journal]




Author:

Philipp Niemann, Robert Wille, D. Michael Miller, Mitchell A. Thornton, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 35, Number 1, pp. 86-99
DOI: 10.1109/TCAD.2015.2459034
Year:


2016





» Embedding of Large Boolean Functions for Reversible Logic
[Link to the Homepage of this journal]




Author:

Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler
Journal:
Journal on Emerging Technologies in Computing Systems (JETC)
Details:
Volume 12, Issue 4
Preprint available at arXiv 1408.3586
Year:


2015





» Ancilla-free synthesis of large reversible functions using binary decision diagrams
[Link to the Homepage of this journal]




Author:

Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler
Journal:
Journal of Symbolic Computation
Details:
accepted, preprint available at arXiv 1408.3955
Year:


2015





» Benefits of illustrations and videos for technical documentations
[Link to the Homepage of this journal]




Author:

Cornelia Große, Lisa Jungmann, Rolf Drechsler
Journal:
Computers in Human Behavior
Details:
Volume 45, April 2015, Pages 109–120
DOI: 10.1016/j.chb.2014.11.095
Year:


2015





» Incorporating User Preferences in Many-Objective Optimization using Relation epsilon-Preferred
[Link to the Homepage of this journal]




Author:

Nicole Drechsler, André Sülflow, Rolf Drechsler
Journal:
Natural Computing
Details:
Volume 14, Issue 3, pp 469-483
Year:


2015





» Exact Reordering of Circuit Lines for Nearest Neighbor Quantum Architectures
[Link to the Homepage of this journal]




Author:

Robert Wille, Aaron Lye, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 33, Number 12, pp. 1818-1831
DOI: 10.1109/TCAD.2014.2356463
Year:


2014





» Special Issue on Reversible Computation
[Link to the Homepage of this journal]




Author:

Robert Wille, Rolf Drechsler, Mehdi . B. Tahoori (editors)
Journal:
Journal on Emerging Technologies in Computing Systems (JETC)
Details:
Volume 11, Number 2
Year:


2014





» An effective fault ordering heuristic for SAT-based dynamic test compaction techniques
[Link to the Homepage of this journal]




Author:

Stephan Eggersglüß, Rolf Drechsler
Journal:
it-Information Technology
Details:
Volume 56, Number 4, pp. 157-164
Special Issue
Year:


2014





» Testing integrated circuits
[Link to the Homepage of this journal]




Author:

Rolf Drechsler
Journal:
it-Information Technology
Details:
Volume 56, Number 4, pp. 148-149
Special Issue
Year:


2014





» Upper bounds for reversible circuits based on Young subgroups
[Link to the Homepage of this journal]




Author:

Nabila Abdessaied, Mathias Soeken, Michael Kirkedal Thomsen, Rolf Drechsler
Journal:
Information Processing Letters
Details:
Volume 114, Number 06 (June 2014), pp. 282-286. DOI: 10.1016/j.ipl.2014.01.003
Year:


2014





» Considering Nearest Neighbor Constraints of Quantum Circuits at the Reversible Circuit Level




Author:

Robert Wille, Aaron Lye, Rolf Drechsler
Journal:
Quantum Information Processing
Details:
DOI: http://dx.doi.org/10.1007/s11128-013-0642-5
Year:


2013





» Quantum circuits employing roots of the Pauli matrices
[Link to the Homepage of this journal]




Author:

Mathias Soeken, D. Michael Miller, Rolf Drechsler
Journal:
Physical Review A
Details:
Volume 88, 042322, 2013, DOI: 10.1103/PhysRevA.88.042322
Year:


2013





» Trading Off Circuit Lines and Gate Costs in the Synthesis of Reversible Logic
[Link to the Homepage of this journal]




Author:

Robert Wille, Mathias Soeken, D. Michael Miller, Rolf Drechsler
Journal:
INTEGRATION, the VLSI Journal
Details:
Volume 47, Number 2, pp. 284-294, DOI: 10.1016/j.vlsi.2013.08.002
Year:


2014





» A Formal Model for Embedded Brain Reading
[Link to the Homepage of this journal]




Author:

Elsa Andrea Kirchner, Rolf Drechsler
Journal:
Industrial Robot: an International Journal
Details:
Volume 40, Issue 6, pp. 530-540
Year:


2013





» Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits
[Link to the Homepage of this journal]




Author:

Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler
Journal:
Multiple-Valued Logic and Soft Computing
Details:
Volume 21, Number 5-6, 2013, pp. 627-640
Year:


2013





» RevKit: An Open Source Toolkit for the Design of Reversible Circuits
[Link to the Homepage of this journal]




Author:

Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Journal:
Reversible Computation 2011 (Series: Lecture Notes in Computer Science)
Details:
Volume 7165, Third International Workshop, RC 2011, Revised Papers, pp. 64-76
Year:


2012





» Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis




Author:

Daniel Große, Görschwin Fey, Rolf Drechsler
Journal:
Electronic Communications of the EASST
Details:
Volume 62, 13 pages
Year:


2013





» Automatic TLM Fault Localization for SystemC
[Link to the Homepage of this journal]




Author:

Hoang M. Le, Daniel Große, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 31, Number 8, pp. 1249-1262,
DOI: 10.1109/TCAD.2012.2188800
Year:


2012





» Special Issue on Reversible Computation
[Link to the Homepage of this journal]




Author:

Rolf Drechsler, Irek Ulidowski, Robert Wille (editors)
Journal:
Multiple-Valued Logic and Soft Computing
Details:
Volume 18, Number 1
Year:


2012





» RevKit: A Toolkit for Reversible Circuit Design
[Link to the Homepage of this journal]




Author:

Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Journal:
Multiple-Valued Logic and Soft Computing
Details:
Volume 18, Number 1, pp. 55-65
Year:


2012





» A Highly Fault-Efficient SAT-Based ATPG Flow
[Link to the Homepage of this journal]




Author:

Stephan Eggersglüß, Rolf Drechsler
Journal:
IEEE Design & Test of Computers
Details:
Volume 29, Issue 4 (July/August), pp. 63-70
Year:


2012





» Efficient Data Structures and Methodologies for SAT-based ATPG providing High Fault Coverage in Industrial Application
[Link to the Homepage of this journal]




Author:

Stephan Eggersglüß, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 30, Number 9, pp. 1411-1415,
DOI: 10.1109/TCAD.2011.2152450
Year:


2011





» Effective Robustness Analysis using Bounded Model Checking Techniques
[Link to the Homepage of this journal]




Author:

Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 30, Number 8, pp. 1239-1252 DOI: 10.1109/TCAD.2011.2120950
Year:


2011





» Synthesis of Quantum Circuits for Linear Nearest Neighbor Architectures
[Link to the Homepage of this journal]




Author:

Mehdi Saeedi, Robert Wille, Rolf Drechsler
Journal:
Quantum Information Processing
Details:
Volume 10, Number 3, pp. 355-377
DOI: 10.1007/s11128-010-0201-2
Year:


2011





» Debugging Reversible Circuits
[Link to the Homepage of this journal]




Author:

Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
Journal:
INTEGRATION, the VLSI Journal
Details:
Volume 44, Number 1, pp. 51-61, January
DOI: 10.1016/j.vlsi.2010.08.002
Year:


2011





» BDD-Based Synthesis of Reversible Logic
[Link to the Homepage of this journal]




Author:

Robert Wille, Rolf Drechsler
Journal:
International Journal of Applied Metaheuristic Computing (IJAMC)
Details:
Volume 1, Number 4, pp. 25-41
Year:


2010





» Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen
[Link to the Homepage of this journal]




Author:

Görschwin Fey, Andre Sülflow, Stefan Frehse, Rolf Drechsler
Journal:
it-Information Technology
Details:
Volume 52, Number 4, pp. 216-223
PDF Download
Year:


2010





» Towards Fully Automatic Synthesis of Embedded Software
[Link to the Homepage of this journal]




Author:

Ulrich Kühne, Daniel Große, Rolf Drechsler
Journal:
IEEE Embedded Systems Letters
Details:
Volume 2, Number 3, pp. 53-57, September
Year:


2010





» Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic
[Link to the Homepage of this journal]




Author:

Robert Wille, Rolf Drechsler
Journal:
Electronic Notes in Theoretical Computer Science
Details:
Volume 253, Number 6, pp. 57-70
DOI: 10.1016/j.entcs.2010.02.006
Year:


2010





» Incremental Solving Techniques for SAT-based ATPG
[Link to the Homepage of this journal]




Author:

Daniel Tille, Stephan Eggersglüß, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 29, Number 7, pp. 1125-1130, July
Year:


2010





» Synthese reversibler Logik
[Link to the Homepage of this journal]




Author:

Robert Wille, Rolf Drechsler
Journal:
it-Information Technology
Details:
Volume 52, Number 1, pp. 30-38
PDF Download
Year:


2010





» MONSOON: SAT-based ATPG for Path Delay Faults Using Multiple-Valued Logics
[Link to the Homepage of this journal]




Author:

Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Rolf Drechsler
Journal:
Journal of Electronic Testing: Theory and Applications
Details:
Volume 26, Number 3 / June, pp. 307-322
Pdf download (Preliminary Version)
The final publication is available at www.springerlink.com
Year:


2010





» Overcoming the limitations of data introspection for SystemC
[Link to the Homepage of this journal]




Author:

Christian Genz, Rolf Drechsler
Journal:
EDA Tech Forum
Details:
Volume 6, Issue 5, Pages 30-34 (December 2009)
Year:


2009





» Weighted A* search - unifying view and application
[Link to the Homepage of this journal]




Author:

Rüdiger Ebendt, Rolf Drechsler
Journal:
Artificial Intelligence
Details:
Volume 173, Issue 15, Pages 1367-1456 (September 2009)
Year:


2009





» Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
[Link to the Homepage of this journal]




Author:

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille
Journal:
it - information technology
Details:
Volume 51, Number 2, pp. 102-111
Pdf download
Year:


2009





» Exact Synthesis of Elementary Quantum Gate Circuits
[Link to the Homepage of this journal]




Author:

Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Journal:
Multiple-Valued Logic and Soft Computing
Details:
Volume 15, Number 4, pp. 283-300
Year:


2009





» Advanced Verification by Automatic Property Generation
[Link to the Homepage of this journal]




Author:

Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke
Journal:
IET Computers & Digital Techniques
Details:
Volume 3, Issue 4, pp. 338-353, July
Year:


2009





» Exact Multiple Control Toffoli Network Synthesis with SAT Techniques
[Link to the Homepage of this journal]




Author:

Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 28, Number 5, pp. 703-715, May
DOI: 10.1109/TCAD.2009.2017215
Year:


2009





» Modeling and Proving Completeness in Formal Verification of Counting Heads
[Link to the Homepage of this journal]




Author:

Sebastian Kinder, Rolf Drechsler
Journal:
Software Tools for Technology Transfer (STTT)
Details:
Springer, Volume 10, Number 6, pp. 521 - 534
Year:


2008





» On Acceleration of SAT-based ATPG for Industrial Designs
[Link to the Homepage of this journal]




Author:

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Daniel Tille
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 27, Number 7, pp. 1329-1333, July
Year:


2008





» Improved SAT-based Reachability Analysis with Observability Don’t Cares
[Link to the Homepage of this journal]




Author:

Sean Safarpour, Andreas Veneris and Rolf Drechsler
Journal:
Journal on Satisfiability, Boolean Modeling and Computation (JSAT)
Details:
Volume 5, pp. 1-25, Special Volume on Application of Constraints to Formal Verification
Year:


2008





» On the Construction of Small Fully Testable Circuits with Low Depth
[Link to the Homepage of this journal]




Author:

Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler
Journal:
Embedded Hardware Design - Microprocessors and Microsystems (MICPRO)
Details:
Special Issue, Volume 32, Issues 5-6, pp. 263-269
Year:


2008





» Logic Minimization and Testability of 2-SPP Networks
[Link to the Homepage of this journal]




Author:

Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 27, Number 7, pp. 1190-1202, July
Year:


2008





» Analyzing Functional Coverage in Bounded Model Checking
[Link to the Homepage of this journal]




Author:

Daniel Große, Ulrich Kühne, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 27, Number 7, pp. 1305-1314, July
Year:


2008





» Automatic Fault Localization for Property Checking
[Link to the Homepage of this journal]




Author:

Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 27, Number 6, pp. 1138-1149, June
Year:


2008





» BDD-based Verification of Scalable Designs
[Link to the Homepage of this journal]




Author:

Daniel Große, Rolf Drechsler
Journal:
Facta Universitatis, Series: Electronics and Energetics
Details:
Volume 20, Number 3, pp. 367-379
Year:


2007





» Building Free Binary Decision Diagrams Using SAT Solvers
[Link to the Homepage of this journal]




Author:

Robert Wille, Görschwin Fey, Rolf Drechsler
Journal:
Facta Universitatis, Series: Electronics and Energetics
Details:
Volume 20, Number 3, pp. 381-394,
Year:


2007





» An Integrated Approach for Combining BDDs and SAT Provers
[Link to the Homepage of this journal]




Author:

Rolf Drechsler, Görschwin Fey, Sebastian Kinder
Journal:
Facta Universitatis, Series: Electronics and Energetics
Details:
Volume 20, Number 3, pp. 415-436
Year:


2007





» Technische Dokumentation von Soft- und Hardware in eingebetteten Systemen
[Link to the Homepage of this journal]




Author:

Beate Muranko, Rolf Drechsler
Journal:
it - information technology
Details:
Number 2, pp. 110-117
Pdf download
Year:


2007





» Exact minimisation of path-related objective functions for binary decision diagrams
[Link to the Homepage of this journal]




Author:

Rüdiger Ebendt, Rolf Drechsler
Journal:
IEE Proceedings Computer & Digital Techniques
Details:
Volume 153, Number 4, pp. 231-242, July
Year:


2006





» Testability of SPP Three-Level Logic Networks in Static Fault Models
[Link to the Homepage of this journal]




Author:

Valentina Ciriani, Anna Bernasconi, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 25, Number 10, pp. 2241-2248, October
Year:


2006





» The Effect of Improved Lower Bounds in Dynamic BDD Reordering
[Link to the Homepage of this journal]




Author:

Rüdiger Ebendt, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 25, Number 5, pp. 902-909, May
Year:


2006





» Minimizing the Number of Paths in BDDs - Theory and Algorithm
[Link to the Homepage of this journal]




Author:

Görschwin Fey, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 25, Number 1, pp. 4-11, January
Year:


2006





» Combining Ordered Best-First Search with Branch and Bound for Exact BDD Minimization
[Link to the Homepage of this journal]




Author:

Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 24, Number 10, pp. 1515-1529, October
Year:


2005





» System Level Validation Using Formal Techniques
[Link to the Homepage of this journal]




Author:

Rolf Drechsler, Daniel Große
Journal:
IEE Proceedings Computer & Digital Techniques, Special Issue on Embedded Microelectronic Systems: Status and Trends
Details:
Volume 152, Number 3, pp. 393-406, May
Year:


2005





» Generic Implementation of Multi-Valued Decision Diagram Packages




Author:

Rolf Drechsler, Dragan Jankovic, Radomir Stankovic
Journal:
Multiple-Valued Logic and Soft Computing
Details:
Volume 11, Numbers 1-2, pp. 1-18
Year:


2005





» Project-Based Learning in Student Teams in Computer Science Education
[Link to the Homepage of this journal]




Author:

Andreas Breiter, Görschwin Fey, Rolf Drechsler
Journal:
Facta Universitatis, Series: Electronics and Energetics
Details:
Volume 18, Number 2, August, pp. 165-180.
Year:


2005





» Synthesis of Fully Testable Circuits from BDDs
[Link to the Homepage of this journal]




Author:

Rolf Drechsler, Junhao Shi, Görschwin Fey
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 23, Number 3, March
Year:


2004





» Methods for Construction of Recursive Algorithms for Reed-Mulle-Fourier Polarity Matrices Calculation




Author:

Dragan Jankovic, Rolf Drechsler
Journal:
Multiple-Valued Logic and Soft Computing
Details:
Volume 10, Numbers 1, pp. 29-50
Year:


2004





» Using Word-Level Information in Formal Hardware Verification
[Link to the Homepage of this journal]




Author:

Rolf Drechsler
Journal:
Automation and Remote Control
Details:
Year:


Volume 65, Issue 6, pp. 963-977, June 2004





» An Improved Branch and Bound Algorithm for Exact BDD Minimization
[Link to the Homepage of this journal]




Author:

Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 22, Number 12, pp. 1657-1663, December
Year:


2003





» Recursive Bi-Partitioning of Netlists for Large Number of Partitions
[Link to the Homepage of this journal]




Author:

Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst
Journal:
Journal of Systems Architecture - the Euromicro Journal
Details:
Volume 49, pp. 521-528
Year:


2003





» Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC
[Link to the Homepage of this journal]




Author:

Daniel Große, Rolf Drechsler
Journal:
it - information technology
Details:
Number 4, pp. 219-226, August
Year:


2003





» Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams
[Link to the Homepage of this journal]




Author:

Wolfgang Günther, Rolf Drechsler
Journal:
IEEE Transactions on Computers
Details:
Volume 52, Number 9, pp. 1196-1209, September
Year:


2003





» Exact Routing with Search Space Reduction
[Link to the Homepage of this journal]




Author:

Frank Schmiedle, Rolf Drechsler, Bernd Becker
Journal:
IEEE Transactions on Computers
Details:
Volume 52, Number 6, pp. 815-825, June
Year:


2003





» Computer Architecture Core of Knowledge for Computer Science Studies




Author:

M. Stojcev, I. Milentijevic, D. Kehagias, Rolf Drechsler, M. Gusev
Journal:
Cyprus Computer Society Journal
Details:
Volume I, Edition 4, April
Year:


2003





» Polynomial Formal Verification of Multipliers
[Link to the Homepage of this journal]




Author:

Martin Keim, Rolf Drechsler, Bernd Becker, Michael Martin, Paul Molitor
Journal:
Formal Methods in System Design: An International Journal
Details:
Volume 22, Issue 1, pp. 39-58
Year:


2003





» Low Power Optimization Techniques for BDD Mapped Circuits Using Temporal Correlation
[Link to the Homepage of this journal]




Author:

Rolf Drechsler, Mikael Kerttu, Per Lindgren, Mitch Thornton
Journal:
Canadian Journal of Electrical and Computer Engineering
Details:
Volume 27, Number 4, pp. 159-164, October
Year:


2002





» Minimization of Word-level Decision Diagrams
[Link to the Homepage of this journal]




Author:

Rolf Drechsler, Wolfgang Günther, Stefan Höreth.
Journal:
INTEGRATION, the VLSI Journal
Details:
Volume 33, Issue 1-2, pp. 39-70
Year:


2002





» Minimization of Free BDDs
[Link to the Homepage of this journal]




Author:

Wolfgang Günther, Rolf Drechsler
Journal:
INTEGRATION, the VLSI Journal
Details:
Volume 32, Issue 1-2, pp. 41-59
Year:


2002





» Verifying Integrity of Decision Diagrams
[Link to the Homepage of this journal]




Author:

Rolf Drechsler
Journal:
INTEGRATION, the VLSI Journal
Details:
Volume 32, Issue 1-2, pp. 61-75
Year:


2002





» Heuristic Learning based on Genetic Programming
[Link to the Homepage of this journal]




Author:

Frank Schmiedle, Nicole Drechsler, Daniel Große and Rolf Drechsler
Journal:
Genetic Programming and Evolvable Machines
Details:
Volume 3, pp. 363-388, December
Year:


2002





» Dynamic Re-Encoding During MDD Minimization
[Link to the Homepage of this journal]




Author:

Frank Schmiedle, Wolfgang Günther, Rolf Drechsler
Journal:
Multiple-Valued Logic - An International Journal
Details:
Volume 8, Numbers 5-6, pp. 625-643
Year:


2002





» History-based Dynamic BDD Minimization
[Link to the Homepage of this journal]




Author:

Rolf Drechsler, Wolfgang Günther
Journal:
INTEGRATION, the VLSI Journal
Details:
Volume 31, Issue 1, pp. 51-63
Year:


2001





» Äquivalenzvergleich digitaler Schaltungen im industriellen Umfeld




Author:

Rolf Drechsler
Journal:
it+ti - Informationstechnik und Technische Informatik
Details:
Oldenbourg Wissenschaftsverlag, Number 4, pp. 200-205
Year:


2001





» Fault Simulation in Multi-Valued Logic Networks
[Link to the Homepage of this journal]




Author:

Rolf Drechsler, Martin Keim, Bernd Becker
Journal:
Multiple-Valued Logic - An International Journal
Details:
Volume 7, Numbers 1-2, pp. 25-47
Year:


2001





» Binary Decision Diagrams in Theory and Practice
[Link to the Homepage of this journal]




Author:

Rolf Drechsler, Detlef Sieling
Journal:
Software Tools for Technology Transfer (STTT)
Details:
Springer, Number 3, pp. 112-136
Year:


2001





» Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
[Link to the Homepage of this journal]




Author:

Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker
Journal:
Journal of Electronic Testing, Theory and Application (JETTA)
Details:
No. 17, pp. 37-51, February
Year:


2001





» Decision Diagram Method for Calculation of Pruned Walsh Transform
[Link to the Homepage of this journal]




Author:

Dragan Jankovic, Radomir Stankovic, Rolf Drechsler
Journal:
IEEE Transactions on Computers
Details:
Volume 50, Number 2, pp. 147-157, February
Year:


2001





» Using Lower Bounds during Dynamic BDD Minimization
[Link to the Homepage of this journal]




Author:

Rolf Drechsler, Wolfgang Günther, Fabio Somenzi
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 20, Number 1, pp. 51-57, January
Year:


2001





» ACTion: Combining Logic Synthesis and Technology Mapping for MUX based FPGAs
[Link to the Homepage of this journal]




Author:

Wolfgang Günther and Rolf Drechsler.
Journal:
Journal of Systems Architecture - the Euromicro Journal
Details:
Volume 46, Issue 14, pp. 1321-1334, December
Year:


2000





» Boolean Function Representation and Spectral Characterization Using AND/OR Graphs
[Link to the Homepage of this journal]




Author:

Alenka Zuzek, Rolf Drechsler, Mitch Thornton
Journal:
INTEGRATION, the VLSI Journal
Details:
Volume 29, Issue 2, pp. 101-116, September
Year:


2000





» Genetic Algorithm for Minimization of fixed polarity Reed-Muller expressions




Author:

Rolf Drechsler, Bernd Becker and Nicole Drechsler
Journal:
IEE Proceedings Computers and Digital Techniques
Details:
Volume 147, Number 5, September
Year:


2000





» On the Computational Power of Linearly Transformed BDDs
[Link to the Homepage of this journal]




Author:

Wolfgang Günther, Rolf Drechsler
Journal:
Information Processing Letters
Details:
Volume 75, Nummer 3, pp. 119-125, August
Year:


2000





» Fast Exact Minimization of BDDs
[Link to the Homepage of this journal]




Author:

Rolf Drechsler, Nicole Drechsler, Wolfgang Günther
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 19, Number 3, pp. 384-389, March
Year:


2000





» Pseudo Kronecker Expressions for Symmetric Functions
[Link to the Homepage of this journal]




Author:

Rolf Drechsler
Journal:
IEEE Transactions on Computers
Details:
Volume 48, Number 9, pp. 987-990, September
Year:


1999





» Testability of 2-Level AND/EXOR Circuits
[Link to the Homepage of this journal]




Author:

Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker
Journal:
Journal of Electronic Testing, Theory and Application (JETTA)
Details:
Volume 14, Number 3, pp. 173-192, June
Year:


1999





» BDD Minimization Using Symmetries
[Link to the Homepage of this journal]




Author:

Christoph Scholl, Dirk Möller, Paul Molitor, Rolf Drechsler
Journal:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 18, Number 2, pp. 81-100, February
Year:


1999





» On Variable Ordering and Decomposition Type Choice in OKFDDs
[Link to the Homepage of this journal]




Author:

Rolf Drechsler, Bernd Becker, Andrea Jahnke
Journal:
IEEE Transactions on Computers
Details:
Volume 47, Number 12, December
Year:


1998






CONFERENCES



» Early SoC Security Validation by VP-based Static Information Flow Analysis




Author:

Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

Irvine, USA, 2017
Hyperlink:

[To the Site of this Conference]



» Self-practicing of logic circuits through mobile devices: Lecturers' and students' perceptions




Author:

Mazyar Seraj, Cornelia Große, Rolf Drechsler
Conference:
9th annual International Conference on Education and New Learning Technologies (EduLearn17)
Reference:

Barcelona, Spain, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» BioViz: An Interactive Visualization Engine for Digital Microfluidic Biochips




Author:

Jannis Stoppe, Oliver Keszöcze, Maximilian Luenert, Robert Wille, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Bochum, Germany, 2017
Hyperlink:

[To the Site of this Conference]



» Towards VHDL-based Design of Reversible Circuits




Author:

Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Kolkata, India, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» An Adaptive Prioritized ε-Preferred Evolutionary Algorithm for Approximate BDD Optimization




Author:

Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
Conference:
Genetic and Evolutionary Computation Conference (GECCO)
Reference:

Berlin, Germany, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» ProACt: A Processor for High Performance On-demand Approximate Computing




Author:

Arun Chandrasekharan, Daniel Große, Rolf Drechsler
Conference:
27th ACM Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

Banff, Alberta, Canada, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» OR-Inverter Graphs for the Synthesis of Optical Circuits




Author:

Arighna Deb, Robert Wille, Rolf Drechsler
Conference:
47th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Novi Sad, Serbia, 2017
Hyperlink:

[To the Site of this Conference]



» Extensions to the Reversible Hardware Description Language SyReC




Author:

Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Conference:
47th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Novi Sad, Serbia, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Error Bounded Exact BDD Minimization in Approximate Computing




Author:

Saman Froehlich, Daniel Große, Rolf Drechsler
Conference:
47th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Novi Sad, Serbia, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exact Synthesis of Ternary Reversible Functions using Ternary Toffoli Gates




Author:

Abhoy Kole, P. Mercy Nesa Rani, Kamalika Datta, Indranil Sengupta, Rolf Drechsler
Conference:
47th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Novi Sad, Serbia, 2017
Hyperlink:

[To the Site of this Conference]



» Effects of Cell Shapes on the Routability of Digital Microfluidic Biochips




Author:

Kevin Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Automatic Equivalence Checking for SystemC-TLM 2.0 Models Against their Formal Specifications




Author:

Mehran Goli, Jannis Stoppe, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Data Flow Testing for Virtual Prototypes




Author:

Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Endurance Management for Resistive Logic-In-Memory Computing Architectures




Author:

Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Optimization of Retargeting for IEEE 1149.1 TAP Controllers with Embedded Compression




Author:

Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Lausanne, Schweiz, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Trust is good, Control is better: Hardware-based Instruction-Replacement for Reliable Processor-IPs




Author:

Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, Rolf Drechsler
Conference:
22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Chiba/Tokyo, Japan, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Enhancing Robustness of Sequential Circuits Using Application-specific Knowledge and Formal Methods




Author:

Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler
Conference:
22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Chiba/Tokyo, Japan, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exact Routing for Micro-Electrode-Dot-Array Digital Microfluidic Biochips




Author:

Oliver Keszöcze, Zipeng Li, Andreas Grimmer, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
Conference:
22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Chiba/Tokyo, Japan, 2017
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exploring Superior Structural Materials Using Multi-Objective Optimization and Formal Techniques




Author:

Rolf Drechsler, Stephan Eggersglüß, Nils Ellendt, Sebastian Huhn, Lutz Mädler
Conference:
6th IEEE International Symposium on Embedded Computing & System Design (ISED)
Reference:

Indian Institute of Technology, Patna, India, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Clocks vs. Instants Relations: Verifying CCSL Time Constraints in UML/MARTE Models




Author:

Judith Peters, Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Reference:

Indian Institute of Technology, Kanpur, India, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Frame Conditions in Symbolic Representations of UML/OCL Models




Author:

Nils Przigoda, Jonas Gomes Filho, Philipp Niemann, Robert Wille, Rolf Drechsler
Conference:
14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Reference:

Indian Institute of Technology, Kanpur, India, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Guided Lightweight Software Test Qualification for IP Integration using Virtual Prototypes




Author:

Daniel Große, Hoang M. Le, Muhammad Hassan, Rolf Drechsler
Conference:
IEEE International Conference on Computer Design (ICCD)
Reference:

Phoenix, USA, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» AIBA: an Automated Intra-Cycle Behavioral Analysis for SystemC-based Design Exploration




Author:

Mehran Goli, Jannis Stoppe, Rolf Drechsler
Conference:
IEEE International Conference on Computer Design (ICCD)
Reference:

Phoenix, USA, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Generating and Checking Control Logic in the HDL-based Design of Reversible Circuits




Author:

Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
Conference:
International Symposium on Electronic System Design (ISED)
Reference:

Patna, Indien, 2016
Hyperlink:

[To the Site of this Conference]



» An Improved Gate Library for Logic Synthesis of Optical Circuits




Author:

Shuchisman Burman, Kamalika Datta, Robert Wille, Indranil Sengupta, Rolf Drechsler
Conference:
International Symposium on Electronic System Design (ISED)
Reference:

Patna, Indien, 2016
Hyperlink:

[To the Site of this Conference]



» Towards a Model-Based Verification Methodology for Complex Swarm Systems




Author:

Jonas Gomes Filho, Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
International Symposium on Electronic System Design (ISED)
Reference:

Patna, Indien, 2016
Hyperlink:

[To the Site of this Conference]



» Ground Setting Properties for an Efficient Translation of OCL in SMT-based Model Finding




Author:

Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
ACM/IEEE 19th International Conference on Model Driven Engineering Languages and Systems (MoDELS)
Reference:

Saint Malo, Brittany, France, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Equivalence Checking Using Gröbner Bases




Author:

Amr Sayed Ahmed, Daniel Große, Mathias Soeken, Rolf Drechsler
Conference:
Formal Methods in Computer Aided Design (FMCAD)
Reference:

Mountain View, USA, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-based Error Effect Simulation - A Case Study




Author:

Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Bremen, Germany, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Approximation-aware Rewriting of AIGs for Error Tolerant Applications




Author:

Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

Austin, USA, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Compiled Symbolic Simulation for SystemC




Author:

Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

Austin, USA, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs




Author:

Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Bologna, Italy, 2016
Hyperlink:

[To the Site of this Conference]



» ParCoSS: Efficient Parallelized Compiled Symbolic Simulation




Author:

Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
International Conference on Computer Aided Verification (CAV)
Reference:

Toronto, Canada, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm




Author:

Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
Conference:
Genetic and Evolutionary Computation Conference (GECCO)
Reference:

Denver, USA, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» An MIG-based Compiler for Programmable Logic-in-Memory Architectures




Author:

Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli
Conference:
Design Automation Conference (DAC)
Reference:

Austin, USA, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Precise Error Determination of Approximated Components in Sequential Circuits with Model Checking




Author:

Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

Austin, USA, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Multi-Objective BDD Optimization for RRAM based Circuit Design




Author:

Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler
Conference:
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'16)
Reference:

Košice, Slovakia, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers




Author:

Sebastian Huhn, Stephan Eggersglüß and Rolf Drechsler
Conference:
IEEE European Test Symposium (ETS)
Reference:

Amsterdam, Niederlande, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Fault Detection in Parity Preserving Reversible Circuits




Author:

Nils Przigoda, Gerhard Dueck, Robert Wille, Rolf Drechsler
Conference:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Sapporo, Japan, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Re-writing HDL Descriptions for Line-aware Synthesis of Reversible Circuits




Author:

Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Conference:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Sapporo, Japan, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation




Author:

Laxmidhar Biswal, Chandan Bandyopadhyay, Anupam Chattopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Conference:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Sapporo, Japan, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Technology mapping of reversible circuits to Clifford+T quantum circuits




Author:

Nabila Abdessaied, Matthew Amy, Mathias Soeken, Rolf Drechsler
Conference:
46rd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Sapporo, Japan, 2016
Hyperlink:

[To the Site of this Conference]



» Quantitative Timing Analysis of UML Activity Diagrams Using Statistical Model Checking




Author:

Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 780-785, Dresden, Germany, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Towards Formal Verification of Real-World SystemC TLM Peripheral Models - A Case Study




Author:

Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1160-1163, Dresden, Germany, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Formal Verification of Integer Multipliers by Combining Gröbner Basis with Logic Reduction




Author:

Amr Sayed Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1048-1053, Dresden, Germany, 2016
Best Paper Candidate
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Fast Logic Synthesis for RRAM-based In-Memory Computing using Majority-Inverter Graphs




Author:

Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Dresden, Germany, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Look-ahead Schemes for Nearest Neighbor Optimization of 1D and 2D Quantum Circuits




Author:

Robert Wille, Oliver Keszöcze, Marcel Walter, Patrick Rohrs, Anupam Chattopadhyay, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Macao, China, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» BDD Minimization for Approximate Computing




Author:

Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 474-479, Macao, China, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library




Author:

Laxmidhar Biswal, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Conference:
International Conference on VLSI Design (VLSI Design)
Reference:

Kolkata, India, 2016
Hyperlink:

[To the Site of this Conference]



» Hardware/Software Co-Visualization on the Electronic System Level using SystemC




Author:

Rolf Drechsler, Jannis Stoppe
Conference:
International Conference on VLSI Design
Reference:

Kolkata, India, 2016
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Ensuring Safety and Reliability of IP-based System Design – A Container Approach




Author:

Arun Chandrasekharan, Kenneth Schmitz, Ulrich Kühne, Rolf Drechsler
Conference:
IEEE International Symposium on Rapid System Protoyping (RSP), 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Reversible Computation: An Alternative Computation Paradigm for Low Power Applications




Author:

Rolf Drechsler, Robert Wille
Conference:
International Green and Sustainable Computing Conference (IGSC)
Reference:

Las Vegas, USA, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Checking Concurrent Behavior in UML/OCL Models




Author:

Nils Przigoda, Christoph Hilken, Robert Wille, Jan Peleska, Rolf Drechsler
Conference:
ACM/IEEE 18th International Conference on Model Driven Engineering Languages and Systems (MoDELS)
Reference:

Ottawa, Kanada, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven Generation




Author:

Hoang M. Le, Rolf Drechsler
Conference:
Design and Verification Conference and Exhibition Europe (DVCon Europe)
Reference:

Munich, Germany, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Reverse Engineering with Simulation Graphs




Author:

Mathias Soeken, Baruch Sterin, Rolf Drechsler, Robert K. Brayton
Conference:
Formal Methods in Computer Aided Design (FMCAD)
Reference:

Austin, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Reversible Circuit Rewriting with Simulated Annealing




Author:

Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, and Rolf Drechsler
Conference:
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Reference:

Daejeon, Korea, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Lazy-CSeq-SP: Boosting Sequentialization-based Verification of Multi-Threaded C Programs via Symbolic Pruning of Redundant Schedules




Author:

Vladimir Herdt, Hoang M. Le, Daniel Große and Rolf Drechsler
Conference:
Automated Technology for Verification and Analysis (ATVA)
Reference:

pp. 228-233, Shanghai, China, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» A General and Exact Routing Methodology for Digital Microfluidic Biochips




Author:

Oliver Keszöcze, Robert Wille, Krishnendu Chakrabarty Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

Austin, USA, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Formal Methods for Emerging Technologies




Author:

Robert Wille, Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

Austin, USA, 2015
Hyperlink:

[To the Site of this Conference]



» Leveraging the Analysis for Invariant Independence in Formal System Models




Author:

Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Funchal, Madeira, Portugal, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Verification-driven Design Across Abstraction Levels - A Case Study




Author:

Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Funchal, Madeira, Portugal, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Envisioning Self-Verification of Electronic Systems




Author:

Rolf Drechsler, Martin Fränzle, Robert Wille
Conference:
Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
Reference:

Bremen, Germany, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits




Author:

Amr Sayed Ahmed, Ulrich Kühne, Daniel Große, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2015).
Reference:

pp. 1-6, Montpellier, France, 2015.
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Coverage of OCL Operation Specifications and Invariants




Author:

Mathias Soeken, Julia Seiter, Rolf Drechsler
Conference:
9th International Conference on Tests & Proofs (TAP)
Reference:

L’Aquila, Italy, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Towards Line-aware Realizations of Expressions for HDL-based Synthesis of Reversible Circuits




Author:

Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Grenoble, France, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Technology mapping for quantum circuits using Boolean functional decomposition




Author:

Nabila Abdessaied, Mathias Soeken, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Grenoble, France, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Multi-Objective BDD Optimization with Evolutionary Algorithms




Author:

Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler
Conference:
Genetic and Evolutionary Computation Conference (GECCO)
Reference:

Madrid, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Contradiction Analysis for Inconsistent Formal Models




Author:

Nils Przigoda, Robert Wille, Rolf Drechsler
Conference:
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15)
Reference:

Belgrade, Serbia, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Requirement Phrasing Assistance using Automatic Quality Assessment




Author:

Arman Allahyari-Abhari, Mathias Soeken, Rolf Drechsler
Conference:
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15)
Reference:

Belgrade, Serbia, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» A Generic Representation of CCSL Time Constraints for UML/MARTE Models




Author:

Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

San Francisco, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Verifying SystemC using Stateful Symbolic Simulation




Author:

Vladimir Herdt, Hoang M. Le, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

San Francisco, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization




Author:

Arighna Deb, Robert Wille, Rolf Drechsler, Debesh Das
Conference:
45th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Waterloo, Canada, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» An Examination of the NCV-v1 Quantum Library Based on Minimal Circuits




Author:

Arman Allahyari-Abhari, Robert Wille, Rolf Drechsler
Conference:
45th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Waterloo, Canada, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Automated Feature Localization for Dynamically Generated SystemC Designs




Author:

Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE'15)
Reference:

Grenoble, France, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» BDD-based Synthesis for All-optical Mach-Zehnder Interferometer Circuits




Author:

Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Conference:
International Conference on VLSI Design (VLSI Design)
Reference:

Bengaluru, India, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Determining the Minimal Number of SWAP Gates for Multi-dimensional Nearest Neighbor Quantum Circuits




Author:

Aaron Lye, Robert Wille, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Chiba/Tokyo, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Reverse BDD-based Synthesis for Splitter-free Optical Circuits




Author:

Robert Wille, Oliver Keszöcze, Clemens Hopfmuller, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

Chiba/Tokyo, 2015
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Safe IP Integration Using Container Modules




Author:

Rolf Drechsler, Ulrich Kühne
Conference:
International Symposium on Electronic System Design (ISED)
Reference:

Mangalore, India, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exact Routing for Digital Microfluidic Biochips with Temporary Blockages




Author:

Oliver Keszöcze, Robert Wille, Rolf Drechsler
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

San Jose, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Automated and Quality-driven Requirements Engineering




Author:

Rolf Drechsler, Mathias Soeken, Robert Wille,
Conference:
International Conference on Computer Aided Design (ICCAD)
Reference:

San Jose, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemC




Author:

Hoang M. Le, Rolf Drechsler
Conference:
Design and Verification Conference and Exhibition Europe (DVCon Europe)
Reference:

Munich, Germany, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» metaSMT: A Unified Interface to SMT-LIB2




Author:

Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL'14)
Reference:

pp. 1-6, Munich, Germany, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Automating the Translation of Assertions Using Natural Language Processing Techniques




Author:

Mathias Soeken, Christopher B. Harris, Nabila Abdessaied, Ian G. Harris and Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Munich, Germany, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Automatic Refinement Checking for Formal System Models




Author:

Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Munich, Germany, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Verifying Consistency between Activity Diagrams and Their Corresponding OCL Contracts




Author:

Christoph Hilken, Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Munich, Germany, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Quality Assessment for Requirements based on Natural Language Processing




Author:

Mathias Soeken, Nabila Abdessaied, Arman Allahyari-Abhari, Andi Buzo, Liana Musat, Georg Pelz, Rolf Drechsler
Conference:
Special Session at the Forum on Specification & Design Languages (FDL'14)
Reference:

Munich, Germany, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Improving Coverage of Simulation-based Verification by Dedicated Stimuli Generation




Author:

Shuo Yang, Robert Wille, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

pp. 599-606, Verona, Italy, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Determining Cases of Scenarios to Improve Coverage in Simulation-based Verication




Author:

Shuo Yang, Robert Wille, Rolf Drechsler
Conference:
Symposium on Integrated Circuits and System Design (SBCCI)
Reference:

Aracaju, Brazil, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Validating SystemC Implementations Against Their Formal Specifications




Author:

Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference:
Symposium on Integrated Circuits and System Design (SBCCI)
Reference:

Aracaju, Brazil, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Self-Verification as the Key Technology for Next Generation Electronic Systems




Author:

Rolf Drechsler, Hoang M. Le, Mathias Soeken
Conference:
Symposium on Integrated Circuits and System Design (SBCCI)
Reference:

Aracaju, Brazil, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Recent Advances in SAT-based ATPG: Non-Standard Fault Models, Multi Constraints and Optimization




Author:

Bernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer
Conference:
International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
Reference:

pp. 1-10, Santorini, Greece, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Behaviour Driven Development for Tests and Verification




Author:

Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
Conference:
8th International Conference on Tests & Proofs (TAP)
Reference:

pp. 61-77, York, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Generating SystemC Implementations for Clock Constraints specified in UML/MARTE CCSL




Author:

Judith Peters, Robert Wille, Rolf Drechsler
Conference:
International Conference on Engineering of Complex Computer Systems (ICECCS)
Reference:

pp. 116-125, Tianjin, China, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exact One-pass Synthesis of Digital Microfluidic Biochips




Author:

Oliver Keszöcze, Robert Wille, Tsung-Yi Ho, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

San Francisco, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State-of-the-Art and Research Challenges




Author:

Jan-Hendrik Oetjens, Nico Bannow, Markus Becker, Oliver Bringmann, Andreas Burger, Moomen Chaari, Samarjit Chakraborty, Rolf Drechsler, Wolfgang Ecker, Kim Gruettner, Thomas Kruse, Christoph Kuznik, Hoang M. Le, Andreas Mauderer, Wolfgang Mueller, Daniel Mueller-Gritschneder, Frank Poppen, Hendrik Post, Sebastian Reiter, Wolfgang Rosenstiel, Simon Roth, Ulf Schlichtmann, Andreas von Schwerin, Bogdan-Andrei Tabacaru, Alexander Viehl
Conference:
Design Automation Conference (DAC)
Reference:

pp. 113:1-6, San Francisco, 2014
Hyperlink:

[To the Site of this Conference]



» Mapping NCV Circuits to Optimized Clifford+T Circuits




Author:

D. Michael Miller, Mathias Soeken, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Kyoto, Japan, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Equivalence Checking in Multi-level Quantum Systems




Author:

Philipp Niemann, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 201-215, Kyoto, Japan, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» RevVis: Visualization of Structures and Properties in Reversible Circuits




Author:

Robert Wille, Jannis Stoppe, Eleonora Schönborn, Kamalika Datta, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Kyoto, Japan, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Quantum Circuit Optimization by Hadamard Gate Reduction




Author:

Nabila Abdessaied, Mathias Soeken, Rolf Drechsler
Conference:
Reversible Computation
Reference:

Kyoto, Japan, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Optimizing DD-based Synthesis of Reversible Circuits using Negative Control Lines




Author:

Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Conference:
IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 129-134, Warschau, Polen, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Optimization-based Multiple Target Test Generation for Highly Compacted Test Sets




Author:

Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
Conference:
19th IEEE European Test Symposium (ETS)
Reference:

Paderborn, Germany, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» A Cube Pairing Approach for Synthesis of ESOP based Reversible Circuit




Author:

Chandan Bandyopadhyay, Hafizur Rahaman, Rolf Drechsler
Conference:
44rd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

Bremen, 2014
Hyperlink:

[To the Site of this Conference]



» Future SoC Verification Methodology: UVM Evolution or Revolution?




Author:

Rolf Drechsler, Christophe Chevallaz, Franco Fummi, Alan Hu, Ronny Morad, Frank Schirrmeister, Alex Goryachev
Conference:
Design, Automation and Test in Europe (DATE'14)
Reference:

Dresden, Germany, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Towards Verifying Determinism of SystemC Designs




Author:

Hoang M. Le, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE'14)
Reference:

pp. 153:1-4, Dresden, Germany, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Grammar-based Program Generation Based on Model Finding




Author:

Mathias Soeken, Rolf Drechsler
Conference:
IEEE Design and Test Symposium 2013 (IDT)
Reference:

Marrakesch, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Optimal SWAP Gate Insertion for Nearest Neighbor Quantum Circuits




Author:

Robert Wille, Aaron Lye, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 489-494, Singapore, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Efficient Synthesis of Quantum Circuits Implementing Clifford Group Operations




Author:

Philipp Niemann, Robert Wille, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 483-488, Singapore, 2014
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Improved SAT-based ATPG: More Constraints, Better Compaction




Author:

Stephan Eggersglüß, Robert Wille, Rolf Drechsler
Conference:
IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
Reference:

pp. 85-90, San Jose, USA, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» A Compact and Efficient SAT Encoding for Quantum Circuits




Author:

Robert Wille, Nils Przigoda, Rolf Drechsler
Conference:
IEEE Africon
Reference:

Mauritius, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exploiting Reversibility in the Complete Simulation of Reversible Circuits




Author:

Robert Wille, Simon Stelter, Rolf Drechsler
Conference:
IEEE Africon
Reference:

Mauritius, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Cone of Influence Analysis at the Electronic System Level Using Machine Learning




Author:

Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Santander, Spain, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Minimal Stimuli Generation in Simulation-based Verification




Author:

Shuo Yang, Robert Wille, Daniel Große and Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

Santander, Spain, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» The SyReC Hardware Description Language: Enabling Scalable Synthesis of Reversible Circuits




Author:

Robert Wille, Rolf Drechsler
Conference:
International Midwest Symposium on Circuits and Systems (MWSCAS)
Reference:

Columbus, USA, 2013
Hyperlink:

[To the Site of this Conference]



» Incorporating User Preferences in Many-Objective Optimization using Relation Epsilon-Preferred




Author:

Nicole Drechsler, André Sülflow, Rolf Drechsler
Conference:
International Conference on Evolutionary Computation Theory and Applications (ECTA)
Reference:

Vilamoura, Portugal, 2013
Hyperlink:

[To the Site of this Conference]



» Data Extraction from SystemC Designs using Debug Symbols and the SystemC API




Author:

Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

Natal, Brazil, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» On the “Q” in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-structure




Author:

Philipp Niemann, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 125-140, Victoria, Canada, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exploiting Negative Control Lines in the Optimization of Reversible Circuits




Author:

Kamalika Datta, Gaurav Rathi, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 209-220, Victoria, Canada, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure




Author:

Arighna Deb, Debesh Kumar Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 182-195, Victoria, Canada, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Reducing the Depth of Quantum Circuits Using Additional Lines




Author:

Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler
Conference:
Reversible Computation
Reference:

pp. 221-233, Victoria, Canada, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Hardware-Software Co-Visualization: Developing Systems in the Holodeck




Author:

Rolf Drechsler, Mathias Soeken
Conference:
16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 1-4, Karlovy Vary, Czech Republic, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Verifying SystemC using an Intermediate Verification Language and Symbolic Simulation




Author:

Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

pp. 116:1-6 Austin, Texas, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits




Author:

Robert Wille, Hongyan Zhang, Rolf Drechsler
Conference:
43rd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 29-34, Toyama, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Debugging of Reversible Circuits using πDDs




Author:

Laura Tague, Mathias Soeken, Shin-ichi Minato, Rolf Drechsler
Conference:
43rd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 316-321, Toyama, Japan, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exact Template Matching Using Boolean Satisfiability




Author:

Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler
Conference:
43rd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 328-333, Toyama, Japan, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Synchronized Debugging across Different Abstraction Levels in System Design




Author:

Rolf Drechsler, Daniel Große, Hoang M. Le, André Sülflow
Conference:
embedded world Conference 2013
Reference:

Nürnberg, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Scalable Fault Localization for SystemC TLM Designs




Author:

Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE'13)
Reference:

pp. 35-38, Grenoble, France, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Determining Relevant Model Elements for the Verification of UML/OCL Specifications




Author:

Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1189-1192, Grenoble, France, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Towards a Generic Verification Methodology for System Models




Author:

Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1193-1196, Grenoble, France, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Improving the Mapping of Reversible Circuits to Quantum Circuits Using Multiple Target Lines




Author:

Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 145-150. Yokohama, Japan, 2013
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» An Evolutionary Approach to Reversible Logic Synthesis using Output Permutation




Author:

Kamalika Datta, Indranil Sen Gupta, Hafizur Rahaman, Rolf Drechsler
Conference:
IEEE Design and Test Symposium 2012 (IDT)
Reference:

Doha, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Towards Dialog Systems for Assisted Natural Language Processing in the Design of Embedded Systems




Author:

Rolf Drechsler, Mathias Soeken, Robert Wille
Conference:
IEEE Design and Test Symposium 2012 (IDT)
Reference:

Doha, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Synthesis of Reversible Circuits Using Decision Diagrams




Author:

Rolf Drechsler, Robert Wille
Conference:
International Symposium on Electronic System Design (ISED)
Reference:

pp. 1-5, Kolkata, WB, India, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» SyDe - a New Graduate School for System Design in an Excellent Setting




Author:

Ulrich Kühne, Rolf Drechsler
Conference:
Informatics Europe (ECSS)
Reference:

Barcelona, 2012
Hyperlink:

[To the Site of this Conference]



» From Requirements and Scenarios to ESL Design in SystemC




Author:

Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
International Symposium on Electronic System Design (ISED)
Reference:

pp. 183-187, Kolkata, WB, India, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» FoREnSiC - An Automatic Debugging Environment for C Programs




Author:

Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow
Conference:
Haifa Verification Conference (HVC)
Reference:

Haifa, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» The System Verification Methodology for Advanced TLM Verification




Author:

Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler, Wolfgang Ecker, Volkan Esen
Conference:
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
Reference:

pp. 313-322, Tampere, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Complete and Effective Robustness Checking by Means of Interpolation




Author:

Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav and Rolf Drechsler
Conference:
Formal Methods in Computer-Aided Design (FMCAD'12)
Reference:

Cambridge, UK, 2012, page 82-90
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Completeness-Driven Development




Author:

Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille
Conference:
International Conference on Graph Transformation
Reference:

pp. 38-50, Bremen, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC




Author:

Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
International Symposium on System-on-Chip (SoC)
Reference:

pp. 1-7, Tampere, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Localizing Features of ESL Models for Design Understanding




Author:

Marc Michael, Daniel Große, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Vienna, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Formal Specification Level: Towards Verification-driven Design Based on Natural Language Processing




Author:

Rolf Drechsler, Mathias Soeken, Robert Wille
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 53-58, Vienna, Austria, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Circuit Line Minimization in the HDL-based Synthesis of Reversible Logic




Author:

Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

pp. 213-218, Amherst, USA, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Coverage-driven Stimuli Generation




Author:

Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler
Conference:
15th Euromicro Conference on Digital System Design (DSD)
Reference:

Izmir, Turkey, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology




Author:

Rolf Drechsler, Robert Wille
Conference:
International Symposium on VLSI Design and Test (VDAT)
Reference:

Shibpur, India, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Assisted Behavior Driven Development Using Natural Language Processing




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference:
50th International Conference on Objects, Models, Components, Patterns (TOOLS)
Reference:

pp. 269-287, Prague, Czech Republic, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» A New SAT-based ATPG for Generating Highly Compacted Test Sets




Author:

Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler
Conference:
15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 230-235, Tallinn, Estonia, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits




Author:

Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler
Conference:
42nd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 173-178, Victoria, Canada, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» A Synthesis Flow for Sequential Reversible Circuits




Author:

Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler
Conference:
42nd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 299-304, Victoria, Canada, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines




Author:

Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler
Conference:
42nd International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 69-74, Victoria, Canada, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis




Author:

Robert Wille, Rolf Drechsler, Christof Oswald, Alberto Garcia-Ortiz
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Dresden, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» A Guiding Coverage Metric for Formal Verification




Author:

Finn Haedicke, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

Dresden, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Eliminating Invariants in UML/OCL Models




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1142-1145, Dresden, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Debugging of Inconsistent UML/OCL Models




Author:

Robert Wille, Mathias Soeken, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1078-1083, Dresden, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Synthesis of Reversible Circuits with Minimal Lines for Large Functions




Author:

Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference:

pp. 85-92, Sydney, 2012
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Improved Fault Diagnosis for Reversible Circuits




Author:

Hongyan Zhang, Robert Wille, Rolf Drechsler
Conference:
Asian Test Symposium (ATS)
Reference:

New Delhi, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Hochoptimierter Ablauf zur Robustheitsprüfung




Author:

Stefan Frehse, Finn Haedicke, Melanie Diepenbeck, Görschwin Fey, Rolf Drechsler
Conference:
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)
Reference:

Hamburg-Harburg, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Analyzing Dependability Measures at the Electronic System Level




Author:

Marc Michael, Daniel Große, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 1-8, Oldenburg, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Efficient Realization of Control Logic in Reversible Circuits




Author:

Sebastian Offermann, Robert Wille, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

Oldenburg, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Determining Minimal Testsets for Reversible Circuits Using Boolean Satisfiability




Author:

Hongyan Zhang, Stefan Frehse, Robert Wille, Rolf Drechsler
Conference:
10th IEEE Africon
Reference:

Livingstone, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» VisSAT: Visualization of SAT Solver Internals for Computer Aided Hardware Verification




Author:

Robert Wille, André Sülflow, Rolf Drechsler
Conference:
International Conference on Modeling, Simulation and Visualization Methods (MSV)
Reference:

pp. 36-39, Las Vegas, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization




Author:

Robert Wille, Hongyan Zhang, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

pp. 120-125, Chennai, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Encoding OCL Data Types for SAT-based Verification of UML/OCL Models




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference:
5th International Conference on Tests & Proofs (TAP)
Reference:

pp. 152-170, Zurich, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Automatic Property Generation for the Formal Verification of Bus Bridges




Author:

Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
Conference:
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 417-422, Cottbus, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» TLM Protocol Compliance Checking at the Electronic System Level




Author:

Mohamed Bawadekji, Daniel Große, Rolf Drechsler
Conference:
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 435-440, Cottbus, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Designing a RISC CPU in Reversible Logic




Author:

Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
Conference:
41st International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 170-175, Tuusula, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits




Author:

Rolf Drechsler, Robert Wille
Conference:
41st International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 78-85, Tuusula, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Simulation-based Equivalence Checking between SystemC Models at different Levels of Abstraction




Author:

Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 223-228, Lausanne, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Verifying Dynamic Aspects of UML Models




Author:

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1077-1082, Grenoble, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Determining the Minimal Number of Lines for Large Reversible Circuits




Author:

Robert Wille, Oliver Keszöcze, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1204—1207, Grenoble, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization




Author:

Stephan Eggersglüß, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1291-1296, Grenoble, 2011
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Automatic Fault Localization for Programmable Logic Controllers




Author:

Andre Sülflow, Rolf Drechsler
Conference:
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT)
Reference:

pp. 247-256, Braunschweig, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Robust Algorithms for High Quality Test Pattern Generation Using Boolean Satisfiability




Author:

Stephan Eggersglüß, Rolf Drechsler
Conference:
International Test Conference (ITC)
Reference:

pp. 1-10, Austin, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Polynomial Datapath Optimization using Constraint Solving and Formal Modelling




Author:

Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler
Conference:
IEEE/ACM International Conference on Computer Aided Design (ICCAD)
Reference:

San Jose, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» SyReC: A Programming Language for Synthesis of Reversible Circuits




Author:

Robert Wille, Sebastian Offermann, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 184-189, Southampton, 2010
Received Best Paper Award
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Proving Transaction and System-level Properties of Untimed SystemC TLM Designs




Author:

Daniel Große, Hoang M. Le, Rolf Drechsler
Conference:
International Conference on Formal Methods and Models for Codesign (MEMOCODE)
Reference:

pp. 113-122, Grenoble, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» RobuCheck: A Robustness Checker for Digital Circuits




Author:

Stefan Frehse, Görschwin Fey, Andre Sülflow and Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

pp. 226-231, Lille, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Reducing the Number of Lines in Reversible Circuits




Author:

Robert Wille, Mathias Soeken, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

pp. 647-652, Anaheim, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Synthesizing Multiplier in Reversible Logic




Author:

Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Conference:
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 335-340, Vienna, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Window Optimization of Reversible and Quantum Circuits




Author:

Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Conference:
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 431-435, Vienna, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» A Better-Than-Worst-Case Robustness Measure




Author:

Stefan Frehse, Görschwin Fey, Rolf Drechsler
Conference:
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference:

pp. 78-83, Vienna, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Enhancing Debugging of Multiple Missing Control Errors in Reversible Logic




Author:

Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 465-470, Rhode Island, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Improving CNF Representations in SAT-based ATPG for Industrial Circuits using BDDs




Author:

Daniel Tille, Stephan Eggersglüß, René Krenz-Bååth, Juergen Schloeffel, Rolf Drechsler
Conference:
15th IEEE European Test Symposium (ETS)
Reference:

pp. 176-181, Prag, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions




Author:

Alexander Finder, Rolf Drechsler
Conference:
40th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 150-155, Barcelona, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Efficient Simulation-based Debugging of Reversible Logic




Author:

Stefan Frehse, Robert Wille, Rolf Drechsler
Conference:
40th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 156-161, Barcelona, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Reducing Reversible Circuit Cost by Adding Lines




Author:

D. Michael Miller, Robert Wille, Rolf Drechsler
Conference:
40th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 217-222, Barcelona, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Efficient Test Generation with Maximal Crosstalk-Induced Noise using Unconstrained Aggressor Excitation




Author:

Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS)
Reference:

pp. 649-652, Paris, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Using QBF to Increase Accuracy of SAT-Based Debugging




Author:

Andre Sülflow, Görschwin Fey, Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS)
Reference:

pp.641-644, Paris, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Verifying UML/OCL Models Using Boolean Satisfiability




Author:

Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1341-1344, Dresden, 2010
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Timing Arc Based Logic Analysis for False Noise Reduction




Author:

Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler
Conference:
IEEE/ACM International Conference on Computer Aided Design (ICCAD)
Reference:

pp. 225-230, San Jose, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Anwendungsbezogene Analyse der Robustheit von Digitalen Schaltungen




Author:

Andre Sülflow, Stefan Frehse, Görschwin Fey, Rolf Drechsler
Conference:
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)
Reference:

pp. 45-52, Stuttgart, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Structural Heuristics for SAT-based ATPG




Author:

Daniel Tille, Stephan Eggersglüß, Hoang M. Le, Rolf Drechsler
Conference:
17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2009)
Reference:

pp. 77-82, Florianópolis, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Speeding up SAT-based ATPG using Dynamic Clause Activation




Author:

Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Conference:
18th Asian Test Symposium (ATS'09)
Reference:

pp. 177-182, Taichung, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Automatic Debugging of System-on-a-Chip Designs




Author:

Frank Rogin, Rolf Drechsler, Steffen Rülke
Conference:
IEEE International SOC Conference (SOCC)
Reference:

Belfast, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» SMT-based Stimuli Generation in the SystemC Verification Library




Author:

Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 1-6, Sophia Antipolis, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Robustness Check for Multiple Faults using Formal Techniques




Author:

Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

pp. 85-90, Patras, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» BDD-based Synthesis of Reversible Logic for Large Functions




Author:

Robert Wille, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

pp. 270-275, San Francisco, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Computing Bounds for Fault Tolerance using Formal Techniques




Author:

Görschwin Fey, Andre Sülflow, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Reference:

pp. 190-195, San Francisco, USA, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» WoLFram - A Word Level Framework for Formal Verification




Author:

Andre Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler
Conference:
IEEE/IFIP International Symposium on Rapid System Prototyping (RSP)
Reference:

pp. 11-17, Paris, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» A Fast Untestability Proof for SAT-based ATPG




Author:

Daniel Tille, Rolf Drechsler
Conference:
12th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
Reference:

pp. 38-43, Liberec, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Increasing Robustness of SAT-based Delay Test Generation using Efficient Dynamic Learning Techniques




Author:

Stephan Eggersglüß, Rolf Drechsler
Conference:
14th IEEE European Test Symposium (ETS)
Reference:

pp. 81-86, Sevilla, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Contradictory Antecedent Debugging in Bounded Model Checking




Author:

Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 173-176, Boston, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Evaluation of Cardinality Constraints on SMT-based Debugging




Author:

Andre Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler
Conference:
39th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 298-303, Naha, Okinawa, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Equivalence Checking of Reversible Circuits




Author:

Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
Conference:
39th International Symposium on Multiple-Valued Logic (ISMVL)
Reference:

pp. 324-330, Naha, Okinawa, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Approximate BDD Minimization by Weighted A*




Author:

Rüdiger Ebendt, Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'09)
Reference:

Taipei, 2009
Hyperlink:

[To the Site of this Conference]



» Overcoming Limitations of the SystemC Data Introspection




Author:

Christian Genz, Rolf Drechsler
Conference:
Design Automation and Test in Europe (DATE)
Reference:

pp. 590-593, Nice, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Property Analysis and Design Understanding




Author:

Ulrich Kühne, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1246-1249, Nice, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Debugging of Toffoli Networks




Author:

Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1284-1289, Nice, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Increasing the Accuracy of SAT-based Debugging




Author:

Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1326-1332, Nice, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Reversible Logic Synthesis with Output Permutation




Author:

Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler
Conference:
22nd International Conference on VLSI Design
Reference:

pp. 189-194, New Delhi, 2009
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Formaler Nachweis der Fehlertoleranz von Schaltkreisen




Author:

Görschwin Fey, Andre Sülflow, Stefan Frehse, Ulrich Kühne, Rolf Drechsler
Conference:
GMM/GI/ITG-Fachtagung: Zuverlässigkeit und Entwurf (ZuE 2008)
Reference:

pp. 75-82, Ingolstadt, 2008
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Verification of PLC Programs using Formal Proof Techniques




Author:

Andre Sülflow, Rolf Drechsler
Conference:
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008)
Reference:

pp. 43-50, Budapest, 2008
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Efficient Formal Verification of Track Vacancy Detection Sections




Author:

Sebastian Kinder und Rolf Drechsler
Conference:
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008)
Reference:

pp. 233-240, Budapest, 2008
Hyperlink:

[To the Site of this Conference]



» Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking




Author:

Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Reference:

pp. 542-549, Parma, 2008
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Contradiction Analysis for Constraint-based Random Simulation




Author:

Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 130-135, Stuttgart, 2008
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability




Author:

Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

pp. 411-416, Montpellier, 2008
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» RevLib: An Online Resource for Reversible Functions and Reversible Circuits




Author:

Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler
Conference:
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Reference:

pp. 220-225, Dallas, 2008
RevLib is available at www.revlib.org
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don’t Cares




Author:

Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Conference:
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Reference:

pp. 214-219, Dallas, 2008
Received IEEE Young Researcher Award
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» On the Influence of Boolean Encodings in SAT-based ATPG for Path Delay Faults




Author:

Stephan Eggersglüß, Rolf Drechsler
Conference:
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Reference:

pp. 94-99, Dallas, 2008
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Using Unsatisfiable Cores to Debug Multiple Design Errors




Author:

Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler
Conference:
IEEE Great Lakes Symposium on VLSI (GLSVLSI'08)
Reference:

pp. 77-82, Orlando, 2008
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Process Variations Aware Robust on-Chip Bus Architecture Synthesis for MPSoCs




Author:

Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'08)
Reference:

Seattle, 2008
Hyperlink:

[To the Site of this Conference]



» A Basis for Formal Robustness Checking




Author:

Görschwin Fey, Rolf Drechsler
Conference:
International Symposium on Quality of Electronic Design (ISQED)
Reference:

San Jose, 2008
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Adaptive Branch and Bound using SAT to Estimate False Crosstalk




Author:

Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler
Conference:
International Symposium on Quality of Electronic Design (ISQED)
Reference:

San Jose, 2008
Hyperlink:

[To the Site of this Conference]



» Automatic Generation of Complex Properties for Hardware Designs




Author:

Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler Steffen Rülke
Conference:
Design, Automation, and Test in Europe (DATE)
Reference:

Munich, 2008
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs




Author:

Sujan Pandey, Rolf Drechsler
Conference:
Design, Automation, and Test in Europe (DATE)
Reference:

Munich, 2008
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Robust On-Chip Bus architecture Synthesis for MPSoCs Under Random Tasks Arrival




Author:

Sujan Pandey, Rolf Drechsler
Conference:
13th Asia and South Pacific Design Automation Conference, (ASP-DAC 2008)
Reference:

Seoul, 2008
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» SWORD: A SAT like Prover Using Word Level Information




Author:

Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
Conference:
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC)
Reference:

pp. 88-93, Atlanta, 2007
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Co-Synthesis of Custom On-Chip Bus and Memory for MPSoC Architectures




Author:

Sujan Pandey, Christian Genz, Rolf Drechsler
Conference:
IFIP International Conference on Very Large Scale Integration Systems and Systems on Chip (VLSI-SoC)
Reference:

pp. 304-307, Atlanta, 2007
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Improving Test Pattern Compactness in SAT-based ATPG




Author:

Stephan Eggersglüß, Rolf Drechsler
Conference:
16th Asian Test Symposium (ATS’07)
Reference:

pp. 445-450, Beijing, 2007
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» An Integrated SystemC Debugging Environment




Author:

Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke
Conference:
Forum on Specification & Design Languages (FDL)
Reference:

pp. 140-145, Barcelona, 2007
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Measuring the Quality of a SystemC Testbench by using Code Coverage Technqiues




Author:

Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Reference:

pp. 146-151, Barcelona, 2007
Received Best Paper Award
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Proving Completeness of Properties in Formal Verification of Counting Heads for Railways




Author:

Sebastian Kinder and Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Architectures, Methods and Tools
Reference:

Lübeck, 2007
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» On the Construction of Small Fully Testable Circuits with Low Depth




Author:

Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Architectures, Methods and Tools
Reference:

Lübeck, 2007
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Hardware Project Management - What we Can Learn from the Software Development Process for Hardware Design?




Author:

Rolf Drechsler, Andreas Breiter
Conference:
2nd International Conference on Software and Data Technologies
Reference:

Barcelona, 2007
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults




Author:

Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel
Conference:
Fifth ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2007)
Reference:

pp. 181-187, Nice, 2007
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Improving the Quality of Bounded Model Checking by Means of Coverage Estimation




Author:

Ulrich Kühne, Daniel Große, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
Reference:

pp. 165-170, Porto Alegre, 2007
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^m) in SystemC




Author:

Andre Sülflow, Rolf Drechsler
Conference:
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07)
Reference:

pp. 42, Oslo, 2007
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL




Author:

Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler
Conference:
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07)
Reference:

Oslo, 2007
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Experimental Studies on SAT-based ATPG for Gate Delay Faults




Author:

Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Conference:
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07)
Reference:

Oslo, 2007
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Visualization of SystemC Designs




Author:

Christian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS)
Reference:

pp. 413-416, New Orleans, 2007
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]
PS:

[view PS]



» SAT-based ATPG for Path Delay Faults in Sequential Circuits




Author:

Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'07)
Reference:

pp. 3671-3674, New Orleans, 2007
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Improvements for Constraint Solving in the SystemC Verification Library




Author:

Daniel Große, Rüdiger Ebendt, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 493-496, Stresa, 2007
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Exact SAT-based Toffoli Network Synthesis




Author:

Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 96-101, Stresa, 2007
Hyperlink:

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» Ein formaler Ansatz zum Robustheitsnachweis




Author:

Görschwin Fey, Rolf Drechsler
Conference:
Zuverlässigkeit und Entwurf
Reference:

München, 2007
Hyperlink:

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» Robust Multi-Objective Optimization in High Dimensional Spaces




Author:

André Sülflow, Nicole Drechsler, Rolf Drechsler
Conference:
Fourth International Conference on Evolutionary Multi-Criterion Optimization
Reference:

pp. 715-726, Matsushima, 2007
Hyperlink:

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» Estimating Functional Coverage in Bounded Model Checking




Author:

Daniel Große, Ulrich Kühne, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1176-1181, Nice, 2007
Hyperlink:

[To the Site of this Conference]
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» Modeling and Formal Verification of Counting Heads for Railways




Author:

Sebastian Kinder, Rolf Drechsler
Conference:
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2007)
Reference:

Braunschweig, 2007
Hyperlink:

[To the Site of this Conference]
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» Reusing Learned Information in SAT-based ATPG




Author:

Görschwin Fey, Tim Warode, Rolf Drechsler
Conference:
20th International Conference on VLSI Design
Reference:

Bangalore, 2007
Hyperlink:

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» Automatic Fault Localization for Property Checking




Author:

Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler
Conference:
Haifa Verification Conference
Reference:

Haifa, 2006
Hyperlink:

[To the Site of this Conference]
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» Technical Documentation of Software and Hardware in Embedded Systems




Author:

Beate Muranko, Rolf Drechsler
Conference:
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC 2006)
Reference:

Nice, France 2006
Hyperlink:

[To the Site of this Conference]
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» A Framework for Quasi-Exact Optimization using Relaxed Best-First Search




Author:

Rüdiger Ebendt, Rolf Drechsler
Conference:
29th Annual German Conference on Artificial Intelligence (KI'06)
Reference:

Bremen, 2006
Hyperlink:

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» HW/SW Co-Verification of Embedded Systems using Bounded Model Checking




Author:

Daniel Große, Ulrich Kühne, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference:

pp. 43-48, Philadelphia, 2006
Hyperlink:

[To the Site of this Conference]
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» Efficiency of Multiple-Valued Encoding in SAT-based ATPG




Author:

Görschwin Fey, Junhao Shi, Rolf Drechsler
Conference:
IEEE International Symposium on Multiple-Valued Logic (ISMVL '06)
Reference:

Singapore, 2006
Hyperlink:

[To the Site of this Conference]
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» Integrating Observability Don't Cares in All-Solution SAT Solvers




Author:

Sean Safarpour, Andreas Veneris, Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'06)
Reference:

Kos, 2006
Hyperlink:

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» On the Sensitivity of BDDs with Respect to Path-Related Objective Functions




Author:

Rüdiger Ebendt, Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'06)
Reference:

Kos, 2006
Hyperlink:

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» System Exploration of SystemC Designs




Author:

Christian Genz, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Reference:

pp. 335-340, Karlsruhe, 2006
Hyperlink:

[To the Site of this Conference]
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PS:

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» On the Relation Between Simulation-based and SAT-based Diagnosis




Author:

Görschwin Fey, Sean Safarpour, Andreas Veneris, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1139-1144, Munich, 2006
Hyperlink:

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» Efficient Minimization of Fully Testable 2-SPP Networks




Author:

Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1300-1305, Munich, 2006
Hyperlink:

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» Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks




Author:

Görschwin Fey, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Reference:

pp. 1225-1226, Munich, 2006
Hyperlink:

[To the Site of this Conference]
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» An Integrated Approach for Combining BDD and SAT Provers




Author:

Rolf Drechsler, Görschwin Fey, Sebastian Kinder
Conference:
International Conference on VLSI Design
Reference:

Hyderabad, 2006
Hyperlink:

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» Experimental Studies on SAT-based Test Pattern Generation for Industrial Circuits




Author:

Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke
Conference:
International Conference on ASIC (ASICON 2005)
Reference:

pp. 967-970, Shanghai, 2005
Hyperlink:

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» Post-Verification Debugging of Hierarchical Designs




Author:

Moayad Ali, Sean Safarpour, Andreas Veneris, Magdy Abadir, Rolf Drechsler
Conference:
IEEE International Conference on Computer Aided Design (ICCAD'05)
Reference:

pp. 871-876, San Jose, 2005
Hyperlink:

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» Exact BDD Minimization for Path-Related Objective Functions




Author:

Rüdiger Ebendt, Rolf Drechsler
Conference:
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC 2005)
Reference:

pp. 525-530, Perth, 2005
Hyperlink:

[To the Site of this Conference]
PS:

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» Acceleration of SAT-based Iterative Property Checking




Author:

Daniel Große, Rolf Drechsler
Conference:
Correct Hardware Design and Verification Methods (CHARME)
Reference:

pp. 349-353, Saarbrücken, 2005
Hyperlink:

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» Quasi-Exact BDD Minimization using Relaxed Best-First Search




Author:

Rüdiger Ebendt and Rolf Drechsler
Conference:
IEEE Annual Symposium on VLSI (ISVLSI '05)
Reference:

pp. 59-64, Tampa, Florida, 2005
Hyperlink:

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» PASSAT: Efficient SAT-based Test Pattern Generation




Author:

Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Conference:
IEEE Annual Symposium on VLSI (ISVLSI '05)
Reference:

pp.212-217, Tampa, Florida, 2005
Hyperlink:

[To the Site of this Conference]
PS:

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» Controlling the Memory During Manipulation of Word-Level Decision Diagrams




Author:

Sebastian Kinder, Görschwin Fey, Rolf Drechsler
Conference:
IEEE International Symposium on Multi-Valued Logic (ISMVL 2005)
Reference:

pp. 250-255, Calgary, 2005
Hyperlink:

[To the Site of this Conference]
PS:

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» Utilizing Don't Care States in SAT-based Bounded Sequential Problems




Author:

Sean Safarpour, Görschwin Fey, Andreas Veneris, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI'05)
Reference:

Chicago, 2005
Hyperlink:

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» CheckSyC: An Efficient Property Checker for RTL SystemC Designs




Author:

Daniel Große, Rolf Drechsler
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'05)
Reference:

pp. 4167-4170, Kobe, 2005
Hyperlink:

[To the Site of this Conference]
PDF:

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» Bridging Fault Testability of BDD Circuits




Author:

Junhao Shi, Görschwin Fey, Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005)
Reference:

pp. 188-191 Shanghai, 2005
Hyperlink:

[To the Site of this Conference]
PDF:

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» Lower Bounds for Dynamic BDD Reordering




Author:

Rüdiger Ebendt and Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 20