» Weighted A* search - unifying view and application
[Link to the Homepage of this journal]
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Author:
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Rüdiger Ebendt, Rolf Drechsler |
| Journal: |
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Artificial Intelligence |
| Details: |
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Volume 173, Issue 15, Pages 1367-1456 (September 2009) |
Year:
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2009
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» Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
[Link to the Homepage of this journal]
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Author:
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Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille |
| Journal: |
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it - information technology |
| Details: |
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Volume 51, Number 2, pp. 102-111
Pdf download |
Year:
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2009
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» Exact Synthesis of Elementary Quantum Gate Circuits
[Link to the Homepage of this journal]
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Author:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Journal: |
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Multiple-Valued Logic and Soft Computing |
| Details: |
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Volume 15, Number 4, pp. 283-300 |
Year:
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2009
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» Advanced Verification by Automatic Property Generation
[Link to the Homepage of this journal]
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Author:
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Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke |
| Journal: |
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IET Computers & Digital Techniques |
| Details: |
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Volume 3, Issue 4, pp. 338-353, July |
Year:
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2009
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» Exact Multiple Control Toffoli Network Synthesis with SAT Techniques
[Link to the Homepage of this journal]
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Author:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Journal: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 28, Number 5, pp. 703-715, May |
Year:
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2009
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» Modeling and Proving Completeness in Formal Verification of Counting Heads
[Link to the Homepage of this journal]
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Author:
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Sebastian Kinder, Rolf Drechsler |
| Journal: |
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Software Tools for Technology Transfer (STTT)
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| Details: |
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Springer, Volume 10, Number 6, pp. 521 - 534 |
Year:
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2008
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» On Acceleration of SAT-based ATPG for Industrial Designs
[Link to the Homepage of this journal]
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Author:
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Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Daniel Tille |
| Journal: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 27, Number 7, pp. 1329-1333, July |
Year:
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2008
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» Improved SAT-based Reachability Analysis with Observability Don’t Cares
[Link to the Homepage of this journal]
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Author:
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Sean Safarpour, Andreas Veneris and Rolf Drechsler |
| Journal: |
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Journal on Satisfiability, Boolean Modeling and Computation (JSAT) |
| Details: |
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Volume 5, pp. 1-25, Special Volume on Application of Constraints to Formal Verification |
Year:
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2008
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» On the Construction of Small Fully Testable Circuits with Low Depth
[Link to the Homepage of this journal]
|
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Author:
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Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler |
| Journal: |
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Embedded Hardware Design - Microprocessors and Microsystems (MICPRO) |
| Details: |
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Special Issue, Volume 32, Issues 5-6, pp. 263-269 |
Year:
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2008
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» Logic Minimization and Testability of 2-SPP Networks
[Link to the Homepage of this journal]
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Author:
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Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa |
| Journal: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 27, Number 7, pp. 1190-1202, July |
Year:
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2008
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» Analyzing Functional Coverage in Bounded Model Checking
[Link to the Homepage of this journal]
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Author:
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Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Journal: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 27, Number 7, pp. 1305-1314, July |
Year:
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2008
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» Automatic Fault Localization for Property Checking
[Link to the Homepage of this journal]
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Author:
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Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler |
| Journal: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 27, Number 6, pp. 1138-1149, June |
Year:
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2008
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» BDD-based Verification of Scalable Designs
[Link to the Homepage of this journal]
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Author:
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Daniel Große, Rolf Drechsler |
| Journal: |
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Facta Universitatis, Series: Electronics and Energetics |
| Details: |
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Volume 20, Number 3, pp. 367-379 |
Year:
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2007
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» Building Free Binary Decision Diagrams Using SAT Solvers
[Link to the Homepage of this journal]
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Author:
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Robert Wille, Görschwin Fey, Rolf Drechsler |
| Journal: |
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Facta Universitatis, Series: Electronics and Energetics |
| Details: |
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Volume 20, Number 3, pp. 381-394, |
Year:
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2007
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» An Integrated Approach for Combining BDDs and SAT Provers
[Link to the Homepage of this journal]
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Author:
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Rolf Drechsler, Görschwin Fey, Sebastian Kinder |
| Journal: |
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Facta Universitatis, Series: Electronics and Energetics
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| Details: |
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Volume 20, Number 3, pp. 415-436 |
Year:
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2007
|
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» Technische Dokumentation von Soft- und Hardware in
eingebetteten Systemen
[Link to the Homepage of this journal]
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Author:
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|
Beate Muranko, Rolf Drechsler |
| Journal: |
|
it - information technology |
| Details: |
|
Number 2, pp. 110-117
Pdf download |
Year:
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2007
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» Exact minimisation of path-related objective functions for binary decision diagrams
[Link to the Homepage of this journal]
|
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Author:
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Rüdiger Ebendt, Rolf Drechsler |
| Journal: |
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IEE Proceedings Computer & Digital Techniques |
| Details: |
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Volume 153, Number 4, pp. 231-242, July |
Year:
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2006
|
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» Testability of SPP Three-Level Logic Networks in Static Fault Models
[Link to the Homepage of this journal]
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Author:
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Valentina Ciriani, Anna Bernasconi, Rolf Drechsler |
| Journal: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 25, Number 10, pp. 2241-2248, October |
Year:
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2006
|
|
» The Effect of Improved Lower Bounds in Dynamic BDD Reordering
[Link to the Homepage of this journal]
|
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Author:
|
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Rüdiger Ebendt, Rolf Drechsler |
| Journal: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 25, Number 5, pp. 902-909, May |
Year:
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2006
|
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» Minimizing the Number of Paths in BDDs
- Theory and Algorithm
[Link to the Homepage of this journal]
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Author:
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Görschwin Fey, Rolf Drechsler |
| Journal: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 25, Number 1, pp. 4-11, January |
Year:
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2006
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» Combining Ordered Best-First Search with Branch and Bound for Exact BDD Minimization
[Link to the Homepage of this journal]
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Author:
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Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler |
| Journal: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 24, Number 10, pp. 1515-1529, October |
Year:
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2005
|
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» System Level Validation Using Formal Techniques
[Link to the Homepage of this journal]
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Author:
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Rolf Drechsler, Daniel Große |
| Journal: |
|
IEE Proceedings Computer & Digital Techniques, Special Issue on Embedded Microelectronic Systems: Status and Trends |
| Details: |
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Volume 152, Number 3, pp. 393-406, May |
Year:
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2005
|
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» Generic Implementation of Multi-Valued Decision Diagram Packages
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Author:
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Rolf Drechsler, Dragan Jankovic, Radomir Stankovic |
| Journal: |
|
Multiple-Valued Logic and Soft Computing |
| Details: |
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Volume 11, Numbers 1-2, pp. 1-18 |
Year:
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2005
|
|
» Project-Based Learning in Student Teams in Computer Science Education
[Link to the Homepage of this journal]
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Author:
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Andreas Breiter, Görschwin Fey, Rolf Drechsler |
| Journal: |
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Facta Universitatis, Series: Electronics and Energetics
|
| Details: |
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Volume 18, Number 2, August, pp. 165-180. |
Year:
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2005
|
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» Synthesis of Fully Testable Circuits from BDDs
[Link to the Homepage of this journal]
|
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Author:
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|
Rolf Drechsler, Junhao Shi, Görschwin Fey |
| Journal: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 23, Number 3, March |
Year:
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2004
|
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» Methods for Construction of Recursive Algorithms for Reed-Mulle-Fourier Polarity Matrices Calculation
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Author:
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Dragan Jankovic, Rolf Drechsler |
| Journal: |
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Multiple-Valued Logic and Soft Computing |
| Details: |
|
Volume 10, Numbers 1, pp. 29-50 |
Year:
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2004
|
|
» Using Word-Level Information in Formal Hardware Verification
[Link to the Homepage of this journal]
|
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Author:
|
|
Rolf Drechsler |
| Journal: |
|
Automation and Remote Control |
| Details: |
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Year:
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|
Volume 65, Issue 6, pp. 963-977, June 2004
|
|
» An Improved Branch and Bound Algorithm for Exact BDD Minimization
[Link to the Homepage of this journal]
|
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Author:
|
|
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler |
| Journal: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 22, Number 12, pp. 1657-1663, December |
Year:
|
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2003
|
|
» Recursive Bi-Partitioning of Netlists for Large Number of Partitions
[Link to the Homepage of this journal]
|
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Author:
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Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst |
| Journal: |
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Journal of Systems Architecture - the Euromicro Journal |
| Details: |
|
Volume 49, pp. 521-528 |
Year:
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2003
|
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» Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC
[Link to the Homepage of this journal]
|
 |
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|
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Author:
|
|
Daniel Große, Rolf Drechsler |
| Journal: |
|
it - information technology |
| Details: |
|
Number 4, pp. 219-226, August |
Year:
|
|
2003
|
|
» Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams
[Link to the Homepage of this journal]
|
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|
|
Author:
|
|
Wolfgang Günther, Rolf Drechsler |
| Journal: |
|
IEEE Transactions on Computers |
| Details: |
|
Volume 52, Number 9, pp. 1196-1209, September |
Year:
|
|
2003
|
|
» Exact Routing with Search Space Reduction
[Link to the Homepage of this journal]
|
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Author:
|
|
Frank Schmiedle, Rolf Drechsler, Bernd Becker |
| Journal: |
|
IEEE Transactions on Computers |
| Details: |
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Volume 52, Number 6, pp. 815-825, June |
Year:
|
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2003
|
|
» Computer Architecture Core of Knowledge for Computer Science Studies
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Author:
|
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M. Stojcev, I. Milentijevic, D. Kehagias, Rolf Drechsler, M. Gusev |
| Journal: |
|
Cyprus Computer Society Journal |
| Details: |
|
Volume I, Edition 4, April |
Year:
|
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2003
|
|
» Polynomial Formal Verification of Multipliers
[Link to the Homepage of this journal]
|
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Author:
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|
Martin Keim, Rolf Drechsler, Bernd Becker, Michael Martin, Paul Molitor |
| Journal: |
|
Formal Methods in System Design: An International Journal |
| Details: |
|
Volume 22, Issue 1, pp. 39-58 |
Year:
|
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2003
|
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» Low Power Optimization Techniques for BDD Mapped Circuits Using Temporal Correlation
[Link to the Homepage of this journal]
|
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Author:
|
|
Rolf Drechsler, Mikael Kerttu, Per Lindgren, Mitch Thornton |
| Journal: |
|
Canadian Journal of Electrical and Computer Engineering |
| Details: |
|
Volume 27, Number 4, pp. 159-164, October |
Year:
|
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2002
|
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» Minimization of Word-level Decision Diagrams
[Link to the Homepage of this journal]
|
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Author:
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|
Rolf Drechsler, Wolfgang Günther, Stefan Höreth. |
| Journal: |
|
INTEGRATION, the VLSI Journal |
| Details: |
|
Volume 33, Issue 1-2, pp. 39-70 |
Year:
|
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2002
|
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» Minimization of Free BDDs
[Link to the Homepage of this journal]
|
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|
|
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Author:
|
|
Wolfgang Günther, Rolf Drechsler |
| Journal: |
|
INTEGRATION, the VLSI Journal |
| Details: |
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Volume 32, Issue 1-2, pp. 41-59 |
Year:
|
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2002
|
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» Verifying Integrity of Decision Diagrams
[Link to the Homepage of this journal]
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|
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Author:
|
|
Rolf Drechsler |
| Journal: |
|
INTEGRATION, the VLSI Journal |
| Details: |
|
Volume 32, Issue 1-2, pp. 61-75 |
Year:
|
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2002
|
|
» Heuristic Learning based on Genetic Programming
[Link to the Homepage of this journal]
|
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|
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Author:
|
|
Frank Schmiedle, Nicole Drechsler, Daniel Große and Rolf Drechsler |
| Journal: |
|
Genetic Programming and Evolvable Machines |
| Details: |
|
Volume 3, pp. 363-388, December |
Year:
|
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2002
|
|
» Dynamic Re-Encoding During MDD Minimization
[Link to the Homepage of this journal]
|
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|
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Author:
|
|
Frank Schmiedle, Wolfgang Günther, Rolf Drechsler |
| Journal: |
|
Multiple-Valued Logic - An International Journal |
| Details: |
|
Volume 8, Numbers 5-6, pp. 625-643 |
Year:
|
|
2002
|
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» History-based Dynamic BDD Minimization
[Link to the Homepage of this journal]
|
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|
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Author:
|
|
Rolf Drechsler, Wolfgang Günther |
| Journal: |
|
INTEGRATION, the VLSI Journal |
| Details: |
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Volume 31, Issue 1, pp. 51-63 |
Year:
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2001
|
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» Äquivalenzvergleich digitaler Schaltungen im industriellen Umfeld
|
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Author:
|
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Rolf Drechsler |
| Journal: |
|
it+ti - Informationstechnik und Technische Informatik |
| Details: |
|
Oldenbourg Wissenschaftsverlag, Number 4, pp. 200-205 |
Year:
|
|
2001
|
|
» Fault Simulation in Multi-Valued Logic Networks
[Link to the Homepage of this journal]
|
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|
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Author:
|
|
Rolf Drechsler, Martin Keim, Bernd Becker |
| Journal: |
|
Multiple-Valued Logic - An International Journal |
| Details: |
|
Volume 7, Numbers 1-2, pp. 25-47 |
Year:
|
|
2001
|
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» Binary Decision Diagrams in Theory and Practice
[Link to the Homepage of this journal]
|
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|
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Author:
|
|
Rolf Drechsler, Detlef Sieling |
| Journal: |
|
Software Tools for Technology Transfer (STTT) |
| Details: |
|
Springer, Number 3, pp. 112-136 |
Year:
|
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2001
|
|
» Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
[Link to the Homepage of this journal]
|
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|
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Author:
|
|
Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker |
| Journal: |
|
Journal of Electronic Testing, Theory and Application (JETTA) |
| Details: |
|
No. 17, pp. 37-51, February |
Year:
|
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2001
|
|
» Decision Diagram Method for Calculation of Pruned Walsh Transform
[Link to the Homepage of this journal]
|
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Author:
|
|
Dragan Jankovic, Radomir Stankovic, Rolf Drechsler |
| Journal: |
|
IEEE Transactions on Computers |
| Details: |
|
Volume 50, Number 2, pp. 147-157, February |
Year:
|
|
2001
|
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» Using Lower Bounds during Dynamic BDD Minimization
[Link to the Homepage of this journal]
|
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|
|
Author:
|
|
Rolf Drechsler, Wolfgang Günther, Fabio Somenzi |
| Journal: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 20, Number 1, pp. 51-57, January |
Year:
|
|
2001
|
|
» ACTion: Combining Logic Synthesis and Technology Mapping for MUX based FPGAs
[Link to the Homepage of this journal]
|
|
|
|
|
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Author:
|
|
Wolfgang Günther and Rolf Drechsler. |
| Journal: |
|
Journal of Systems Architecture - the Euromicro Journal |
| Details: |
|
Volume 46, Issue 14, pp. 1321-1334, December |
Year:
|
|
2000
|
|
» Boolean Function Representation and Spectral Characterization Using AND/OR Graphs
[Link to the Homepage of this journal]
|
|
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|
|
|
Author:
|
|
Alenka Zuzek, Rolf Drechsler, Mitch Thornton |
| Journal: |
|
INTEGRATION, the VLSI Journal |
| Details: |
|
Volume 29, Issue 2, pp. 101-116, September |
Year:
|
|
2000
|
|
» Genetic Algorithm for Minimization of fixed polarity Reed-Muller expressions
|
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|
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Author:
|
|
Rolf Drechsler, Bernd Becker and Nicole Drechsler |
| Journal: |
|
IEE Proceedings Computers and Digital Techniques |
| Details: |
|
Volume 147, Number 5, September |
Year:
|
|
2000
|
|
» On the Computational Power of Linearly Transformed BDDs
[Link to the Homepage of this journal]
|
 |
|
|
|
|
Author:
|
|
Wolfgang Günther, Rolf Drechsler |
| Journal: |
|
Information Processing Letters |
| Details: |
|
Volume 75, Nummer 3, pp. 119-125, August |
Year:
|
|
2000
|
|
» Fast Exact Minimization of BDDs
[Link to the Homepage of this journal]
|
|
|
|
|
|
Author:
|
|
Rolf Drechsler, Nicole Drechsler, Wolfgang Günther |
| Journal: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 19, Number 3, pp. 384-389, March |
Year:
|
|
2000
|
|
» Pseudo Kronecker Expressions for Symmetric Functions
[Link to the Homepage of this journal]
|
|
|
|
|
|
Author:
|
|
Rolf Drechsler |
| Journal: |
|
IEEE Transactions on Computers |
| Details: |
|
Volume 48, Number 9, pp. 987-990, September |
Year:
|
|
1999
|
|
» Testability of 2-Level AND/EXOR Circuits
[Link to the Homepage of this journal]
|
|
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|
|
|
Author:
|
|
Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker |
| Journal: |
|
Journal of Electronic Testing, Theory and Application (JETTA) |
| Details: |
|
Volume 14, Number 3, pp. 173-192, June |
Year:
|
|
1999
|
|
» BDD Minimization Using Symmetries
[Link to the Homepage of this journal]
|
|
|
|
|
|
Author:
|
|
Christoph Scholl, Dirk Möller, Paul Molitor, Rolf Drechsler |
| Journal: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 18, Number 2, pp. 81-100, February |
Year:
|
|
1999
|
|
» On Variable Ordering and Decomposition Type Choice in OKFDDs
[Link to the Homepage of this journal]
|
|
|
|
|
|
Author:
|
|
Rolf Drechsler, Bernd Becker, Andrea Jahnke |
| Journal: |
|
IEEE Transactions on Computers |
| Details: |
|
Volume 47, Number 12, December |
Year:
|
|
1998
|
|
» Verifying UML/OCL Models Using Boolean Satisfiability
|
|
|
|
Author:
|
|
Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler |
| Conference: |
|
Design, Automation and Test in Europe (DATE) |
Reference:
|
| Dresden, 2010
|
Hyperlink:
|
| [To the Site of this Conference]
|
» Timing Arc Based Logic Analysis for False Noise Reduction
|
|
|
|
Author:
|
|
Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler |
| Conference: |
|
IEEE/ACM International Conference on Computer Aided Design (ICCAD) |
Reference:
|
| San Jose, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Anwendungsbezogene Analyse der Robustheit von Digitalen Schaltungen
|
|
|
|
Author:
|
|
Andre Sülflow, Stefan Frehse, Görschwin Fey, Rolf Drechsler |
| Conference: |
|
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) |
Reference:
|
| pp. 45-52, Stuttgart, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Structural Heuristics for SAT-based ATPG
|
|
|
|
Author:
|
|
Daniel Tille, Stephan Eggersglüß, Hoang M. Le, Rolf Drechsler |
| Conference: |
|
17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2009) |
Reference:
|
| Florianópolis, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Speeding up SAT-based ATPG using Dynamic Clause Activation
|
|
|
|
Author:
|
|
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
| Conference: |
|
18th Asian Test Symposium (ATS'09) |
Reference:
|
| Taichung, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Automatic Debugging of System-on-a-Chip Designs
|
|
|
|
Author:
|
|
Frank Rogin, Rolf Drechsler, Steffen Rülke |
| Conference: |
|
IEEE International SOC Conference (SOCC) |
Reference:
|
| Belfast, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» SMT-based Stimuli Generation in the SystemC Verification Library
|
|
|
|
Author:
|
|
Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler |
| Conference: |
|
Forum on specification & Design Languages (FDL) |
Reference:
|
| Sophia Antipolis, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Robustness Check for Multiple Faults using Formal Techniques
|
|
|
|
Author:
|
|
Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler |
| Conference: |
|
Euromicro Conference on Digital System Design (DSD) |
Reference:
|
| pp. 85-90, Patras, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» BDD-based Synthesis of Reversible Logic for Large Functions
|
|
|
|
Author:
|
|
Robert Wille, Rolf Drechsler |
| Conference: |
|
Design Automation Conference (DAC) |
Reference:
|
| pp. 270-275, San Francisco, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Computing Bounds for Fault Tolerance using Formal Techniques
|
|
|
|
Author:
|
|
Görschwin Fey, Andre Sülflow, Rolf Drechsler |
| Conference: |
|
Design Automation Conference (DAC) |
Reference:
|
| pp. 190-195, San Francisco, USA, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» WoLFram - A Word Level Framework for Formal Verification
|
|
|
|
Author:
|
|
Andre Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler |
| Conference: |
|
IEEE/IFIP International Symposium on Rapid System Prototyping (RSP) |
Reference:
|
| pp. 11-17, Paris, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» A Fast Untestability Proof for SAT-based ATPG
|
|
|
|
Author:
|
|
Daniel Tille, Rolf Drechsler |
| Conference: |
|
12th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems |
Reference:
|
| pp. 38-43, Liberec, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Increasing Robustness of SAT-based Delay Test Generation using Efficient Dynamic Learning Techniques
|
|
|
|
Author:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Conference: |
|
14th IEEE European Test Symposium (ETS) |
Reference:
|
| pp. 81-86, Sevilla, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Contradictory Antecedent Debugging in Bounded Model Checking
|
|
|
|
Author:
|
|
Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
| Conference: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Reference:
|
| pp. 173-176, Boston, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Evaluation of Cardinality Constraints on SMT-based Debugging
|
|
|
|
Author:
|
|
Andre Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler |
| Conference: |
|
39th International Symposium on Multiple-Valued Logic (ISMVL) |
Reference:
|
| pp. 298-303, Naha, Okinawa, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Equivalence Checking of Reversible Circuits
|
|
|
|
Author:
|
|
Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler |
| Conference: |
|
39th International Symposium on Multiple-Valued Logic (ISMVL) |
Reference:
|
| pp. 324-330, Naha, Okinawa, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Approximate BDD Minimization by Weighted A*
|
|
|
|
Author:
|
|
Rüdiger Ebendt, Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'09) |
Reference:
|
| Taipei, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
» Overcoming Limitations of the SystemC Data Introspection
|
|
|
|
Author:
|
|
Christian Genz, Rolf Drechsler |
| Conference: |
|
Design Automation and Test in Europe (DATE)
|
Reference:
|
| pp. 590-593, Nice, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Property Analysis and Design Understanding
|
|
|
|
Author:
|
|
Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Conference: |
|
Design, Automation and Test in Europe (DATE)
|
Reference:
|
| pp. 1246-1249, Nice, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Debugging of Toffoli Networks
|
|
|
|
Author:
|
|
Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
|
| Conference: |
|
Design, Automation and Test in Europe (DATE) |
Reference:
|
| pp. 1284-1289, Nice, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Increasing the Accuracy of SAT-based Debugging
|
|
|
|
Author:
|
|
Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler |
| Conference: |
|
Design, Automation and Test in Europe (DATE) |
Reference:
|
| pp. 1326-1332, Nice, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Reversible Logic Synthesis with Output Permutation
|
|
|
|
Author:
|
|
Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
| Conference: |
|
22nd International Conference on VLSI Design |
Reference:
|
| pp. 189-194, New Delhi, 2009
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Formaler Nachweis der Fehlertoleranz von Schaltkreisen
|
|
|
|
Author:
|
|
Görschwin Fey, Andre Sülflow, Stefan Frehse, Ulrich Kühne, Rolf Drechsler |
| Conference: |
|
GMM/GI/ITG-Fachtagung: Zuverlässigkeit und Entwurf (ZuE 2008) |
Reference:
|
| pp. 75-82, Ingolstadt, 2008
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Verification of PLC Programs using Formal Proof Techniques
|
|
|
|
Author:
|
|
Andre Sülflow, Rolf Drechsler |
| Conference: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008) |
Reference:
|
| pp. 43-50, Budapest, 2008
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Efficient Formal Verification of Track Vacancy Detection Sections
|
|
|
|
Author:
|
|
Sebastian Kinder und Rolf Drechsler |
| Conference: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008)
|
Reference:
|
| Budapest, 2008
|
Hyperlink:
|
| [To the Site of this Conference]
|
» Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking
|
|
|
|
Author:
|
|
Robert Wille, Görschwin Fey, Marc Messing, Gerhard
Angst, Lothar Linhard, Rolf Drechsler |
| Conference: |
|
Euromicro Conference on Digital System Design (DSD) |
Reference:
|
| pp. 542-549, Parma, 2008
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Contradiction Analysis for Constraint-based Random Simulation
|
|
|
|
Author:
|
|
Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler |
| Conference: |
|
Forum on specification & Design Languages (FDL) |
Reference:
|
| pp. 130-135, Stuttgart, 2008
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability
|
|
|
|
Author:
|
|
Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler |
| Conference: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Reference:
|
| pp. 411-416, Montpellier, 2008
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» RevLib: An Online Resource for
Reversible Functions and Reversible Circuits
|
|
|
|
Author:
|
|
Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler |
| Conference: |
|
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Reference:
|
| pp. 220-225, Dallas, 2008
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Exact Synthesis of Elementary Quantum Gate
Circuits for Reversible Functions with Don’t Cares
|
|
|
|
Author:
|
|
Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Conference: |
|
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Reference:
|
| pp. 214-219, Dallas, 2008
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» On the Influence of Boolean Encodings in SAT-based ATPG for Path Delay Faults
|
|
|
|
Author:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Conference: |
|
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Reference:
|
| pp. 94-99, Dallas, 2008
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Using Unsatisfiable Cores to Debug Multiple Design Errors
|
|
|
|
Author:
|
|
Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
| Conference: |
|
IEEE Great Lakes Symposium on VLSI (GLSVLSI'08) |
Reference:
|
| pp. 77-82, Orlando, 2008
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Process Variations Aware Robust on-Chip Bus Architecture Synthesis for MPSoCs
|
|
|
|
Author:
|
|
Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner |
| Conference: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'08) |
Reference:
|
| Seattle, 2008
|
Hyperlink:
|
| [To the Site of this Conference]
|
» A Basis for Formal Robustness Checking
|
|
|
|
Author:
|
|
Görschwin Fey, Rolf Drechsler
|
| Conference: |
|
International Symposium on Quality of Electronic Design (ISQED) |
Reference:
|
| San Jose, 2008
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Adaptive Branch and Bound using SAT to Estimate False Crosstalk
|
|
|
|
Author:
|
|
Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler
|
| Conference: |
|
International Symposium on Quality of Electronic Design (ISQED) |
Reference:
|
| San Jose, 2008
|
Hyperlink:
|
| [To the Site of this Conference]
|
» Automatic Generation of Complex Properties for Hardware Designs
|
|
|
|
Author:
|
|
Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler Steffen Rülke |
| Conference: |
|
Design, Automation, and Test in Europe (DATE) |
Reference:
|
| Munich, 2008
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs
|
|
|
|
Author:
|
|
Sujan Pandey, Rolf Drechsler |
| Conference: |
|
Design, Automation, and Test in Europe (DATE) |
Reference:
|
| Munich, 2008
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Robust On-Chip Bus architecture Synthesis for MPSoCs Under Random Tasks Arrival
|
|
|
|
Author:
|
|
Sujan Pandey, Rolf Drechsler |
| Conference: |
|
13th Asia and South Pacific Design Automation Conference, (ASP-DAC 2008) |
Reference:
|
| Seoul, 2008
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» SWORD: A SAT like Prover Using Word Level Information
|
|
|
|
Author:
|
|
Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler |
| Conference: |
|
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC) |
Reference:
|
| pp. 88-93, Atlanta, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Co-Synthesis of Custom On-Chip Bus and Memory for
MPSoC Architectures
|
|
|
|
Author:
|
|
Sujan Pandey, Christian Genz, Rolf Drechsler |
| Conference: |
|
IFIP International Conference on Very Large Scale Integration Systems and Systems on Chip (VLSI-SoC) |
Reference:
|
| pp. 304-307, Atlanta, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Improving Test Pattern Compactness in SAT-based ATPG
|
|
|
|
Author:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Conference: |
|
16th Asian Test Symposium (ATS’07) |
Reference:
|
| pp. 445-450, Beijing, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» An Integrated SystemC Debugging Environment
|
|
|
|
Author:
|
|
Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke |
| Conference: |
|
Forum on Specification & Design Languages (FDL) |
Reference:
|
| pp. 140-145, Barcelona, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Measuring the Quality of a SystemC Testbench by using Code Coverage Technqiues
|
|
|
|
Author:
|
|
Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler |
| Conference: |
|
Forum on specification & Design Languages (FDL) |
Reference:
|
| Barcelona, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Proving Completeness of Properties in Formal Verification of Counting Heads for Railways
|
|
|
|
Author:
|
|
Sebastian Kinder and Rolf Drechsler |
| Conference: |
|
Euromicro Conference on Digital System Design (DSD)
Architectures, Methods and Tools |
Reference:
|
| Lübeck, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» On the Construction of Small Fully Testable Circuits with Low Depth
|
|
|
|
Author:
|
|
Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler |
| Conference: |
|
Euromicro Conference on Digital System Design (DSD)
Architectures, Methods and Tools |
Reference:
|
| Lübeck, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Hardware Project Management - What we Can Learn from the Software Development Process for Hardware Design?
|
|
|
|
Author:
|
|
Rolf Drechsler, Andreas Breiter |
| Conference: |
|
2nd International Conference on Software and Data Technologies |
Reference:
|
| Barcelona, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
» Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
|
|
|
|
Author:
|
|
Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
| Conference: |
|
Fifth ACM-IEEE International Conference on
Formal Methods and Models for Codesign (MEMOCODE'2007) |
Reference:
|
| pp. 181-187, Nice, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
|
|
|
|
Author:
|
|
Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Conference: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07) |
Reference:
|
| pp. 165-170, Porto Alegre, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^m) in SystemC
|
|
|
|
Author:
|
|
Andre Sülflow, Rolf Drechsler |
| Conference: |
|
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07) |
Reference:
|
| pp. 42, Oslo, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL
|
|
|
|
Author:
|
|
Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler |
| Conference: |
|
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07) |
Reference:
|
| Oslo, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Experimental Studies on SAT-based ATPG for Gate Delay Faults
|
|
|
|
Author:
|
|
Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
| Conference: |
|
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07) |
Reference:
|
| Oslo, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Visualization of SystemC Designs
|
|
|
|
Author:
|
|
Christian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard |
| Conference: |
|
IEEE International Symposium on Circuits and Systems (ISCAS) |
Reference:
|
| pp. 413-416,
New Orleans, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
PS:
|
| [view PS]
|
» SAT-based ATPG for Path Delay Faults in Sequential Circuits
|
|
|
|
Author:
|
|
Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'07) |
Reference:
|
| pp. 3671-3674, New Orleans, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Improvements for Constraint Solving in the SystemC Verification Library
|
|
|
|
Author:
|
|
Daniel Große, Rüdiger Ebendt, Rolf Drechsler |
| Conference: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Reference:
|
| pp. 493-496, Stresa, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Exact SAT-based Toffoli Network Synthesis
|
|
|
|
Author:
|
|
Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler |
| Conference: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Reference:
|
| pp. 96-101, Stresa, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Ein formaler Ansatz zum Robustheitsnachweis
|
|
|
|
Author:
|
|
Görschwin Fey, Rolf Drechsler |
| Conference: |
|
Zuverlässigkeit und Entwurf |
Reference:
|
| München, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Robust Multi-Objective Optimization in High Dimensional Spaces
|
|
|
|
Author:
|
|
André Sülflow, Nicole Drechsler, Rolf Drechsler |
| Conference: |
|
Fourth International Conference on Evolutionary Multi-Criterion Optimization |
Reference:
|
| pp. 715-726, Matsushima, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Estimating Functional Coverage in Bounded Model Checking
|
|
|
|
Author:
|
|
Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Conference: |
|
Design, Automation and Test in Europe (DATE) |
Reference:
|
| pp. 1176-1181, Nice, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Modeling and Formal Verification of Counting Heads for Railways
|
|
|
|
Author:
|
|
Sebastian Kinder, Rolf Drechsler |
| Conference: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2007) |
Reference:
|
| Braunschweig, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Reusing Learned Information in SAT-based ATPG
|
|
|
|
Author:
|
|
Görschwin Fey, Tim Warode, Rolf Drechsler |
| Conference: |
|
20th International Conference on VLSI Design |
Reference:
|
| Bangalore, 2007
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Automatic Fault Localization for Property Checking
|
|
|
|
Author:
|
|
Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
| Conference: |
|
Haifa Verification Conference |
Reference:
|
| Haifa, 2006
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Technical Documentation of Software and Hardware
in Embedded Systems
|
|
|
|
Author:
|
|
Beate Muranko, Rolf Drechsler |
| Conference: |
|
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC 2006) |
Reference:
|
| Nice, France 2006
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» A Framework for Quasi-Exact Optimization using Relaxed Best-First Search
|
|
|
|
Author:
|
|
Rüdiger Ebendt, Rolf Drechsler |
| Conference: |
|
29th Annual German Conference on Artificial Intelligence (KI'06) |
Reference:
|
| Bremen, 2006
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» HW/SW Co-Verification of Embedded Systems using Bounded Model Checking
|
|
|
|
Author:
|
|
Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Conference: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Reference:
|
| pp. 43-48, Philadelphia, 2006
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Efficiency of Multiple-Valued Encoding in SAT-based ATPG
|
|
|
|
Author:
|
|
Görschwin Fey, Junhao Shi, Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Multiple-Valued Logic (ISMVL '06) |
Reference:
|
| Singapore, 2006
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Integrating Observability Don't Cares in All-Solution SAT Solvers
|
|
|
|
Author:
|
|
Sean Safarpour, Andreas Veneris, Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'06) |
Reference:
|
| Kos, 2006
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» On the Sensitivity of BDDs with Respect to Path-Related Objective Functions
|
|
|
|
Author:
|
|
Rüdiger Ebendt, Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'06) |
Reference:
|
| Kos, 2006
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» System Exploration of SystemC Designs
|
|
|
|
Author:
|
|
Christian Genz, Rolf Drechsler |
| Conference: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Reference:
|
| pp. 335-340, Karlsruhe, 2006
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
PS:
|
| [view PS]
|
» On the Relation Between Simulation-based and SAT-based Diagnosis
|
|
|
|
Author:
|
|
Görschwin Fey, Sean Safarpour, Andreas Veneris, Rolf Drechsler |
| Conference: |
|
Design, Automation and Test in Europe (DATE) |
Reference:
|
| pp. 1139-1144, Munich, 2006
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Efficient Minimization of Fully Testable 2-SPP Networks
|
|
|
|
Author:
|
|
Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa |
| Conference: |
|
Design, Automation and Test in Europe (DATE) |
Reference:
|
| pp. 1300-1305, Munich, 2006
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks
|
|
|
|
Author:
|
|
Görschwin Fey, Daniel Große, Rolf Drechsler |
| Conference: |
|
Design, Automation and Test in Europe (DATE) |
Reference:
|
| pp. 1225-1226, Munich, 2006
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» An Integrated Approach for Combining BDD and SAT Provers
|
|
|
|
Author:
|
|
Rolf Drechsler, Görschwin Fey, Sebastian Kinder |
| Conference: |
|
International Conference on VLSI Design |
Reference:
|
| Hyderabad, 2006
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Experimental Studies on SAT-based Test Pattern Generation for Industrial Circuits
|
|
|
|
Author:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke |
| Conference: |
|
International Conference on ASIC (ASICON 2005)
|
Reference:
|
| pp. 967-970, Shanghai, 2005
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Post-Verification Debugging of Hierarchical Designs
|
|
|
|
Author:
|
|
Moayad Ali, Sean Safarpour, Andreas Veneris, Magdy Abadir, Rolf Drechsler |
| Conference: |
|
IEEE International Conference on Computer Aided Design (ICCAD'05) |
Reference:
|
| pp. 871-876, San Jose, 2005
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Exact BDD Minimization for Path-Related Objective Functions
|
|
|
|
Author:
|
|
Rüdiger Ebendt, Rolf Drechsler |
| Conference: |
|
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC 2005) |
Reference:
|
| pp. 525-530, Perth, 2005
|
Hyperlink:
|
| [To the Site of this Conference]
|
PS:
|
| [view PS]
|
» Acceleration of SAT-based Iterative Property Checking
|
|
|
|
Author:
|
|
Daniel Große, Rolf Drechsler |
| Conference: |
|
Correct Hardware Design and Verification Methods (CHARME) |
Reference:
|
| pp. 349-353, Saarbrücken, 2005
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Quasi-Exact BDD Minimization using Relaxed Best-First Search
|
|
|
|
Author:
|
|
Rüdiger Ebendt and Rolf Drechsler |
| Conference: |
|
IEEE Annual Symposium on VLSI (ISVLSI '05) |
Reference:
|
| pp. 59-64, Tampa, Florida, 2005
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» PASSAT: Efficient SAT-based Test Pattern Generation
|
|
|
|
Author:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
| Conference: |
|
IEEE Annual Symposium on VLSI (ISVLSI '05) |
Reference:
|
| pp.212-217, Tampa, Florida, 2005
|
Hyperlink:
|
| [To the Site of this Conference]
|
PS:
|
| [view PS]
|
» Controlling the Memory During Manipulation of Word-Level Decision Diagrams
|
|
|
|
Author:
|
|
Sebastian Kinder, Görschwin Fey, Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL 2005) |
Reference:
|
| pp. 250-255, Calgary, 2005
|
Hyperlink:
|
| [To the Site of this Conference]
|
PS:
|
| [view PS]
|
» Utilizing Don't Care States in SAT-based Bounded Sequential Problems
|
|
|
|
Author:
|
|
Sean Safarpour, Görschwin Fey, Andreas Veneris, Rolf Drechsler |
| Conference: |
|
Great Lakes Symposium on VLSI (GLSVLSI'05) |
Reference:
|
| Chicago, 2005
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» CheckSyC: An Efficient Property Checker for RTL SystemC Designs
|
|
|
|
Author:
|
|
Daniel Große, Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'05) |
Reference:
|
| pp. 4167-4170, Kobe, 2005
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Bridging Fault Testability of BDD Circuits
|
|
|
|
Author:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler |
| Conference: |
|
Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005) |
Reference:
|
| pp. 188-191 Shanghai, 2005
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Lower Bounds for Dynamic BDD Reordering
|
|
|
|
Author:
|
|
Rüdiger Ebendt and Rolf Drechsler |
| Conference: |
|
Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005) |
Reference:
|
| pp. 579-582, Shanghai, 2005
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Automated Verification For Train Control Systems
|
|
|
|
Author:
|
|
Jan Peleska, Daniel Große, Anne E. Haxthausen, Rolf Drechsler |
| Conference: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2004) |
Reference:
|
| pp. 252-265, Braunschweig, 2004
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Debugging Sequential Circuits Using Boolean Satisfiability
|
|
|
|
Author:
|
|
Moayad Ali, Andreas Veneris, Sean Safarpour, Magdy Abadir, Rolf Drechsler, Alexander Smith |
| Conference: |
|
IEEE International Conference on Computer Aided Design (ICCAD'04) |
Reference:
|
| pp. 204-209, San Jose, 2004
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» BDD Circuit Optimization for Path Delay Fault Testability
|
|
|
|
Author:
|
|
Görschwin Fey, Junhao Shi, Rolf Drechsler |
| Conference: |
|
Euromicro Symposium on Digital System Design (DSD'2004) |
Reference:
|
| pp. 168-172, Rennes, 2004
|
Hyperlink:
|
| [To the Site of this Conference]
|
PS:
|
| [view PS]
|
» Checkers for SystemC Designs
|
|
|
|
Author:
|
|
Daniel Große, Rolf Drechsler |
| Conference: |
|
Second ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2004) |
Reference:
|
| pp. 171-178, San Diego, 2004
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Reduction of Sizes of Multiple-Valued Decision Diagrams by Copy Properties
|
|
|
|
Author:
|
|
Dragan Jankovic, Radomir Stankovic, Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2004) |
Reference:
|
| pp. 229-234, Toronto, 2004
|
Hyperlink:
|
| [To the Site of this Conference]
|
» Algorithms for Taylor Expansion Diagrams
|
|
|
|
Author:
|
|
Görschwin Fey, Rolf Drechsler, Maciej Ciesielski |
| Conference: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2004) |
Reference:
|
| pp. 235-240, Toronto, 2004
|
Hyperlink:
|
| [To the Site of this Conference]
|
PS:
|
| [view PS]
|
» Placement and Routing Optimization for Circuits Derived from BDDs
|
|
|
|
Author:
|
|
Thomas Eschbach, Rolf Drechsler, Bernd Becker |
| Conference: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'04) |
Reference:
|
| Vancouver, 2004
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Managing Don't Cares in Boolean
Satisfiability
|
|
|
|
Author:
|
|
Sean Safarpour, Andreas Veneris, Rolf Drechsler, Joanne Hang |
| Conference: |
|
IEEE Design, Automation and Test in Europe
|
Reference:
|
| Vol. I, pp. 260-265, Paris, 2004
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Improving Simulation-Based Verification by Means of Formal Methods
|
|
|
|
Author:
|
|
Görschwin Fey, Rolf Drechsler |
| Conference: |
|
Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
|
Reference:
|
| pp. 640-643, Yokohama, 2004
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Minimization of the Expected Path Length in BDDs Based on Local Changes
|
|
|
|
Author:
|
|
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler |
| Conference: |
|
Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
|
Reference:
|
| pp. 866-871, Yokohama, 2004
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Combining Ordered Best-First Search with Branch and Bound for Exact BDD Minimization
|
|
|
|
Author:
|
|
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler |
| Conference: |
|
Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
|
Reference:
|
| pp. 876-879, Yokohama, 2004
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Hardware Project Management – What we Can Learn from the Software Development Process for Hardware Design?
|
|
|
|
Author:
|
|
Rolf Drechsler, Andreas Breiter |
| Conference: |
|
4th Conference of Informatics and Information Technologies |
Reference:
|
| Bitola, 2003
|
Hyperlink:
|
| [To the Site of this Conference]
|
» Minimizing the Number of One-Paths in BDDs by an Evolutionary Algorithm
|
|
|
|
Author:
|
|
Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler |
| Conference: |
|
Congress on Evolutionary Computation 2003 (CEC2003) |
Reference:
|
| Vol.3, pp.1724-1731, Canberra, 2003
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
PS:
|
| [view PS]
|
» Testability of SPP Three-Level Logic Networks
|
|
|
|
Author:
|
|
Valentina Ciriani, Anna Bernasconi, Rolf Drechsler |
| Conference: |
|
IFIP International Conference on Very Large Scale Integration (VLSI'03) |
Reference:
|
| pp. 331-336, Darmstadt, 2003
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Exploration of Sequential Depth by Evolutionary Algorithms
|
|
|
|
Author:
|
|
Nicole Drechsler, Rolf Drechsler |
| Conference: |
|
IFIP International Conference on Very Large Scale Integration (VLSI'03) |
Reference:
|
| pp. 81-85, Darmstadt, 2003
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
|
|
|
|
Author:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler |
| Conference: |
|
Twelfth Asian Test Symposium (ATS03)
|
Reference:
|
| p.290-293,
Xi'an, 2003
|
Hyperlink:
|
| [To the Site of this Conference]
|
PS:
|
| [view PS]
|
» Efficient Automatic Visualization of SystemC Designs
|
|
|
|
Author:
|
|
Daniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst |
| Conference: |
|
Forum on Specification & Design Languages (FDL'03) |
Reference:
|
| pp. 646-657, Frankfurt, 2003
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Finding Good Counter-Examples to Aid Design Verification
|
|
|
|
Author:
|
|
Görschwin Fey, Rolf Drechsler |
| Conference: |
|
First ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2003) |
Reference:
|
| pp. 51-52, Mont Saint-Michel, 2003
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
PS:
|
| [view PS]
|
» Fast Heuristics for the Edge Coloring of Large Graphs
|
|
|
|
Author:
|
|
Mario Hilgemeier, Nicole Drechsler and Rolf Drechsler |
| Conference: |
|
Euromicro Symposium on Digital System Design (DSD'2003) |
Reference:
|
| pp. 230-237, Antalya, 2003
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
PS:
|
| [view PS]
|
» MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits
|
|
|
|
Author:
|
|
Rolf Drechsler, Junhao Shi and Görschwin Fey |
| Conference: |
|
IEEE Great Lakes Symposium on VLSI (GLSV'03) |
Reference:
|
| p. 80-83, Washington, 2003
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
PS:
|
| [view PS]
|
» Efficient Minimization of Multi-Valued Decision Diagrams for Incompletely Specified Functions
|
|
|
|
Author:
|
|
Denis Popel and Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003) |
Reference:
|
| pp. 241-246, Tokyo, 2003
|
Hyperlink:
|
| [To the Site of this Conference]
|
PS:
|
| [view PS]
|
» Augmented Sifting for Multiple-Valued Decision Diagrams
|
|
|
|
Author:
|
|
Michael Miller and Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003) |
Reference:
|
| pp. 375-382, Tokyo, 2003
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Modeling Multi-Valued Circuits in SystemC
|
|
|
|
Author:
|
|
Daniel Große, Görschwin Fey and Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003) |
Reference:
|
| pp. 281-286, Tokyo, 2003
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
PS:
|
| [view PS]
|
» Using Games for Benchmarking and Representing the Complete Solution Space Using Symbolic Techniques
|
|
|
|
Author:
|
|
Görschwin Fey, Sebastian Kinder and Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003) |
Reference:
|
| pp. 361-366, Tokyo, 2003
|
PS:
|
| [view PS]
|
» Formal Verification of LTL Formulas for SystemC Designs
|
|
|
|
Author:
|
|
Daniel Große, Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'03) |
Reference:
|
| pp. V:245-V:248, Bangkok, 2003
|
PDF:
|
| [view Pdf]
|
» Synthesizing Checkers for On-line Verification of System-on-Chip Designs
|
|
|
|
Author:
|
|
Rolf Drechsler |
| Conference: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'03) |
Reference:
|
| pp. IV:748-IV:751, Bangkok, 2003
|
PDF:
|
| [view Pdf]
|
» Minimization of Transitions by Complementation and Resequencing using Evolutionary Algorithms
|
|
|
|
Author:
|
|
Rolf Drechsler and Nicole Drechsler |
| Conference: |
|
21st IASTED International Multi-Conference Applied Informatics (AI 2003) |
Reference:
|
| Innsbruck, 2003
|
Hyperlink:
|
| [To the Site of this Conference]
|
PS:
|
| [view PS]
|
» Combination of Lower Bounds in Exact BDD Minimization
|
|
|
|
Author:
|
|
Rüdiger Ebendt, Wolfgang Günther and Rolf Drechsler |
| Conference: |
|
IEEE Design, Automation and Test in Europe (DATE'03) |
Reference:
|
| pp. 758-763, Munich, 2003
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
» Utilizing BDDs for disjoint SOP minimization
|
|
|
|
Author:
|
|
Görschwin Fey and Rolf Drechsler |
| Conference: |
|
IEEE The 45rd Midwest Symposium on Circuits and Systems (MWSCAS'2002) |
Reference:
|
| volume II, pages 306-309, Tulsa, 2002
|
PS:
|
| [view PS]
|
» Minimizing the Number of Paths in BDDs
|
|
|
|
Author:
|
|
Görschwin Fey and Rolf Drechsler |
| Conference: |
|
15th Symposium on Integrated Circuits and System Design |
Reference:
|
| pages 359-364, Porto Alegre, 2002
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
|
PS:
|
| [view PS]
|
» Crossing Reduction by Windows Optimization
|
|
|
|
Author:
|
|
Thomas Eschbach, Wolfgang Günther, Rolf Drechsler and Bernd Becker |
| Conference: |
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10th International Symposium on Graph Drawing (GD'2002) |
Reference:
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| LNCS 2528, pp. 285-294, Irvine, 2002
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PDF:
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| [view Pdf]
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PS:
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| [view PS]
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» Reachability Analysis for Formal Verification of SystemC
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Author:
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Rolf Drechsler and Daniel Große |
| Conference: |
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Euromicro Symposium on Digital System Design (DSD'2002) |
Reference:
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| pages 337-340, Dortmund, 2002
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Hyperlink:
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| [To the Site of this Conference]
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PDF:
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| [view Pdf]
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» Decision Diagrams Optimization Using Copy Properties
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Author:
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Dragan Jankovic, Radomir Stankovic and Rolf Drechsler |
| Conference: |
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Euromicro Symposium on Digital System Design (DSD'2002) |
Reference:
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| pages 236-243, Dortmund, 2002
|
Hyperlink:
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| [To the Site of this Conference]
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PDF:
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| [view Pdf]
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» Recursive Bi-Partitioning of Netlists for Large Number of Partitions
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Author:
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Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard and Gerhard Angst |
| Conference: |
|
Euromicro Symposium on Digital System Design (DSD'2002) |
Reference:
|
| pages 38-44, Dortmund, 2002
|
Hyperlink:
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| [To the Site of this Conference]
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PDF:
|
| [view Pdf]
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» JADE: Implementation and Visualization of a BDD Package in JAVA
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Author:
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Rolf Drechsler |
| Conference: |
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IEEE Design, Automation and Test in Europe (DATE'02) - User Forum |
Reference:
|
| page 259, Paris, 2002
|
Hyperlink:
|
| [To the Site of this Conference]
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PDF:
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| [view Pdf]
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» Computing Walsh, Arithmetic and Reed-Muller Spectral Decision Diagrams Using Graph Transformations
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Author:
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Whitney Townsend, Mitch Thornton, Rolf Drechsler and Michael Miller |
| Conference: |
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IEEE Great Lakes Symposium on VLSI (GLSV'02) |
Reference:
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| pp. 178-183, New York, 2002
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PDF:
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| [view Pdf]
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» Switching Activity Estimation for Finite State Machines for Low Power Synthesis (Poster)
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Author:
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Mikael Kerttu, Per Lindgren, Mitch Thornton and Rolf Drechsler |
| Conference: |
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IEEE International Symposium on Circuits and Systems (ISCAS'02) |
Reference:
|
| Scottsdale, 2002
|
Hyperlink:
|
| [To the Site of this Conference]
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PDF:
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| [view Pdf]
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PS:
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| [view PS]
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» Multi-Output Timed Shannon Circuits
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Author:
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Mitch Thorton, Rolf Drechsler and Michael Miller |
| Conference: |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002) |
Reference:
|
| pages 47-52, Pittsburgh, 2002
|
Hyperlink:
|
| [To the Site of this Conference]
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PDF:
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| [view Pdf]
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PS:
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| [view PS]
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» Evaluation of Static Variable Ordering Heuristics for MDD Construction
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Author:
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Rolf Drechsler |
| Conference: |
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IEEE International Symposium on Multi-Valued Logic (ISMVL'2002) |
Reference:
|
| pages 254-260, Boston, 2002
|
Hyperlink:
|
| [To the Site of this Conference]
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PDF:
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| [view Pdf]
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PS:
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| [view PS]
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» On the Construction of Multi-Valued Decision Diagrams
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Author:
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Michael Miller and Rolf Drechsler |
| Conference: |
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IEEE International Symposium on Multi-Valued Logic (ISMVL'2002) |
Reference:
|
| pages 245-253, Boston, 2002
|
Hyperlink:
|
| [To the Site of this Conference]
|
PDF:
|
| [view Pdf]
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» Efficient Calculation of Fixed-Polarity Polynomial Expressions for Multi-Valued Logic Functions
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