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Home « Team « Publications
» Publications of
Stephan Eggersglüß
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BOOKS |
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» High Quality Test Pattern Generation and Boolean Satisfiability
[Read more about this book!]
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Publisher: |
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Springer |
Author:
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Stephan Eggersglüß, Rolf Drechsler |
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Hardcover |
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2012
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» Test Pattern Generation using Boolean Proof Engines
[Read more about this book!]
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Publisher: |
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Springer |
Author:
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Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille |
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Hardcover |
Year:
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2009
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BOOK CONTRIBUTIONS |
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| » Robuste Erfüllbarkeitsalgorithmen für die Generierung hochwertiger Testmuster für digitale Schaltungen |
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Author:
| Stephan Eggersglüß
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| Editor: | S. Hölldobler et al. |
| Booktitle: | Ausgezeichnete Informatikdissertationen 2010 |
| Publisher: | GI |
| Sites: | 81-90 |
| Year: | 2011 |
| Format: | Paperback |
| » SWORD: A SAT like Prover Using Word Level Information |
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Author:
| Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
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| Editor: | Ricardo Reis, Vincent Mooney, Paul Hasler |
| Booktitle: | VLSI-SoC: Advanced Topics on Systems on a Chip:
A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip |
| Publisher: | Springer |
| Sites: | 175-192 |
| Year: | 2009 |
| Format: | Hardcover |
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JOURNALS |
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» A Highly Fault-Efficient SAT-Based ATPG Flow
[Link to the Homepage of this journal]
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Author:
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Stephan Eggersglüß, Rolf Drechsler |
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IEEE Design & Test of Computers |
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Volume 29, Issue 4 (July/August), pp. 63-70
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Year:
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2012
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» Efficient Data Structures and Methodologies for SAT-based ATPG providing High Fault Coverage in Industrial Application
[Link to the Homepage of this journal]
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Author:
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Stephan Eggersglüß, Rolf Drechsler |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 30, Number 9, pp. 1411-1415,
DOI: 10.1109/TCAD.2011.2152450 |
Year:
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2011
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» Incremental Solving Techniques for SAT-based ATPG
[Link to the Homepage of this journal]
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Author:
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Daniel Tille, Stephan Eggersglüß, Rolf Drechsler |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 29, Number 7, pp. 1125-1130, July |
Year:
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2010
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» MONSOON: SAT-based ATPG for Path Delay Faults Using Multiple-Valued Logics
[Link to the Homepage of this journal]
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Author:
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Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Rolf Drechsler |
| Journal: |
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Journal of Electronic Testing: Theory and Applications |
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Volume 26, Number 3 / June, pp. 307-322
Pdf download (Preliminary Version)
The final publication is available at www.springerlink.com |
Year:
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2010
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» Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
[Link to the Homepage of this journal]
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Author:
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Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille |
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it - information technology |
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Volume 51, Number 2, pp. 102-111
Pdf download |
Year:
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2009
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» On Acceleration of SAT-based ATPG for Industrial Designs
[Link to the Homepage of this journal]
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Author:
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Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Daniel Tille |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 27, Number 7, pp. 1329-1333, July |
Year:
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2008
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CONFERENCES |
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» Improved SAT-based ATPG: More Constraints, Better Compaction
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Author:
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Stephan Eggersglüß, Robert Wille, Rolf Drechsler |
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IEEE/ACM International Conference on Computer-Aided Design (ICCAD) |
Reference:
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| San Jose, USA, 2013
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| [To the Site of this Conference]
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» Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization
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Author:
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Stephan Eggersglüß, Mahmut Yilmaz, Krishnendu Chakrabarty |
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21st IEEE Asian Test Symposium (ATS) |
Reference:
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| pp. 290-295, Niigata, Japan, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» A New SAT-based ATPG for Generating Highly Compacted Test Sets
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Author:
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Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler |
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15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Reference:
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| pp. 230-235, Tallinn, Estonia, 2012
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization
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Author:
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Stephan Eggersglüß, Rolf Drechsler |
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Design, Automation and Test in Europe (DATE) |
Reference:
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| pp. 1291-1296, Grenoble, 2011
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Robust Algorithms for High Quality Test Pattern Generation Using Boolean Satisfiability
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Author:
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Stephan Eggersglüß, Rolf Drechsler |
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International Test Conference (ITC) |
Reference:
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| pp. 1-10, Austin, 2010
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Improving CNF Representations in SAT-based ATPG for Industrial Circuits using BDDs
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Author:
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Daniel Tille, Stephan Eggersglüß, René Krenz-Bååth, Juergen Schloeffel, Rolf Drechsler |
| Conference: |
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15th IEEE European Test Symposium (ETS) |
Reference:
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| pp. 176-181, Prag, 2010
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Efficient Test Generation with Maximal Crosstalk-Induced Noise using Unconstrained Aggressor Excitation
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Author:
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Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
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IEEE International Symposium on Circuits and Systems (ISCAS) |
Reference:
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| pp. 649-652, Paris, 2010
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Timing Arc Based Logic Analysis for False Noise Reduction
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Author:
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Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler |
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IEEE/ACM International Conference on Computer Aided Design (ICCAD) |
Reference:
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| pp. 225-230, San Jose, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Structural Heuristics for SAT-based ATPG
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Author:
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Daniel Tille, Stephan Eggersglüß, Hoang M. Le, Rolf Drechsler |
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17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2009) |
Reference:
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| pp. 77-82, Florianópolis, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Speeding up SAT-based ATPG using Dynamic Clause Activation
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Author:
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Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
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18th Asian Test Symposium (ATS'09) |
Reference:
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| pp. 177-182, Taichung, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Increasing Robustness of SAT-based Delay Test Generation using Efficient Dynamic Learning Techniques
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Author:
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Stephan Eggersglüß, Rolf Drechsler |
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14th IEEE European Test Symposium (ETS) |
Reference:
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| pp. 81-86, Sevilla, 2009
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» On the Influence of Boolean Encodings in SAT-based ATPG for Path Delay Faults
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Author:
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Stephan Eggersglüß, Rolf Drechsler |
| Conference: |
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38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Reference:
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| pp. 94-99, Dallas, 2008
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» SWORD: A SAT like Prover Using Word Level Information
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Author:
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Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler |
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IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC) |
Reference:
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| pp. 88-93, Atlanta, 2007
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Improving Test Pattern Compactness in SAT-based ATPG
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Author:
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Stephan Eggersglüß, Rolf Drechsler |
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16th Asian Test Symposium (ATS’07) |
Reference:
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| pp. 445-450, Beijing, 2007
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
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Author:
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Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel |
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Fifth ACM-IEEE International Conference on
Formal Methods and Models for Codesign (MEMOCODE'2007) |
Reference:
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| pp. 181-187, Nice, 2007
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» Experimental Studies on SAT-based ATPG for Gate Delay Faults
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Author:
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Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
| Conference: |
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37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07) |
Reference:
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| Oslo, 2007
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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» SAT-based ATPG for Path Delay Faults in Sequential Circuits
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Author:
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Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler |
| Conference: |
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IEEE International Symposium on Circuits and Systems (ISCAS'07) |
Reference:
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| pp. 3671-3674, New Orleans, 2007
| Hyperlink:
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| [To the Site of this Conference]
| PDF:
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| [view Pdf]
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WORKSHOPS |
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» Towards Increasing Test Compaction Abilities of SAT-based ATPG through Fault Detection Constraints
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Author:
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Stephan Eggersglüß, Melanie Diepenbeck, Robert Wille, Rolf Drechsler |
| Workshop: |
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IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12) |
Reference:
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| Niigata, Japan, 2012
| PDF:
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| [view Pdf]
| Hyperlink:
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| [Link to the Workshop]
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» Formal Analysis Techniques: A Basis for High-Quality Designs
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Author:
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Stephan Eggersglüß, Rolf Drechsler |
| Workshop: |
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IEEE International Workshop on Processor Verification, Test and Debug |
Reference:
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| Invited Talk, Trondheim, 2011
| PDF:
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| [view Pdf]
| Hyperlink:
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| [Link to the Workshop]
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» On Timing-Aware ATPG using Pseudo-Boolean Optimization
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Author:
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Stephan Eggersglüß, Rolf Drechsler |
| Workshop: |
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IEEE European Test Symposium (ETS), Informal Digest of Papers |
Reference:
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| Trondheim, 2011
| PDF:
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| [view Pdf]
| Hyperlink:
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| [Link to the Workshop]
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» As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization
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Author:
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Stephan Eggersglüß, Rolf Drechsler |
| Workshop: |
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23. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2011 |
Reference:
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| Passau, 2011
| PDF:
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| [view Pdf]
| Hyperlink:
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| [Link to the Workshop]
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» A Two-Stage SAT-based ATPG Approach with Reduced Switching Activity
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Author:
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Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
| Workshop: |
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Second International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR) 2009 |
Reference:
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| Sevilla, Spain, 2009
| PDF:
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| [view Pdf]
| Hyperlink:
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| [Link to the Workshop]
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» Robust Tests for Transition Faults with Long Propagation Paths Using Boolean Satisfiability
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Author:
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Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
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| Workshop: |
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IEEE European Test Symposium (ETS), Informal Digest of Papers |
Reference:
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| Lago Maggiore, 2008
| PDF:
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| [view Pdf]
| Hyperlink:
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| [Link to the Workshop]
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» SAT-based ATPG for Path Delay Fault in Industrial Circuits
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Author:
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Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel |
| Workshop: |
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IEEE European Test Symposium (ETS), Informal Digest of Papers |
Reference:
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| Freiburg, 2007
| Hyperlink:
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| [Link to the Workshop]
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» Studies on Integrating SAT-based ATPG in an Industrial Environment
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Author:
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Daniel Tille, Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
| Workshop: |
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19. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
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Reference:
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| Erlangen, 2007
| PDF:
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| [view Pdf]
| Hyperlink:
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| [Link to the Workshop]
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» Formal Verification on the Word Level using SAT-like Proof
Techniques
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Author:
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Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler |
| Workshop: |
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GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Reference:
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| pp. 165-173, Erlangen, 2007
| Hyperlink:
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| [Link to the Workshop]
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