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BOOKS


BOOK CONTRIBUTIONS


JOURNALS

» Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic




Author:

Sujan Pandey, Manfred Glesner
Journal:
IEEE Transaction on Very Large Scale Integration (VLSI) Systems
Details:
Volume 15, Number 10, pp. 1111-1124, October
Year:


2007






CONFERENCES



» Process Variations Aware Robust on-Chip Bus Architecture Synthesis for MPSoCs




Author:

Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner
Conference:
IEEE International Symposium on Circuits and Systems (ISCAS'08)
Reference:

Seattle, 2008
Hyperlink:

[To the Site of this Conference]



» Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs




Author:

Sujan Pandey, Rolf Drechsler
Conference:
Design, Automation, and Test in Europe (DATE)
Reference:

Munich, 2008
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Robust On-Chip Bus architecture Synthesis for MPSoCs Under Random Tasks Arrival




Author:

Sujan Pandey, Rolf Drechsler
Conference:
13th Asia and South Pacific Design Automation Conference, (ASP-DAC 2008)
Reference:

Seoul, 2008
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]



» Co-Synthesis of Custom On-Chip Bus and Memory for MPSoC Architectures




Author:

Sujan Pandey, Christian Genz, Rolf Drechsler
Conference:
IFIP International Conference on Very Large Scale Integration Systems and Systems on Chip (VLSI-SoC)
Reference:

pp. 304-307, Atlanta, 2007
Hyperlink:

[To the Site of this Conference]
PDF:

[view Pdf]


WORKSHOPS




» On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-Micron Interconnects.




Author:

Tudor Murgan, Petru Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner
Workshop:
In Intl. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sept. 2007.
Reference:

pp. 242-254, Göteborg, Sweden
Hyperlink:

[Link to the Workshop]

















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