Since October 2001 Prof. Dr. Rolf Drechsler is the head of the computer architecture group. Beside the lectures for graduate and undergraduate students, in the research field we are active in different areas of VLSI CAD covering synthesis, verification and test.
I am the head of the group of computer architecture. The main focus of the group is the development and application of CAD tools in circuit design. The research areas range from system descriptions in SystemC over test and verification down to synthesis.
I'm the technical assistent of the group computer architecture. I'm responsible for all computers at our group and consulting our members and students.
I am working as lecturer and research assistent in the area of evolutionary algorithms and applications. The considered approaches are mainly taken from the world of digital circuit design.
My field of activity is the Satisfiability-Problem (SAT). One main focus of my research interests is the efficient solving of SAT-instances. The other main focus is located in the field of 'Test of digital circuits'. In this field I analyse the generation of test pattern for dynamic fault models on basis of the Satisfiability-Problem.
Exercises and tutorial lessons are simply important - computer scientists have to know how their machines work.
The other main focus is research - formal verification of circuits must become easier! So far designs are rarely formally verified - too difficult - this is to be changed ...
Until now I was interested in heuristic and exact optimization procedures in logic synthesis. Actually my research interests are focused on analyzing and debugging of circuits.
My research is the robustness check of digital circuits with use of formal methods. The features sizes in VLSI circuits shrinking continuously. The circuits gets more and more vulnerable against transient faults. The currently developed methods of robustness verification have to be improved for real-world applications.
My role in the the work-group is about developing techniques for design-space exploration and visualization. These techniques are priory used in hardware-software co-design, to develop integrated environments which optimize the VLSI-CAD.
My research interest is formal verification of circuits. The goal of formal
verification is to prove the correctness of circuits (in contrast to simulation
based approaches whose limitations were highlighted e.g. by the Pentium Bug).
Especially, I examine how information of high-level descriptions can be used
effectively in the formal verification process. Thereby the system description
language SystemC plays an important role.
In my work I integrate contextual knowledge into system-level verification. This is done by using and extending word-level solvers and combining them with current verification approaches.
My research interest is the application of constraint programming techniques, such as arc-consistency, in the area of SMT-solving. In particular, I am trying to combine bit vector logic with the SAT problem.
My main focus lies on the one hand in research and there specially in the technical documentation and formal specification from circuits and systems on the other hand in care of courses and seminars in basic and main studies.
My research is mainly about formal verification. In particular, I am working on the verification of micro processors. I am studying how to automate the verification and make it easier to handle.
My principally research interests cover the subject areas of the satisfiability problem (SAT) and the optimization of false path analysis as well as the study of crosstalks.
In the work-group I am working on the examination of Boolean Satisfiability
(SAT) on different layers of abstraction. Furthermore, my research is about ATPG and LBIST.
The focus of my research is automation in debugging and diagnosis of reliable systems. Formal verification and semi-formal methods are studied in this area.
In the past, my research interest has been SAT-Solving. Now, at the group of computer architecture, I mainly focus on Automatic Test Pattern Generation. Goal is to combine these two techniques.
My main research focus is on reversible logic which shows promising applications e.g. in the area of low-power design and quantum computation. However, till today no design flow for reversible logic exists - this must be changed. In particular, approaches for synthesis, verification, and debugging need improvements. Besides that, I am trying to improve the existing SAT- and SMT-solvers and their application in formal hardware verification.
I am Fachinformatikerin in the emphasis application development specialized in Multimedia. I concern myself primarily with design and the development from websites based on CMS.
