The Group of Computer Architecture, the Group of Reliable Embedded Systems and Group of Computer Engineering and IT-Security offer lectures in the area of computer aided design of circuits and systems for students on bachelor- and master-level. Beside the lectures for graduate and undergraduate students, we run student team projects to enforce research oriented learning. In research the groups are successful in Computer Aided Design (CAD) of circuits and systems covering synthesis, verification, test and reliability.
I am the head of the group of computer architecture. The main focus of the group is the development and application of CAD tools in circuit design. The research areas range from system descriptions in SystemC over test and verification down to synthesis.
Since March 2012 I am heading the Group of Reliable Embedded Systems under a cooperative professor ship associated to leading the Department of Avionics Systems at the Institute of Space Systems of the German Aerospace Center (DLR).
Since October 2015 I'm the head of the Group on Computer Engineering and IT-Security (Embedded Security) that was established as part of the
initiative of excellence to strengthen the cooperation between the University of Bremen and the German Research Center for Artificial Intelligence.
Together with Birthe Semken I work as team assistant in the Group for Computer Architecture. I am responsible for all issues concerning the administration of the group. In particular, I administrate the projects funded by third parties.
Together with Regine Janssen I work as team assistant in the Group for Computer Architecture.
I am responsible for all issues concerning the administration of the group. In particular, I plan and process the official journeys of the group members.
I had my BSc. and MSc. Degree from the university of Baghdad before I work as a university instructor in my home country. Now, I'm a scholarship holder to get the PhD. degree, and my research is focused on employing Hardware Description Languages for Reversible Logic Circuit Synthesis.
Reliability is great concern in space-systems due to the lack of physical access, high costs of a space-launch and ionizing radiation from the sun. Especially the latter leads to transient and permanent changes on digital circuits which eventually leads to unwanted behavior.
My research interests lie in fault-tolerance techniques for digital systems at gate- as well as system-level by using hardware-software interaction.
My focus of research is highly reliable embedded systems, from both hardware and software viewpoints. In particular I look into the architectural aspects of embedded processors and how reliability can be incorporated into hardware-software co-design. Besides I am also interested in high level synthesis.
My field of activity is the Satisfiability-Problem (SAT). One main focus of my research interests is the efficient solving of SAT-instances. The other main focus is located in the field of 'Test of digital circuits'. In this field I analyse the generation of test pattern for dynamic fault models on basis of the Satisfiability-Problem.
My research focus is on "Design Understanding".
I am studying how to support developers in understanding an unknown or new design. The goal is to simplify training of new team members or debugging of the design. Formal methods known from property checking will be used for automation.
My research interest is system level design and verification. Currently I am working on systemC designs visualization for understanding of a given system.The problem is that the extraction of data from system designs written in SystemC is thereby crucial. In order to address this, information of a given system which are static and dynamic information is being retrieved by controlling and monitoring the executing of the elaboration phase of the model.
I received my Master and PhD degrees from the University of Sao Paulo in Brazil, where I have worked on reconfigurable computing, networks-on-chip (NoC), and AI algorithms. Currently, I am working on the development of complex swarm systems, a new system paradigm which is characterized by a large number of heterogeneous components that dynamically change their structure and, by this, open new possibilities for the development of many novel applications.
My research interest is formal verification of circuits. The goal of formal
verification is to prove the correctness of circuits (in contrast to simulation
based approaches whose limitations were highlighted e.g. by the Pentium Bug).
Especially, I examine how information of high-level descriptions can be used
effectively in the formal verification process. Thereby the system description
language SystemC plays an important role.
I work in the domain of Educational Psychology and investigate topics of learning and instruction. My present work focuses on supporting learners to solve mathematical problems which are presented within a real context. For this purpose, methods are developed and their effectiveness is tested experimentally. Various methods are considered, ranging from fostering reading competencies to discussing common errors.
My research focus is on ESL design, verification and (virtual) prototyping. The methodology enables the designer to efficiently, and cost-effectively optimize the design in comparison to RTL methodology.
The main question I am trying to answer is if the software performs as expected (in terms of correctness and efficiency) on the target architecture, and if the architecture is capable to give the advertised functionality
I am interested in the verification of systems on high levels of abstraction.
My current research focus is on fully automatic formal methods for property checking as well as bug hunting in SystemC (TLM) models.
The inherent concurrency of the models in combination with the large input space, requires sophisticated proof techniques.
My activity is focused on the development of algorithms for high-quality test set generation for digital circuits. An important aspect of my work lies in the integration and profitable use of structural knowledge about the design under test within formal proof techniques, which are applied by the test computation process.
I work on natural language processing (NLP) of german and english texts to create formal descriptions of systems. I use these descriptions to perform formally verify the system.
Furthermore I work on reversible logic and biochips.
My research area is the formal verification of systems at high levels of abstraction. Currently the focus is the development of an automated formal verification flow for SystemC TLM designs integrating property checking, debugging, and coverage analysis.
My research focuses on power aware design, especially at the system level. In the nearby future, embedded designs will require to be thought of as the result of both functionality and power requirements and will require a unified workflow. The idea is to use modern techniques to aid the development of this integrated workflow for different application scenarios.
I am interested in systems temporal behaviour modeling and verification. The problem I am currently addressing is to formally verify that a system fulfills its Real-Time specifications. As software nowadays is held responsible for the most critical bugs in embedded systems, I am investigating how to prove meeting certain software Real-Time specifications, given hardware models and Real-Time environment simulators.
I am working on quantum circuits and reversible logic. My investigations
focus on data structures that allow for the representation of larger
functions in an efficient way and, at the same time, can be used for the
synthesis of corresponding circuits.
My research focus is on the formal verification of arithmetic floating-point designs. In particular, I am developing appropriate formal verification techniques for decimal floating-point designs. As decimal floating-point is a quite recent addition to the IEEE Standard for Floating-Point Arithmetic (IEEE Std754-2008), new verification technologies are needed to verify the compliance of hardware designs with the standard.
The main field of my work is test generation in the design flow of digital circuits and systems. Here I am working on methods for both full and compact test generation for production test as well as for the validation of the design process at high levels of abstraction. In particular, I am working with formal proof techniques.
My area of research focuses on Web/Mobile-based learning application, specially semantic m-based learning app. I am currently working on enhancement of students' performance who want to learn complex combination of Logic Units and Verilog programming language via semantic mobile application.
I am working in the area of solving optimization problems using probabilistic techniques such as evolutionary algorithms (EAs). In particular, I am aiming for applying these concepts in order to solve multi-objective optimization (MOO) problems which frequently occur in electronic design automation. My vision is to integrate them in existing design flows in a more comprehensive fashion.
The main focus of my research activities is the analysis of description languages for hardware/software design. Major questions are how such hybrid systems can be visualized and what technical prerequisites need to be satisfied for this purpose.
In the context of the graduate school „System Design“ I'm researching simulation and formal verification of failure tolerant systems. Due to single transistors becoming smaller and requiring less voltage with each passing generation, it becomes more probable that a signal changes by outer influence like cosmic rays. For this reason, failure tolerance takes an important role in the design of new systems. Failure tolerance is meant to ensure that such a fault in a signal does not lead to an error that's visible for the user. In this context I specifically examine the processor Leon3.
My main research focus is on reversible logic which shows promising applications e.g. in the area of low-power design and quantum computation. However, till today no design flow for reversible logic exists - this must be changed. In particular, approaches for synthesis, verification, and debugging need improvements. Besides that, I am trying to improve the existing SAT- and SMT-solvers and their application in formal hardware verification.