The Group of Computer Architecture offer lectures in the area of computer aided design of circuits and systems for students on bachelor- and master-level. Beside the lectures for graduate and undergraduate students, we run student team projects to enforce research oriented learning. In research the groups are successful in Computer Aided Design (CAD) of circuits and systems covering synthesis, verification, test and reliability.
I am the head of the group of computer architecture. The main focus of the group is the development and application of CAD tools in circuit design. The research areas range from system descriptions in SystemC over test and verification down to synthesis.
Together with Birthe Semken I work as team assistant in the Group for Computer Architecture. I am responsible for all issues concerning the administration of the group. In particular, I administrate the projects funded by third parties.
Together with Regine Janssen I work as team assistant in the Group for Computer Architecture.
I am responsible for all issues concerning the administration of the group. In particular, I plan and process the official journeys of the group members.
I contribute to establish a data exchange format specification for the screening data that are generated by the Collaborative Research Center SFB1232.
On the basis of that, I develop parsing and handling routines as well as a database structure and implement a web interface for end users.
I had my BSc. and MSc. Degree from the university of Baghdad before I work as a university instructor in my home country. Now, I'm a scholarship holder to get the PhD. degree, and my research is focused on employing Hardware Description Languages for Reversible Logic Circuit Synthesis.
My focus of research is highly reliable embedded systems, from both hardware and software viewpoints. In particular I look into the architectural aspects of embedded processors and how reliability can be incorporated into hardware-software co-design. Besides I am also interested in high level synthesis.
My field of research is low power Design For Test (DFT) for integrated circuits. The identification of risky and vulnerable test patterns is very important for a reliable post-production test. Therefore, my work focuses on the development of a test pattern analysis methodology within this field.
My field of activity is the Satisfiability-Problem (SAT). One main focus of my research interests is the efficient solving of SAT-instances. The other main focus is located in the field of 'Test of digital circuits'. In this field I analyse the generation of test pattern for dynamic fault models on basis of the Satisfiability-Problem.
My research focus is on "Design Understanding".
I am studying how to support developers in understanding an unknown or new design. The goal is to simplify training of new team members or debugging of the design. Formal methods known from property checking will be used for automation.
My research interest is system level design and verification. Currently I am working on SystemC designs visualization for understanding of a given system. The problem is that the extraction of data from system designs written in SystemC is crucial. It brings this challenge that how can both, the structure and the behavior of a given SystemC design be retrieved without restricting the language means and/or modifying the existing infrastructures?
I work in the domain of Educational Psychology and investigate topics of learning and instruction. My present work focuses on supporting learners to solve mathematical problems which are presented within a real context. For this purpose, methods are developed and their effectiveness is tested experimentally. Various methods are considered, ranging from fostering reading competencies to discussing common errors.
My research interest is formal verification of circuits. The goal of formal
verification is to prove the correctness of circuits (in contrast to simulation
based approaches whose limitations were highlighted e.g. by the Pentium Bug).
Especially, I examine how information of high-level descriptions can be used
effectively in the formal verification process. Thereby the system description
language SystemC plays an important role.
I am interested in the verification of systems on high levels of abstraction.
My current research focus is on fully automatic formal methods for property checking as well as bug hunting in SystemC (TLM) models.
The inherent concurrency of the models in combination with the large input space, requires sophisticated proof techniques.
My activity is focused on the development of algorithms for high-quality test set generation for digital circuits. An important aspect of my work lies in the integration and profitable use of structural knowledge about the design under test within formal proof techniques, which are applied by the test computation process.
My research topics are Information- and Network Security. My research focus is
‘Adaptive Network Security Services in virtualized Networks’. I am also active in
the field of Digital Computer Forensics, here especially in the topic of ‘Digital
Forensic Readyness’. I have a professorship at the Norwegian University of
Science and Technology (NTNU) in Network Security.
I work on natural language processing (NLP) of german and english texts to create formal descriptions of systems. I use these descriptions to perform formally verify the system.
Furthermore I work on reversible logic and biochips.
My research focuses on the optimization of robotic software to hardware deployment mainly driven through formalized nonfunctional requirements.
This includes as well basic research on the domains of software component profiling on different architectures as well as the semantic analysis of software component networks.
My research area is the formal verification of systems at high levels of abstraction. Currently the focus is the development of an automated formal verification flow for SystemC TLM designs integrating property checking, debugging, and coverage analysis.
My research focuses on power aware design, especially at the system level. In the nearby future, embedded designs will require to be thought of as the result of both functionality and power requirements and will require a unified workflow. The idea is to use modern techniques to aid the development of this integrated workflow for different application scenarios.
My field of research is formal verification and debugging of gate-level arithmetic circuits specially large and complex multipliers and dividers. These circuits play an important role in different applications, and they usually consist of millions of gates. The idea is to take advantage of fast and scalable methods (e.g. computer algebra) to verify circuits, localize the faults, and make the buggy parts correct.
I am interested in systems temporal behaviour modeling and verification. The problem I am currently addressing is to formally verify that a system fulfills its Real-Time specifications. As software nowadays is held responsible for the most critical bugs in embedded systems, I am investigating how to prove meeting certain software Real-Time specifications, given hardware models and Real-Time environment simulators.
My main research area is the verification of cryptographic security properties. In researching this topic I combine my interest for cryptology, algebra, number theory, logics and proof techniques, in order to find holistic security proofs that are relevant and applicable in practice.
My area of research focuses on Web/Mobile-based learning application, specially semantic m-based learning apps. I am currently working on enhancement of students' performance who want to learn complex combination of Logic Circuits and Verilog programming language via semantic mobile application.
I am working in the area of solving optimization problems using probabilistic techniques such as evolutionary algorithms (EAs). In particular, I am aiming for applying these concepts in order to solve multi-objective optimization (MOO) problems which frequently occur in electronic design automation. My vision is to integrate them in existing design flows in a more comprehensive fashion.
The main focus of my research activities is the analysis of description languages for hardware/software design. Major questions are how such hybrid systems can be visualized and what technical prerequisites need to be satisfied for this purpose.
My research topic is algorithm design for synthesis and optimization of classical and emerging computer technologies. For this purpose I apply both heuristic and exact approaches. Besides CMOS, I have got experiences in the fields of Reversible Logic, Quantum Computing, DNA Computing, and Optical Computing, Digital Microfluidic Biochips (DMFB) as well as Quantum-dot Cellular Automata (QCA).
My main research focus is on reversible logic which shows promising applications e.g. in the area of low-power design and quantum computation. However, till today no design flow for reversible logic exists - this must be changed. In particular, approaches for synthesis, verification, and debugging need improvements. Besides that, I am trying to improve the existing SAT- and SMT-solvers and their application in formal hardware verification.
I am professor at the UFMG (Brazil). My research focus is on reversible circuits based on the nanotechnology Quantum-dot Cellular Automata (QCA), Low Power techniques for integrated circuits, and Cross-layer reliable system design.