The Group of Computer Architecture and the Group of Reliable Embedded Systems offer lectures in the area of computer aided design of circuits and systems for students on bachelor- and master-level. Beside the lectures for graduate and undergraduate students, we run student team projects to enforce research oriented learning. In research the groups are successful in Computer Aided Design (CAD) of circuits and systems covering synthesis, verification, test and reliability.
I am the head of the group of computer architecture. The main focus of the group is the development and application of CAD tools in circuit design. The research areas range from system descriptions in SystemC over test and verification down to synthesis.
Since March 2012 I am heading the Group of Reliable Embedded Systems under a cooperative professor ship associated to leading the Department of Avionics Systems at the Institute of Space Systems of the German Aerospace Center (DLR).
Together with Birthe Semken I work as team assistant in the Group for Computer Architecture. I am responsible for all issues concerning the administration of the group. In particular, I administrate the projects funded by third parties.
Together with Regine Janssen I work as team assistant in the Group for Computer Architecture.
I am responsible for all issues concerning the administration of the group. In particular, I plan and process the official journeys of the group members.
My main focus lies in the research field of "reversible logic and quantum computing". In particular, I am interested in the optimization of reversible and quantum circuits in terms of costs, number of gates, depth, and complexity.
Reliability is great concern in space-systems due to the lack of physical access, high costs of a space-launch and ionizing radiation from the sun. Especially the latter leads to transient and permanent changes on digital circuits which eventually leads to unwanted behavior.
My research interests lie in fault-tolerance techniques for digital systems at gate- as well as system-level by hardware-software interaction. I take part in the Graduate School System Design and am FPGA designer in the Avionics group of DLR Bremen.
My research interests lie in the area of system-level design and verification. Currently I focus on developing new simulative methods for System-On-Chip (SoC) verification at higher level of abstraction.
My field of activity is the Satisfiability-Problem (SAT). One main focus of my research interests is the efficient solving of SAT-instances. The other main focus is located in the field of 'Test of digital circuits'. In this field I analyse the generation of test pattern for dynamic fault models on basis of the Satisfiability-Problem.
I work in the domain of Educational Psychology and investigate topics of learning and instruction. My present work focuses on supporting learners to solve mathematical problems which are presented within a real context. For this purpose, methods are developed and their effectiveness is tested experimentally. Various methods are considered, ranging from fostering reading competencies to discussing common errors.
I work on natural language processing (NLP) of german and english texts to create formal descriptions of systems. I use these descriptions to perform formally verify the system.
Furthermore I work on reversible logic and biochips.
My research area is the formal verification of systems at high levels of abstraction. Currently the focus is the development of an automated formal verification flow for SystemC TLM designs integrating property checking, debugging, and coverage analysis.
My previous research were in the area of automatic testing and automatic test case generation.
In the work-group, I am working in the area of automatic debugging of embedded systems. In particular the analysis of the data-flow.
I am working on quantum circuits and reversible logic. My investigations
focus on data structures that allow for the representation of larger
functions in an efficient way and, at the same time, can be used for the
synthesis of corresponding circuits.
There is a gap each between the natural language description of a system, its formal description and its implementation, which leads to incorrectness in system development processes. Within the graduate school “system design” I deal with trying to close these gaps one with (semi-) automatic natural language processing and the other with code generation from formal descriptions (like UML).
The development of correct and reliable concurrent programs is tedious and error-prone. Failures may show up only under very specific
interleavings of the execution threads. Similarly the field of concurrent programming lacks tool support for the needs of programmers. My research focuses on the design of automatic debugging methods for concurrent programs, including the detection of failures, the localization of the corresponding faults, and finally the repair of the programs.
My research focus is on the formal verification of arithmetic floating-point designs. In particular, I am developing appropriate formal verification techniques for decimal floating-point designs. As decimal floating-point is a quite recent addition to the IEEE Standard for Floating-Point Arithmetic (IEEE Std754-2008), new verification technologies are needed to verify the compliance of hardware designs with the standard.
The focus of my research is on reversible logic, which e.g. provides the basis for quantum computing and shows promising applications in the area of low-power design. In particular, I study the synthesis of reversible circuits based on hardware description languages. Besides that, I am involved in teaching.
My research interests cover solving complex problems using Boolean satisfiability algorithms. In particular, I investigate how techniques such as massive parallelism can be exploited for increasing performance.
In the context of the graduate school „System Design“ I'm researching simulation and formal verification of failure tolerant systems. Due to single transistors becoming smaller and requiring less voltage with each passing generation, it becomes more probable that a signal changes by outer influence like cosmic rays. For this reason, failure tolerance takes an important role in the design of new systems. Failure tolerance is meant to ensure that such a fault in a signal does not lead to an error that's visible for the user. In this context I specifically examine the processor Leon3.
My main research focus is on reversible logic which shows promising applications e.g. in the area of low-power design and quantum computation. However, till today no design flow for reversible logic exists - this must be changed. In particular, approaches for synthesis, verification, and debugging need improvements. Besides that, I am trying to improve the existing SAT- and SMT-solvers and their application in formal hardware verification.
My research interest is mainly on visualization of circuits specified in Hardware Description Languages. Currently, I am focusing on the development of visualization methods for hardware systems described in ¨higher"levels.