The Group of Computer Architecture offer lectures in the area of computer aided design of circuits and systems for students on bachelor- and master-level. Beside the lectures for graduate and undergraduate students, we run student team projects to enforce research oriented learning. In research the groups are successful in Computer Aided Design (CAD) of circuits and systems covering synthesis, verification, test and reliability.
I am the head of the group of computer architecture. The main focus of the group is the development and application of CAD tools in circuit design. The research areas range from system descriptions in SystemC over test and verification down to synthesis.
Together with Birthe Semken I work as team assistant in the Group for Computer Architecture. I am responsible for all issues concerning the administration of the group. In particular, I administrate the projects funded by third parties.
Together with Regine Janssen I work as team assistant in the Group for Computer Architecture.
I am responsible for all issues concerning the administration of the group. In particular, I plan and process the official journeys of the group members.
The focus of my research lies in the field of natural language processing (NLP). Therefore, artificial intelligence, computational linguistics and machine learning are important aspects of my work. The goal is to fill as many gaps in linguistic research with intelligent systems that can be applied in everyday life.
I am concerned with Approximate Computing and Artificial Intelligence (AI). In particular, I am trying to develop methods to incorporate Approximate Computing techniques into AI algorithms such that the benefit from the use of Approximate Computing is maximized. At the same time, it must be ensured that the functionality of the AI is guaranteed.
I work in the domain of Educational Psychology and investigate topics of learning and instruction. My present work focuses on supporting learners to solve mathematical problems which are presented within a real context. For this purpose, methods are developed and their effectiveness is tested experimentally. Various methods are considered, ranging from fostering reading competencies to discussing common errors.
My research interest is formal verification of circuits. The goal of formal
verification is to prove the correctness of circuits (in contrast to simulation
based approaches whose limitations were highlighted e.g. by the Pentium Bug).
Especially, I examine how information of high-level descriptions can be used
effectively in the formal verification process. Thereby the system description
language SystemC plays an important role.
My research mainly aims to the development of solutions to enhance the testability of integrated circuits and to improve the quality of the manufacturing test. In this regard, I am modeling state-of-the-art test access mechanisms on system-level, which allows me to orchestrate formal methods yielding to an optimization of certain characteristics already in an early design phase.
I am interested in the verification of systems on high levels of abstraction.
My current research focus is on fully automatic formal methods for property checking as well as bug hunting in SystemC (TLM) models.
The inherent concurrency of the models in combination with the large input space, requires sophisticated proof techniques.
My activity is focused on the development of algorithms for high-quality test set generation for digital circuits. An important aspect of my work lies in the integration and profitable use of structural knowledge about the design under test within formal proof techniques, which are applied by the test computation process.
My research is focussed on the combination of IT security and artificial intelligence. Hence, I am particularly interested in how AI can be used to secure IT systems by analysing these systems and identifying threats, potential risks or attacks. Furthermore, the definition of appropriate security goals and mechanisms has to be based on this knowledge.
My research topics are Information- and Network Security. My research focus is
‘Adaptive Network Security Services in virtualized Networks’. I am also active in
the field of Digital Computer Forensics, here especially in the topic of ‘Digital
Forensic Readyness’. I have a professorship at the Norwegian University of
Science and Technology (NTNU) in Network Security.
My research focuses on the optimization of robotic software to hardware deployment mainly driven through formalized nonfunctional requirements.
This includes as well basic research on the domains of software component profiling on different architectures as well as the semantic analysis of software component networks.
My research area is the formal verification of systems at high levels of abstraction. Currently the focus is the development of an automated formal verification flow for SystemC TLM designs integrating property checking, debugging, and coverage analysis.
My research focuses on power aware design, especially at the system level. In the nearby future, embedded designs will require to be thought of as the result of both functionality and power requirements and will require a unified workflow. The idea is to use modern techniques to aid the development of this integrated workflow for different application scenarios.
My field of research is formal verification and debugging of gate-level arithmetic circuits specially large and complex multipliers and dividers. These circuits play an important role in different applications, and they usually consist of millions of gates. The idea is to take advantage of fast and scalable methods (e.g. computer algebra) to verify circuits, localize the faults, and make the buggy parts correct.
I am interested in systems temporal behaviour modeling and verification. The problem I am currently addressing is to formally verify that a system fulfills its Real-Time specifications. As software nowadays is held responsible for the most critical bugs in embedded systems, I am investigating how to prove meeting certain software Real-Time execution specifications.
As part of the Collaborative Research Center EASE I am focusing on formal verification and optimization of plans for autonomous robots. In addition, my interests lie in the areas of automated reasoning and mathematical optimization.
I am working on quantum circuits and reversible logic. My investigations
focus on data structures that allow for the representation of larger
functions in an efficient way and, at the same time, can be used for the
synthesis of corresponding circuits.
My main research area is the verification of cryptographic security properties. In researching this topic I combine my interest for cryptology, algebra, number theory, logics and proof techniques, in order to find holistic security proofs that are relevant and applicable in practice.
My area of research focuses on Computer Science Education, specially Interactive Educational systems. I am currently working on enhancement of students' performance who want to learn programming languages via visual programming environments in the context of smart environments.
The main focus of my research activities is the analysis of description languages for hardware/software design. Major questions are how such hybrid systems can be visualized and what technical prerequisites need to be satisfied for this purpose.
My research topic is algorithm design for synthesis, optimization, and layout of classical and emerging computer technologies. For this purpose I apply both heuristic and exact approaches. Besides CMOS, my experiences are in the fields of Reversible Logic, Quantum Computing, DNA Computing, and Optical Computing, Digital Microfluidic Biochips (DMFB) as well as Quantum-dot Cellular Automata (QCA) and Nanomagnet Logic (NML).
My main research focus is on reversible logic which shows promising applications e.g. in the area of low-power design and quantum computation. However, till today no design flow for reversible logic exists - this must be changed. In particular, approaches for synthesis, verification, and debugging need improvements. Besides that, I am trying to improve the existing SAT- and SMT-solvers and their application in formal hardware verification.