Since October 2001 Prof. Dr. Rolf Drechsler is the head of the group of computer architecture. Beside the lectures for graduate and undergraduate students, in the research field we are active in different areas of VLSI CAD covering synthesis, verification and test.
I am the head of the group of computer architecture. The main focus of the group is the development and application of CAD tools in circuit design. The research areas range from system descriptions in SystemC over test and verification down to synthesis.
Since July 2010 I am head of a junior research group located within the Group of Computer Architecture. Within the areas test and verification, the junior research group is mainly focussing on robustness analysis and new debugging approaches for circuits and systems.
My business particularly includes the administrative support of research funding. Besides that, I also take care of all organizational and administrational tasks.
I'm the technical assistent of the group computer architecture. I'm responsible for all computers at our group and consulting our members and students.
My research interests cover the improvement of the the SMT solvers in order to make it run faster in solving complex algorithms using parallel programming techniques and so taking the advantages of the existing multi-core parallel architectures.
My research interests lie in the area of system-level design and verification. Currently I focus on developing new simulative methods for System-On-Chip (SoC) verification at higher level of abstraction.
My scope is the timing analysis of digital circuits with the focus on the efficient identification of false paths or the generation of stimuli for specific paths, respectively.
In particular, I investigate and develop approaches based on formal methods. These methods promise a high degree of robustness which is very important for practical use.
My research area is (formal) verification at the
Electronic System Level (ESL). In particular, the focus is on descriptions at higher levels of abstraction.
I am working as lecturer and research assistent in the area of evolutionary algorithms and applications. The considered approaches are mainly taken from the world of digital circuit design.
My field of activity is the Satisfiability-Problem (SAT). One main focus of my research interests is the efficient solving of SAT-instances. The other main focus is located in the field of 'Test of digital circuits'. In this field I analyse the generation of test pattern for dynamic fault models on basis of the Satisfiability-Problem.
Until now I was interested in heuristic and exact optimization procedures in logic synthesis. Actually my research interests are focused on analyzing and debugging of circuits.
My research is about robustness check of digital circuits with use of formal methods. The features sizes in VLSI circuits shrinking continuously. Thus, circuits becoming more and more vulnerable against transient faults. The currently developed methods of robustness verification have to be improved for real-world applications.
My research interest is formal verification of circuits. The goal of formal
verification is to prove the correctness of circuits (in contrast to simulation
based approaches whose limitations were highlighted e.g. by the Pentium Bug).
Especially, I examine how information of high-level descriptions can be used
effectively in the formal verification process. Thereby the system description
language SystemC plays an important role.
In my work I integrate contextual knowledge into system-level verification. This is done by using and extending word-level solvers and combining them with current verification approaches.
My main focus lies on the one hand in research and there specially in the technical documentation and formal specification from circuits and systems on the other hand in care of courses and seminars in basic and main studies.
My research is mainly about formal verification. In particular, I am working on the verification of micro processors. I am studying how to automate the verification and make it easier to handle.
My research area is the formal verification of systems at high levels of abstraction. Currently the focus is the development of an automated formal verification flow for SystemC TLM designs integrating property checking, debugging, and coverage analysis.
My previous research were in the area of automatic testing and automatic test case generation.
In the work-group, I am working in the area of automatic debugging of embedded systems. In particular the analysis of the data-flow.
My research is based on the analysis and the verification of software and hardware. Currently the focus are SystemC-based models interacting with real hardware.
The development of correct and reliable concurrent programs is tedious and error-prone. Failures may show up only under very specific
interleavings of the execution threads. Similarly the field of concurrent programming lacks tool support for the needs of programmers. My research focuses on the design of automatic debugging methods for concurrent programs, including the detection of failures, the localization of the corresponding faults, and finally the repair of the programs.
My research is about formal verification at the Electronic System Level, which considers systems at a higher level of abstraction. I am also interested in reversible logics and quantum computing.
In the work-group I am working on formal verification of models that are used for the specification of systems such as UML. Furthermore, I am interested in reversible logic and quantum computing.
The main focus of my research activities is the analysis of description languages for hardware/software design. Major questions are how such hybrid systems can be visualized and what technical prerequisites need to be satisfied for this purpose.
The focus of my research is automation in debugging and diagnosis of reliable systems. Formal verification and semi-formal methods are studied in this area.
My research interests cover solving complex problems using Boolean satisfiability algorithms. In particular, I investigate how techniques such as massive parallelism can be exploited for increasing performance.
In general I am interested in topics of Human-Computer Interaction (HCI) as the creation of user interfaces, the development of novel interaction techniques, their implementation and evaluation. In the working group I am concentrating on the development of a user-friendly debugging interface.
My main research focus is on reversible logic which shows promising applications e.g. in the area of low-power design and quantum computation. However, till today no design flow for reversible logic exists - this must be changed. In particular, approaches for synthesis, verification, and debugging need improvements. Besides that, I am trying to improve the existing SAT- and SMT-solvers and their application in formal hardware verification.
My research interest is mainly on visualization of circuits specified in Hardware Description Languages. Currently, I am focusing on the development of visualization methods for hardware systems described in ¨higher"levels.
I am Fachinformatikerin in the emphasis application development specialized in Multimedia. I concern myself primarily with design and the development from websites based on CMS.
