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» Improving SAT solving using Monte Carlo Tree Search-based Clause Learning




Author:

Oliver Keszöcze, Kenneth Schmitz, Jens Schloeter, Rolf Drechsler
Workshop:
13th International Workshop on Boolean Problems (IWSBP)
Reference:

Bremen, Germany, 2018
Hyperlink:

[Link to the Workshop]



» ConfidenceSat: A Parallel SAT Solver with Conflict Clause Handling




Author:

Kenneth Schmitz, Oliver Keszöcze, Jil Tietjen and Rolf Drechsler
Workshop:
13th International Workshop on Boolean Problems (IWSBP)
Reference:

Bremen, Germany, 2018
Hyperlink:

[Link to the Workshop]



» Towards Self-Explaining Digital Systems: A Design Methodology for the Next Generation




Author:

Rolf Drechsler, Christoph Lüth, Goerschwin Fey, Tim Güneysu
Workshop:
3nd International Verification and Security Workshop (IVSW)
Reference:

Costa Brava, Spain, 2018
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» Evaluation of Power State Cross Coverage in Firmware-Based Power Management




Author:

Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop:
Embedded Software for Industrial IoTs (ESIIT)
Reference:

Dresden, Germany, 2018
Hyperlink:

[Link to the Workshop]



» Towards Automated Refinement of TLM Properties to RTL




Author:

Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop:
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference:

Tübingen, Germany, 2018
Hyperlink:

[Link to the Workshop]



» A Codeword-based Compaction Technique for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks




Author:

Sebastian Huhn, Marcel Merten, Stephan Eggersglüß and Rolf Drechsler
Workshop:
30. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2018)
Reference:

Freiburg (Breisgau), Germany, 2018
Hyperlink:

[Link to the Workshop]
PDF:

[click here]



» ATPG Constraint Analysis for Reducing Regional Power Activity




Author:

Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen
Workshop:
30. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2018)
Reference:

Freiburg (Breisgau), Germany, 2018
Hyperlink:

[Link to the Workshop]



» Time-stamps for Hardware Simulation Models Accurate Time-back Annotation




Author:

Rehab Massoud, Jannis Stoppe, Karthik Maddikunta, Rolf Drechsler
Workshop:
5th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference:

Dresden, Germany, 2018
Hyperlink:

[Link to the Workshop]



» Execution Environment for Dynamic Software Runtime Examination




Author:

Kenneth Schmitz, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Workshop:
5th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference:

Dresden, Germany, 2018
Hyperlink:

[Link to the Workshop]



» A Lightweight Method for Transient Test Power Pattern Analysis for Pattern Selection




Author:

Harshad Dhotre, Stephan Eggersglüß
Workshop:
29. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2017)
Reference:

Lübeck, Germany, 2017
Hyperlink:

[Link to the Workshop]



» Making Waveforms Great Again




Author:

Jannis Stoppe and Rolf Drechsler
Workshop:
4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[Link to the Workshop]



» A Human-Centered Approach to Routing for Digital Microfluidic Biochips




Author:

Oliver Keszöcze, Andre Pols and Rolf Drechsler
Workshop:
4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[Link to the Workshop]



» Verilog2GEXF - Dynamic Large Scale Circuit Visualization




Author:

Kenneth Schmitz, Jannis Stoppe, Rolf Drechsler
Workshop:
4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[Link to the Workshop]



» Computing Exact Fault Candidates Incrementally




Author:

Heinz Riener, Görschwin Fey
Workshop:
4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[Link to the Workshop]



» Mining Latency Guarantees for RT-level Designs




Author:

Jan Malburg, Heinz Riener, Görschwin Fey
Workshop:
4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[Link to the Workshop]



» Revisiting Symbolic Software-implemented Fault Injection




Author:

Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
Workshop:
2nd International Workshop on Resiliency in Embedded Electronic Systems (REES)
Reference:

Lausanne, Switzerland, 2017
Hyperlink:

[Link to the Workshop]



» Der Einfluss von Zellformen auf das Routing von Digital Microfluidic Biochips




Author:

Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Workshop:
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference:

Bremen, Germany, 2017
Hyperlink:

[Link to the Workshop]



» Exakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate Computing




Author:

Saman Fröhlich, Daniel Große, Rolf Drechsler
Workshop:
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference:

Bremen, Germany, 2017
Hyperlink:

[Link to the Workshop]



» Counterexample-Guided EF Synthesis of Boolean Functions




Author:

Heinz Riener, Rüdiger Ehlers, Görschwin Fey
Workshop:
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference:

Bremen, Germany, 2017
Hyperlink:

[Link to the Workshop]



» Using Lightweight Containers in Hardware/Software Co-Design for Security




Author:

Daniel Große, Kenneth Schmitz, Rolf Drechsler
Workshop:
Workshop on Computer-Aided Design and Implementation for Cryptography and Security (CADICS)
Reference:

Austin, USA, 2016
Hyperlink:

[Link to the Workshop]



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