» Induction-based Formal Verification of SystemC TLM Designs
|
|
|
|
Author:
|
|
Daniel Große, Hoang M. Le, Rolf Drechsler |
| Workshop: |
|
10th International Workshop on Microprocessor Test and Verification (MTV) |
Reference:
|
| Austin, Texas, 2009
|
Hyperlink:
|
| [Link to the Workshop]
|
» Using QBF to Increase the Accuracy of SAT-Based Debugging
|
|
|
|
Author:
|
|
Andre Sülflow, Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
International Workshop on Constraints in Formal Verification (CFV) |
Reference:
|
| Grenoble, France, 2009
|
PDF:
|
| [click here]
|
Hyperlink:
|
| [Link to the Workshop]
|
» Reducing Reversible Circuit Cost by Adding Lines
|
|
|
|
Author:
|
|
D. Michael Miller, Robert Wille, Rolf Drechsler |
| Workshop: |
|
International Workshop on Logic Synthesis (IWLS) |
Reference:
|
| Berkeley, 2009
|
Hyperlink:
|
| [Link to the Workshop]
|
» Synthesis of Reversible Functions Beyond Gate Count and Quantum Cost
|
|
|
|
Author:
|
|
Robert Wille, Mehdi Saeedi, Rolf Drechsler |
| Workshop: |
|
International Workshop on Logic Synthesis (IWLS) |
Reference:
|
| Berkeley, 2009
|
PDF:
|
| [click here]
|
Hyperlink:
|
| [Link to the Workshop]
|
» Model-Based Diagnosis for Programmable Logic Controllers
|
|
|
|
Author:
|
|
Andre Sülflow, Rolf Drechsler |
| Workshop: |
|
Gemeinsamer Workshop der Informatik-Graduiertenkollegs und Forschungskollegs |
Reference:
|
| Dagstuhl, 2009
|
» A Two-Stage SAT-based ATPG Approach with Reduced Switching Activity
|
|
|
|
Author:
|
|
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
| Workshop: |
|
Second International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR) 2009 |
Reference:
|
| Sevilla, Spain, 2009
|
PDF:
|
| [click here]
|
Hyperlink:
|
| [Link to the Workshop]
|
» Robustness Check for Multiple Faults using Formal Techniques
|
|
|
|
Author:
|
|
Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler |
| Workshop: |
|
Constraints in Formal Verification (CFV) |
Reference:
|
| Grenoble, France, 2009
|
PDF:
|
| [click here]
|
Hyperlink:
|
| [Link to the Workshop]
|
» Synthesizing Reversible Logic: An Overview
|
|
|
|
Author:
|
|
Robert Wille, Rolf Drechsler |
| Workshop: |
|
Reed-Muller Workshop |
Reference:
|
| Naha, Okinawa, 2009
|
Hyperlink:
|
| [Link to the Workshop]
|
» Synthesising Reversible Circuits from Irreversible Specifications using Reed-Muller Spectral Techniques
|
|
|
|
Author:
|
|
D. Michael Miller, Gerhard W. Dueck, Robert Wille |
| Workshop: |
|
Reed-Muller Workshop |
Reference:
|
| Naha, Okinawa, 2009
|
Hyperlink:
|
| [Link to the Workshop]
|
» FormED: A Formal Environment for Debugging
|
|
|
|
Author:
|
|
Andre Sülflow, Robert Wille, Christian Genz, Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
University Booth at Design, Automation and Test in Europe (DATE09) |
Reference:
|
| Nizza, 2009
|
PDF:
|
| [click here]
|
Hyperlink:
|
| [Link to the Workshop]
|
» Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic
|
|
|
|
Author:
|
|
Robert Wille, Rolf Drechsler |
| Workshop: |
|
Reversible Computation |
Reference:
|
| York, 2009
|
Hyperlink:
|
| [Link to the Workshop]
|
» A Fast Untestability Proof for SAT-based ATPG
|
|
|
|
Author:
|
|
Daniel Tille, Rolf Drechsler |
| Workshop: |
|
21. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2009 |
Reference:
|
| Bremen, 2009
|
PDF:
|
| [click here]
|
Hyperlink:
|
| [Link to the Workshop]
|
» Algorithms for ATPG under Leakage Constraints
|
|
|
|
Author:
|
|
Görschwin Fey |
| Workshop: |
|
21. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2009 |
Reference:
|
| Bremen, 2009
|
PDF:
|
| [click here]
|
Hyperlink:
|
| [Link to the Workshop]
|
» Using a Two-Dimensional Fault List for Compact Automatic Test Pattern Generation
|
|
|
|
Author:
|
|
Marc Messing, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler |
| Workshop: |
|
10th IEEE Latin-American TestWorkshop (LATW) |
Reference:
|
| Búzios, Rio de Janeiro, 2009
|
Hyperlink:
|
| [Link to the Workshop]
|
» Increasing the Accuracy of SAT-based Debugging
|
|
|
|
Author:
|
|
Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
|
12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Reference:
|
| pp. 47-56, Berlin, 2009
|
PDF:
|
| [click here]
|
Hyperlink:
|
| [Link to the Workshop]
|
» Equivalence Checking of Reversible Circuits
|
|
|
|
Author:
|
|
Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler |
| Workshop: |
|
12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Reference:
|
| 2009
|
Hyperlink:
|
| [Link to the Workshop]
|
» Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow
|
|
|
|
Author:
|
|
Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Workshop: |
|
9th International Workshop on Microprocessor Test and Verification (MTV) |
Reference:
|
| pp. 88-93, Austin, Texas, 2008
|
PDF:
|
| [click here]
|
Hyperlink:
|
| [Link to the Workshop]
|
» Computing Bounds for Fault Tolerance using Formal Techniques
|
|
|
|
Author:
|
|
Andre Sülflow, Görschwin Fey, Stefan Frehse, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
|
IEEE Workshop on Design for Reliability and Variability (DRV) |
Reference:
|
| Santa Clara, USA, 2008
|
PDF:
|
| [click here]
|
Hyperlink:
|
| [Link to the Workshop]
|
» Experimental Studies on SMT-based Debugging
|
|
|
|
Author:
|
|
Andre Sülflow, Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
IEEE 9th Workshop on RTL and High Level Testing (WRTLT'08) |
Reference:
|
| pp. 93-98, Japan, 2008
|
PDF:
|
| [click here]
|
Hyperlink:
|
| [Link to the Workshop]
|
» Reversible Logic Synthesis with Output Permutation
|
|
|
|
Author:
|
|
Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
| Workshop: |
|
International Workshop on Boolean Problems |
Reference:
|
| Freiberg, 2008
|
Hyperlink:
|
| [Link to the Workshop]
|
