» Improving SAT solving using Monte Carlo Tree Search-based Clause Learning
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Author:
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Oliver Keszöcze, Kenneth Schmitz, Jens Schloeter, Rolf Drechsler |
| Workshop: |
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13th International Workshop on Boolean Problems (IWSBP) |
Reference:
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| Bremen, Germany, 2018
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Hyperlink:
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| [Link to the Workshop]
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» ConfidenceSat: A Parallel SAT Solver with Conflict Clause Handling
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Author:
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Kenneth Schmitz, Oliver Keszöcze, Jil Tietjen and Rolf Drechsler |
| Workshop: |
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13th International Workshop on Boolean Problems (IWSBP) |
Reference:
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| Bremen, Germany, 2018
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Hyperlink:
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| [Link to the Workshop]
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» Towards Self-Explaining Digital Systems:
A Design Methodology for the Next Generation
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Author:
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Rolf Drechsler, Christoph Lüth, Goerschwin Fey, Tim Güneysu |
| Workshop: |
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3nd International Verification and Security Workshop (IVSW) |
Reference:
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| Costa Brava, Spain, 2018
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Hyperlink:
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| [Link to the Workshop]
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PDF:
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| [click here]
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» Evaluation of Power State Cross Coverage in Firmware-Based Power Management
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Author:
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Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler |
| Workshop: |
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Embedded Software for Industrial IoTs (ESIIT) |
Reference:
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| Dresden, Germany, 2018
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Hyperlink:
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| [Link to the Workshop]
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» Towards Automated Refinement of TLM Properties to RTL
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Author:
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Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler |
| Workshop: |
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Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) |
Reference:
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| Tübingen, Germany, 2018
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Hyperlink:
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| [Link to the Workshop]
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» A Codeword-based Compaction Technique for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks
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Author:
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Sebastian Huhn, Marcel Merten, Stephan Eggersglüß and Rolf Drechsler |
| Workshop: |
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30. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2018) |
Reference:
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| Freiburg (Breisgau), Germany, 2018
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Hyperlink:
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| [Link to the Workshop]
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PDF:
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| [click here]
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» ATPG Constraint Analysis for Reducing Regional Power Activity
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Author:
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Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen |
| Workshop: |
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30. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2018) |
Reference:
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| Freiburg (Breisgau), Germany, 2018
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Hyperlink:
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| [Link to the Workshop]
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» Time-stamps for Hardware Simulation Models Accurate Time-back Annotation
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Author:
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Rehab Massoud, Jannis Stoppe, Karthik Maddikunta, Rolf Drechsler |
| Workshop: |
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5th Workshop on Design Automation for Understanding Hardware Designs (DUHDe) |
Reference:
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| Dresden, Germany, 2018
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Hyperlink:
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| [Link to the Workshop]
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» Execution Environment for Dynamic Software Runtime Examination
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Author:
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Kenneth Schmitz, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler |
| Workshop: |
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5th Workshop on Design Automation for Understanding Hardware Designs (DUHDe) |
Reference:
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| Dresden, Germany, 2018
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Hyperlink:
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| [Link to the Workshop]
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» A Lightweight Method for Transient Test Power Pattern Analysis for Pattern Selection
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Author:
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Harshad Dhotre, Stephan Eggersglüß |
| Workshop: |
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29. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2017) |
Reference:
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| Lübeck, Germany, 2017
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Hyperlink:
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| [Link to the Workshop]
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» Making Waveforms Great Again
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Author:
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Jannis Stoppe and Rolf Drechsler |
| Workshop: |
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4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe) |
Reference:
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| Lausanne, Switzerland, 2017
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Hyperlink:
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| [Link to the Workshop]
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» A Human-Centered Approach to Routing for Digital Microfluidic Biochips
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Author:
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Oliver Keszöcze, Andre Pols and Rolf Drechsler |
| Workshop: |
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4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe) |
Reference:
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| Lausanne, Switzerland, 2017
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Hyperlink:
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| [Link to the Workshop]
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» Verilog2GEXF - Dynamic Large Scale Circuit Visualization
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Author:
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Kenneth Schmitz, Jannis Stoppe, Rolf Drechsler |
| Workshop: |
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4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe) |
Reference:
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| Lausanne, Switzerland, 2017
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Hyperlink:
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| [Link to the Workshop]
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» Computing Exact Fault Candidates Incrementally
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Author:
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Heinz Riener, Görschwin Fey |
| Workshop: |
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4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe) |
Reference:
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| Lausanne, Switzerland, 2017
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Hyperlink:
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| [Link to the Workshop]
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» Mining Latency Guarantees for RT-level Designs
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Author:
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Jan Malburg, Heinz Riener, Görschwin Fey |
| Workshop: |
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4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe) |
Reference:
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| Lausanne, Switzerland, 2017
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Hyperlink:
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| [Link to the Workshop]
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» Revisiting Symbolic Software-implemented Fault Injection
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Author:
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Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler |
| Workshop: |
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2nd International Workshop
on Resiliency in Embedded Electronic Systems (REES) |
Reference:
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| Lausanne, Switzerland, 2017
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Hyperlink:
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| [Link to the Workshop]
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» Der Einfluss von Zellformen auf das Routing von Digital Microfluidic Biochips
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Author:
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Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler |
| Workshop: |
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Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) |
Reference:
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| Bremen, Germany, 2017
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Hyperlink:
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| [Link to the Workshop]
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» Exakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate Computing
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Author:
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Saman Fröhlich, Daniel Große, Rolf Drechsler |
| Workshop: |
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Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) |
Reference:
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| Bremen, Germany, 2017
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Hyperlink:
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| [Link to the Workshop]
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» Counterexample-Guided EF Synthesis of Boolean Functions
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Author:
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Heinz Riener, Rüdiger Ehlers, Görschwin Fey |
| Workshop: |
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Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) |
Reference:
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| Bremen, Germany, 2017
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Hyperlink:
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| [Link to the Workshop]
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» Using Lightweight Containers in Hardware/Software Co-Design for Security
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Author:
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Daniel Große, Kenneth Schmitz, Rolf Drechsler |
| Workshop: |
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Workshop on Computer-Aided Design and Implementation for Cryptography and Security (CADICS) |
Reference:
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| Austin, USA, 2016
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Hyperlink:
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| [Link to the Workshop]
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