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Universität Bremen Universität Bremen Fachbereich 3 Informatik
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» Kolloquium - Verification and debugging of hardware designs utilizing C‐based high‐level design descriptions Abstract

26.10.2009 - Cartesium | Rotunde | 13 Uhr s.t. Masahiro Fujita and Amir Gharehbagh | VLSI Design and Education Center | University of Tokyo

This presentation has two parts. The first part overviews our verification research activities regarding to C‐based high‐level design descriptions. Various dependences are automatically extracted from given C‐based hardware designs, and then they are reasoned about by various traversals on them. We show how efficient equivalence checking with respect to C‐based descriptions can be made with those analysis methods. In the second part, a post‐silicon verification method which tries to map chip traces with C‐based description is introduced. It is based on a little bit of extra hardware supports for extraction of communication events happening in the chip. The extracted traces are then analyzed by the backend debugging software. Several experimental results are given to show the effectiveness of the proposed approach.

Biography | Fujita
Masahiro Fujita received his Ph.D. degree in Information Engineering from the University of Tokyo in 1985 and shortly after joined Fujitsu Laboratories Ltd. From 1993 to 2000, he had been assigned to Fujitsu's US research office and directed the CAD research and development group. In March 2000, he joined the department of Electronic Engineering in the University of Tokyo as a professor. He is now a professor at VLSI Design and Education Center (VDEC) in the university. He has co‐authored 7 books, and has over 150 publications. He has received several awards from Japanese major scientific societies on his works in formal verification and logic synthesis. His doctor degree thesis was written in early 80's and on model checking. Since then he has been involved in many research projects on various aspects of formal verification. His current research interests include synthesis and verification in higher level design stages, hardware/software co‐designs and also digital/analog co‐designs.


Kontakt:
Dr. Görschwin Fey, Prof. Dr. Rolf Drechsler

Erfassungsdatum: 26.10.2009 | Nr. 47





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