VLSI CAD has greatly benefited from the use of reduced ordered Binary Decision Diagrams (BDDs) and the clausal representation as a problem of "Boolean Satisfiability" (SAT), e.g. in logic synthesis, verification or design-for-testability. In recent practical applications, BDDs are optimized with respect to new objective functions for design space exploration. The latest trends show a growing number of proposals to fuse the concepts of BDD and SAT.
Advanced BDD Optimization gives a modern presentation of the established as well as of recent concepts. Latest results in BDD optimization are given, covering different aspects of paths in BDDs and the use of efficient lower bounds during optimization. The presented algorithms include Branch and Bound and the generic A*-algorithm as efficient techniques to explore large search spaces.
The A*-algorithm originates from "Artificial Intelligence" (AI), and the EDA community has been unaware of this concept for a long time. Recently, the A*-algorithm has been introduced as a new paradigm to explore design spaces in VLSI CAD. Besides AI techniques, Advanced BDD Optimization also discusses the relation to another field of activity bordered to VLSI CAD and BDD optimization: the clausal representation as a SAT problem.
When regarding BDD optimization, mainly the minimization of diagram size was considered. The present book is the first to give a unified framework for the problem of BDD optimization and it presents the respective recent approaches. Moreover, the relation between BDD and SAT is studied in response to the questions that have emerged from the latest developments. This includes an analysis from a theoretical point of view as well as practical examples in formal equivalence checking.
Advanced BDD optimization closes the gap between theory and practice by transferring the latest theoretical insights into practical applications.