» Model-Based Diagnosis versus Error Explanation
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Autor:
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Heinz Riener, Görschwin Fey |
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10th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'12) |
Referenz:
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| Arlington, Virginia. USA, 2012
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Hyperlink:
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| [Link zur Konferenz]
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» Circuit Line Minimization in the HDL-based Synthesis of Reversible Logic
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Autor:
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Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler |
| Konferenz: |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
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| Amherst, USA, 2012
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Hyperlink:
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| [Link zur Konferenz]
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» On Modeling and Evaluation of Logic Circuits
Under Timing Variations
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Autor:
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Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan |
| Konferenz: |
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15th Euromicro Conference on Digital System Design (DSD) |
Referenz:
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| Izmir, Turkey, 2012
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Hyperlink:
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| [Link zur Konferenz]
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» Coverage-driven Stimuli Generation
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Autor:
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Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler |
| Konferenz: |
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15th Euromicro Conference on Digital System Design (DSD) |
Referenz:
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| Izmir, Turkey, 2012
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Hyperlink:
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| [Link zur Konferenz]
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» Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology
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Autor:
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Rolf Drechsler, Robert Wille |
| Konferenz: |
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International Symposium on VLSI Design and Test (VDAT) |
Referenz:
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| Shibpur, India, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Assisted Behavior Driven Development Using Natural Language Processing
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Autor:
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Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
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50th International Conference on Objects, Models, Components, Patterns (TOOLS) |
Referenz:
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| Prague, Czech Republic, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» A New SAT-based ATPG for Generating Highly Compacted Test Sets
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Autor:
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Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler |
| Konferenz: |
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15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
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| Tallinn, Estonia, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Automated Debugging from Pre-Silicon to Post-Silicon
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Autor:
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Mehdi Dehbashi, Görschwin Fey |
| Konferenz: |
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15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
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| Tallinn, Estonia, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Automated Feature Localization for Hardware Designs
using Coverage Metrics
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Autor:
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Jan Malburg, Alexander Finder, Görschwin Fey |
| Konferenz: |
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Design Automation Conference (DAC) |
Referenz:
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| San Francisco, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Realizing Reversible Circuits Using a New Class of Quantum Gates
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Autor:
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Zahra Sasanian, Robert Wille, Michael Miller |
| Konferenz: |
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Design Automation Conference (DAC) |
Referenz:
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| San Francisco, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Functional Analysis of Circuits Under Timing
Variations
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Autor:
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Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
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| Konferenz: |
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17th IEEE European Test Symposium (ETS) |
Referenz:
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| Annecy, France, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits
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Autor:
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Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler |
| Konferenz: |
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42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| 2012, Victoria
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» A Synthesis Flow for Sequential Reversible Circuits
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Autor:
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Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler |
| Konferenz: |
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42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| 2012, Victoria
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines
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Autor:
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Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler |
| Konferenz: |
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42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| Victoria, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis
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Autor:
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Robert Wille, Rolf Drechsler, Christof Oswald, Alberto Garcia-Ortiz |
| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| Dresden, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» A Guiding Coverage Metric for Formal Verification
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Autor:
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Finn Haedicke, Daniel Große, Rolf Drechsler |
| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| Dresden, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Eliminating Invariants in UML/OCL Models
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Autor:
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Mathias Soeken, Robert Wille, Rolf Drechsler
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| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| pp. 1142-1145, Dresden, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Debugging of Inconsistent UML/OCL Models
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Autor:
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Robert Wille, Mathias Soeken, Rolf Drechsler
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| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| pp. 1078-1083, Dresden, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Synthesis of Reversible Circuits with Minimal Lines for Large Functions
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Autor:
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Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler |
| Konferenz: |
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Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
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| pp. 85-92, Sydney, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Improved Fault Diagnosis for Reversible Circuits
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Autor:
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Hongyan Zhang, Robert Wille, Rolf Drechsler |
| Konferenz: |
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Asian Test Symposium (ATS) |
Referenz:
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| New Delhi, 2011
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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