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» Automated Detection of Spatial Memory Safety Violations for Constrained Devices




Autor:

Sören Tempel, Vladimir Herdt, Rolf Drechsler
Konferenz:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Referenz:

Taipei, Taiwan, 2022
Hyperlink:

[Link zur Konferenz]



» Polynomial Formal Verification of Prefix Adders




Autor:

Alireza Mahzoon, Rolf Drechsler
Konferenz:
Asian Test Symposium (ATS)
Referenz:

Virtual Conference, Japan, 2021
Hyperlink:

[Link zur Konferenz]



» A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks




Autor:

Marcel Merten, Sebastian Huhn, Rolf Drechsler
Konferenz:
34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Referenz:

Athens, Greece, 2021
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]



» Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs




Autor:

Mehran Goli, Rolf Drechsler
Konferenz:
International Conference on Computer Aided Design (ICCAD)
Referenz:

Munich, Germany, 2021
Hyperlink:

[Link zur Konferenz]



» Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level




Autor:

Frank Riese, Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz:
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Referenz:

Virtual Conference, Singapore, 2021
Hyperlink:

[Link zur Konferenz]



» RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems




Autor:

Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
Konferenz:
Forum on Specification & Design Languages (FDL)
Referenz:

Antibes, France, 2021
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]



» VIP-VP: Early Validation of SoCs Information Flow Policies using SystemC-based Virtual Prototypes




Autor:

Mehran Goli, Rolf Drechsler
Konferenz:
Forum on Specification & Design Languages (FDL)
Referenz:

Antibes, France, 2021
Best Paper Award
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]



» In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes




Autor:

Sören Tempel, Vladimir Herdt, Rolf Drechsler
Konferenz:
Forum on Specification & Design Languages (FDL)
Referenz:

Antibes, France, 2021
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]



» Work-in-Progress: Early Power Estimation of CUDA-based CNNs on GPGPUs




Autor:

Christopher Metz, Mehran Goli, Rolf Drechsler
Konferenz:
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
Referenz:

VIRTUAL CONFERENCE, 2021
Hyperlink:

[Link zur Konferenz]



» Minimally Invasive HW/SW Co-debug Live Visualization on Architecture Level




Autor:

Pascal Pieper, Ralf Wimmer, Gerhard Angst, Rolf Drechsler
Konferenz:
31st ACM Great Lakes Symposium on VLSI (GLSVLSI)
Referenz:

Virtual Conference, 2021
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]



» Finding Optimal Implementations of Non-native CNOT Gates using SAT




Autor:

Philipp Niemann, Luca Müller, Rolf Drechsler
Konferenz:
Reversible Computation (RC)
Referenz:

Nagoya, Japan, 2021
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]



» Combining SWAPs and Remote CNOT Gates for Quantum Circuit Transformation




Autor:

Philipp Niemann, Luca Müller, Rolf Drechsler
Konferenz:
Euromicro Conference on Digital System Design (DSD)
Referenz:

Palermo, Sicily, Italy, 2021
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]



» Automated Debugging-Aware Visualization Technique for SystemC HLS Designs




Autor:

Mehran Goli, Alireza Mahzoon, Rolf Drechsler
Konferenz:
Euromicro Conference on Digital System Design (DSD)
Referenz:

Palermo, Sicily, Italy, 2021
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]



» ALF – A Fitness-Based Artificial Life Form for Evolving Large-Scale Neural Networks




Autor:

Rune Krauss, Marcel Merten, Mirco Bockholt, Rolf Drechsler
Konferenz:
The Genetic and Evolutionary Computation Conference (GECCO)
Referenz:

Lille, France, 2021
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]



» Optimization-based Test Scheduling for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability




Autor:

Payam Habiby, Sebastian Huhn, Rolf Drechsler
Konferenz:
28th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
Referenz:

Apulia, Italy, 2021
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]



» Synthesis of Asymptotically Optimal Adders for Multiple-Valued Logic




Autor:

Philipp Niemann, Rolf Drechsler
Konferenz:
51st International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

Nursultan, Kazakhstan, 2021
Hyperlink:

[Link zur Konferenz]
Vortrag:

[Link Vortragsvideo]
PDF:

[hier ansehen]



» Depth Optimized Synthesis of Symmetric Boolean Functions




Autor:

Martha Schnieber, Saman Fröhlich, Rolf Drechsler
Konferenz:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Referenz:

Tampa, Florida, USA, 2021
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]



» Domain-driven correlation-aware recombination and mutation operators for complex real-world applications




Autor:

Christina Plump, Bernhard J. Berger, Rolf Drechsler
Konferenz:
IEEE Congress on Evolutionary Computation (CEC)
Referenz:

Kraków, Poland, 2021
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]



» Improving evolutionary algorithms by enhancing an approximative fitness function through prediction intervals




Autor:

Christina Plump, Bernhard J. Berger, Rolf Drechsler
Konferenz:
IEEE Congress on Evolutionary Computation (CEC)
Referenz:

Krakow, Poland, 2021
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]



» PolyAdd: Polynomial Formal Verification of Adder Circuits




Autor:

Rolf Drechsler
Konferenz:
24th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Referenz:

Vienna, Austria, 2021
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]




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