» Self-Adaptive Evolutionary Many-Objective Optimization based on Relation Epsilon-Preferred
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Autor:
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Nicole Drechsler |
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International Conference on Soft Computing MENDEL |
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| Brno, Czech Republic, 2013
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Hyperlink:
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| [Link zur Konferenz]
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» Improved SAT-based ATPG: More Constraints, Better Compaction
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Autor:
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Stephan Eggersglüß, Robert Wille, Rolf Drechsler |
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IEEE/ACM International Conference on Computer-Aided Design (ICCAD) |
Referenz:
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| San Jose, USA, 2013
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Hyperlink:
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| [Link zur Konferenz]
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» A Compact and Efficient SAT Encoding for Quantum Circuits
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Autor:
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Robert Wille, Nils Przigoda, Rolf Drechsler |
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IEEE Africon |
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| Mauritius, 2013
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Hyperlink:
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| [Link zur Konferenz]
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» Exploiting Reversibility in the Complete Simulation of Reversible Circuits
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Autor:
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Robert Wille, Simon Stelter, Rolf Drechsler |
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IEEE Africon |
Referenz:
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| Mauritius, 2013
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Hyperlink:
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| [Link zur Konferenz]
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» Cone of Influence Analysis at the Electronic System Level Using Machine Learning
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Autor:
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Jannis Stoppe, Robert Wille, Rolf Drechsler |
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Euromicro Conference on Digital System Design (DSD) |
Referenz:
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| Santander, Spain, 2013
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Hyperlink:
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| [Link zur Konferenz]
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» Minimal Stimuli Generation in Simulation-based Verification
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Autor:
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Shuo Yang, Robert Wille, Daniel Große and Rolf Drechsler |
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Euromicro Conference on Digital System Design (DSD) |
Referenz:
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| Santander, Spain, 2013
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Hyperlink:
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| [Link zur Konferenz]
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» The SyReC Hardware Description Language:
Enabling Scalable Synthesis of Reversible Circuits
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Autor:
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Robert Wille, Rolf Drechsler |
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International Midwest Symposium on Circuits and Systems (MWSCAS) |
Referenz:
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| Columbus, USA, 2013
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Hyperlink:
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| [Link zur Konferenz]
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» Incorporating User Preferences in Many-Objective Optimization using Relation Epsilon-Preferred
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Autor:
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Nicole Drechsler, André Sülflow, Rolf Drechsler |
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International Conference on Evolutionary Computation Theory and Applications (ECTA) |
Referenz:
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| Vilamoura, Portugal, 2013
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Hyperlink:
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| [Link zur Konferenz]
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» Data Extraction from SystemC Designs using Debug Symbols and the SystemC API
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Autor:
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Jannis Stoppe, Robert Wille, Rolf Drechsler |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
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| Natal, Brazil, 2013
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Hyperlink:
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| [Link zur Konferenz]
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» On the “Q” in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-structure
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Autor:
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Philipp Niemann, Robert Wille, Rolf Drechsler |
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Reversible Computation |
Referenz:
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| Victoria, Canada, 2013
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Exploiting Negative Control Lines in the Optimization of Reversible Circuits
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Autor:
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Kamalika Datta, Gaurav Rathi, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler |
| Konferenz: |
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Reversible Computation |
Referenz:
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| Victoria, Canada, 2013
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure
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Autor:
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Arighna Deb, Debesh Kumar Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler |
| Konferenz: |
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Reversible Computation |
Referenz:
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| Victoria, Canada, 2013
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» White Dots do Matter: Rewriting Reversible Logic Circuits
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Autor:
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Mathias Soeken, Michael Kirkedal Thomsen |
| Konferenz: |
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Reversible Computation |
Referenz:
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| Victoria, Canada, 2013
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Hyperlink:
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| [Link zur Konferenz]
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» Reducing the Depth of Quantum Circuits Using Additional Lines
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Autor:
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Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
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Reversible Computation |
Referenz:
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| Victoria, Canada, 2013
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Hardware-Software Co-Visualization: Developing Systems in the Holodeck
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Autor:
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Rolf Drechsler, Mathias Soeken |
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16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
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| Karlovy Vary, Czech Republic, 2013
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Debugging HDL Designs Based on Functional Equivalences with High-Level Specifications
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Autor:
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Alexander Finder, Jan-Philipp Witte, Görschwin Fey |
| Konferenz: |
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16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
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| Karlovy Vary, Czech Republic, 2013
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Efficient Automated Speedpath Debugging
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Autor:
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Mehdi Dehbashi, Görschwin Fey |
| Konferenz: |
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16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
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| pp. 48-53, Karlovy Vary, Czech Republic, 2013
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Verifying SystemC using an Intermediate Verification Language and Symbolic Simulation
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Autor:
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Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler |
| Konferenz: |
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Design Automation Conference (DAC) |
Referenz:
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| Austin, Texas, 2013
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits
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Autor:
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Robert Wille, Hongyan Zhang, Rolf Drechsler |
| Konferenz: |
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43rd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| Toyama, 2013
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Debugging of Reversible Circuits using πDDs
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Autor:
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Laura Tague, Mathias Soeken, Shin-ichi Minato, Rolf Drechsler |
| Konferenz: |
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43rd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| Toyama, 2013
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Hyperlink:
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| [Link zur Konferenz]
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