» Exact Template Matching Using Boolean Satisfiability
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Autor:
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Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
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43rd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| Toyama, 2013
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Synchronized Debugging across Different Abstraction Levels in System Design
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Autor:
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Rolf Drechsler, Daniel Große, Hoang M. Le, André Sülflow |
| Konferenz: |
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embedded world Conference 2013 |
Referenz:
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| Nürnberg, 2013
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Scalable Fault Localization for SystemC TLM Designs
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Autor:
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Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
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Design, Automation and Test in Europe (DATE'13) |
Referenz:
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| pp. 35-38, Grenoble, France, 2013
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Reliability Analysis Reloaded: How Will We Survive?
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Autor:
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Robert Aitken, Görschwin Fey, Zbigniew T. Kalbarczyk, Frank Reichenbach, Matteo Sonza Reorda |
| Konferenz: |
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Design, Automation and Test in Europe (DATE'13) |
Referenz:
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| Grenoble, France, 2013
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Tuning Dynamic Data Flow Analysis to Support Design Understanding
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Autor:
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Jan Malburg, Alexander Finder, Görschwin Fey |
| Konferenz: |
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Design, Automation and Test in Europe (DATE'13) |
Referenz:
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| Grenoble, France, 2013
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Improving Fault Tolerance Utilizing Hardware-Software-Co-Synthesis
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Autor:
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Heinz Riener, Stefan Frehse, Görschwin Fey |
| Konferenz: |
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Design, Automation and Test in Europe (DATE'13) |
Referenz:
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| pp. 939-943, Grenoble, France, 2013
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Determining Relevant Model Elements for the Verification of UML/OCL Specifications
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Autor:
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Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| Grenoble, France, 2013
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Towards a Generic Verification Methodology for System Models
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Autor:
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Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler |
| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| Grenoble, France, 2013
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Improving the Mapping of Reversible Circuits to Quantum Circuits Using Multiple Target Lines
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Autor:
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Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler |
| Konferenz: |
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Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
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| Yokohama, Japan, 2013
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» An Evolutionary Approach to Reversible Logic Synthesis using Output Permutation
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Autor:
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Kamalika Datta, Indranil Sen Gupta, Hafizur Rahaman, Rolf Drechsler |
| Konferenz: |
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IEEE Design and Test Symposium 2012 (IDT) |
Referenz:
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| Doha, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Towards Dialog Systems for Assisted Natural Language Processing in the Design of Embedded Systems
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Autor:
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Rolf Drechsler, Mathias Soeken, Robert Wille |
| Konferenz: |
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IEEE Design and Test Symposium 2012 (IDT) |
Referenz:
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| Doha, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Synthesis of Reversible Circuits Using Decision Diagrams
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Autor:
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Rolf Drechsler, Robert Wille |
| Konferenz: |
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International Symposium on Electronic System Design (ISED) |
Referenz:
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| Kolkata, WB, India, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» SyDe - a New Graduate School for
System Design in an Excellent Setting
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Autor:
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Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
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Informatics Europe (ECSS) |
Referenz:
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| Barcelona, 2012
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Hyperlink:
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| [Link zur Konferenz]
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» From Requirements and Scenarios to ESL Design in SystemC
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Autor:
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Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
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International Symposium on Electronic System Design (ISED) |
Referenz:
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| Kolkata, WB, India, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» FoREnSiC - An Automatic Debugging Environment for C Programs
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Autor:
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Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow
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| Konferenz: |
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Haifa Verification Conference (HVC) |
Referenz:
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| Haifa, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization
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Autor:
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Stephan Eggersglüß, Mahmut Yilmaz, Krishnendu Chakrabarty |
| Konferenz: |
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21st IEEE Asian Test Symposium (ATS) |
Referenz:
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| pp. 290-295, Niigata, Japan, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Automated Post-Silicon Debugging of Failing
Speedpaths
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Autor:
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Mehdi Dehbashi, Görschwin Fey |
| Konferenz: |
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21st IEEE Asian Test Symposium (ATS) |
Referenz:
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| pp. 13-18, Niigata, Japan, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» The System Verification Methodology for
Advanced TLM Verification
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Autor:
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Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler, Wolfgang Ecker, Volkan Esen |
| Konferenz: |
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International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) |
Referenz:
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| pp. 313-322, Tampere, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Complete and Effective Robustness Checking by Means of Interpolation
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Autor:
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Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav and Rolf Drechsler |
| Konferenz: |
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Formal Methods in Computer-Aided Design (FMCAD'12) |
Referenz:
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| Cambridge, UK, 2012, page 82-90
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Completeness-Driven Development
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Autor:
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Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille |
| Konferenz: |
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International Conference on Graph Transformation |
Referenz:
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| pp. 38-50, Bremen, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC
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Autor:
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Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
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International Symposium on System-on-Chip (SoC) |
Referenz:
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| pp. 1-7, Tampere, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Distributed and Coupled Electrothermal Model of Power Semiconductor Devices
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Autor:
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G. Belkacem, D. Labrousse, S. Lefebvre, P.-Y. Joubert, U. Kühne, L. Fribourg, R. Soulat, E. Florentin, C. Rey |
| Konferenz: |
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International Conference on Renewable Energies and Vehicular Technology |
Referenz:
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| Hammamet, 2012
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Hyperlink:
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| [Link zur Konferenz]
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» Hardware-Software-Co-Synthese zur Verbesserung der Fehlertoleranz
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Autor:
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Stefan Frehse, Heinz Riener, Görschwin Fey |
| Konferenz: |
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6. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE'12) |
Referenz:
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| pp. 90-96, Bremen, Germany, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Application of Timing Variation Modeling to Speedpath Diagnosis
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Autor:
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Mehdi Dehbashi, Görschwin Fey |
| Konferenz: |
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4th International Conference on System, Software, SoC and Silicon Debug (S4D) |
Referenz:
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| pp. 34-37, Vienna, Austria, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Localizing Features of ESL Models for Design Understanding
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Autor:
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Marc Michael, Daniel Große, Rolf Drechsler |
| Konferenz: |
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Forum on specification & Design Languages (FDL) |
Referenz:
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| Vienna, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Formal Specification Level: Towards Verification-driven Design Based on Natural Language Processing
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Autor:
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Rolf Drechsler, Mathias Soeken, Robert Wille |
| Konferenz: |
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Forum on specification & Design Languages (FDL) |
Referenz:
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| pp. 53-58, Vienna, Austria, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Parametric Analysis of Hybrid Systems Using HyMITATOR (Tool Presentation)
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Autor:
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Étienne André, Ulrich Kühne |
| Konferenz: |
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International Conference on Integrated Formal Methods (iFM)
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Referenz:
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| Pisa, Italy, 2012
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Hyperlink:
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| [Link zur Konferenz]
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» IMITATOR 2.5: A Tool for Analyzing Robustness in Scheduling Problems (Tool Paper)
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Autor:
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Étienne André, Laurent Fribourg, Ulrich Kühne, Romain Soulat |
| Konferenz: |
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International Symposium on Formal Methods (FM) |
Referenz:
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| Paris, France, 2012
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Hyperlink:
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| [Link zur Konferenz]
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» Model-Based Diagnosis versus Error Explanation
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Autor:
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Heinz Riener, Görschwin Fey |
| Konferenz: |
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10th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'12) |
Referenz:
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| pp. 43-52, Arlington, Virginia, USA, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Circuit Line Minimization in the HDL-based Synthesis of Reversible Logic
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Autor:
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Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler |
| Konferenz: |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
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| pp. 213-218, Amherst, USA, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» On Modeling and Evaluation of Logic Circuits
Under Timing Variations
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Autor:
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Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan |
| Konferenz: |
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15th Euromicro Conference on Digital System Design (DSD) |
Referenz:
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| pp. 431-436, Izmir, Turkey, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Coverage-driven Stimuli Generation
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Autor:
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Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler |
| Konferenz: |
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15th Euromicro Conference on Digital System Design (DSD) |
Referenz:
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| Izmir, Turkey, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology
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Autor:
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Rolf Drechsler, Robert Wille |
| Konferenz: |
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International Symposium on VLSI Design and Test (VDAT) |
Referenz:
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| Shibpur, India, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Assisted Behavior Driven Development Using Natural Language Processing
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Autor:
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Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
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50th International Conference on Objects, Models, Components, Patterns (TOOLS) |
Referenz:
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| pp. 269-287, Prague, Czech Republic, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» A New SAT-based ATPG for Generating Highly Compacted Test Sets
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Autor:
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Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler |
| Konferenz: |
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15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
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| pp. 230-235, Tallinn, Estonia, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Automated Debugging from Pre-Silicon to Post-Silicon
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Autor:
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Mehdi Dehbashi, Görschwin Fey |
| Konferenz: |
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15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
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| pp. 324-329, Tallinn, Estonia, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Automated Feature Localization for Hardware Designs
using Coverage Metrics
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Autor:
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Jan Malburg, Alexander Finder, Görschwin Fey |
| Konferenz: |
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Design Automation Conference (DAC) |
Referenz:
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| pp. 941-946, San Francisco, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Realizing Reversible Circuits Using a New Class of Quantum Gates
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Autor:
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Zahra Sasanian, Robert Wille, Michael Miller |
| Konferenz: |
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Design Automation Conference (DAC) |
Referenz:
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| San Francisco, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Functional Analysis of Circuits Under Timing
Variations
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Autor:
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Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
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| Konferenz: |
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17th IEEE European Test Symposium (ETS) |
Referenz:
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| pp. 177, Annecy, France, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits
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Autor:
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Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler |
| Konferenz: |
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42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| 2012, Victoria
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» A Synthesis Flow for Sequential Reversible Circuits
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Autor:
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Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler |
| Konferenz: |
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42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| 2012, Victoria
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines
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Autor:
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Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler |
| Konferenz: |
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42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| Victoria, 2012
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
|
| [hier ansehen]
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» Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis
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Autor:
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Robert Wille, Rolf Drechsler, Christof Oswald, Alberto Garcia-Ortiz |
| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| Dresden, 2012
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Hyperlink:
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| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
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» A Guiding Coverage Metric for Formal Verification
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Autor:
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Finn Haedicke, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Dresden, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
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» Eliminating Invariants in UML/OCL Models
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Autor:
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Mathias Soeken, Robert Wille, Rolf Drechsler
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| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1142-1145, Dresden, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
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» Debugging of Inconsistent UML/OCL Models
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Autor:
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Robert Wille, Mathias Soeken, Rolf Drechsler
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| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1078-1083, Dresden, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
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» Synthesis of Reversible Circuits with Minimal Lines for Large Functions
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Autor:
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Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| pp. 85-92, Sydney, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Improved Fault Diagnosis for Reversible Circuits
|
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Autor:
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|
Hongyan Zhang, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Asian Test Symposium (ATS) |
Referenz:
|
| New Delhi, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automated Post-Silicon Debugging of Design Bugs
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Autor:
|
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Mehdi Dehbashi, Görschwin Fey |
| Konferenz: |
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3rd International Conference on System, Software, SoC and Silicon Debug (S4D) |
Referenz:
|
| pp. 67-71, Munich, Germany, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Hochoptimierter Ablauf zur Robustheitsprüfung
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Autor:
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Stefan Frehse, Finn Haedicke, Melanie Diepenbeck, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) |
Referenz:
|
| Hamburg-Harburg, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Analyzing Dependability Measures at the Electronic System Level
|
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|
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Autor:
|
|
Marc Michael, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 1-8, Oldenburg, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Efficient Realization of Control Logic in Reversible Circuits
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Autor:
|
|
Sebastian Offermann, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Oldenburg, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Determining Minimal Testsets for Reversible Circuits Using Boolean Satisfiability
|
|
|
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Autor:
|
|
Hongyan Zhang, Stefan Frehse, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
10th IEEE Africon |
Referenz:
|
| Livingstone, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automated Design Debugging in a Testbench-Based Verification Environment
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Autor:
|
|
Mehdi Dehbashi, André Sülflow, Görschwin Fey |
| Konferenz: |
|
14th Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 479-486, Oulu, Finland, 2011
Best Paper Candidate
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» VisSAT: Visualization of SAT Solver Internals for Computer Aided Hardware Verification
|
|
|
|
Autor:
|
|
Robert Wille, André Sülflow, Rolf Drechsler |
| Konferenz: |
|
International Conference on Modeling, Simulation and Visualization Methods (MSV) |
Referenz:
|
| pp. 36-39, Las Vegas, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Orchestrated Multi-level Information Flow Analysis to Understand SoCs
|
|
|
|
Autor:
|
|
Görschwin Fey |
| Konferenz: |
|
48th Design Automation Conference (DAC)
|
Referenz:
|
| San Diego, USA, 2011
Promotion video on YouTube
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» ATPG for Reversible Circuits Using Simulation,
Boolean Satisfiability, and Pseudo Boolean
Optimization
|
|
|
|
Autor:
|
|
Robert Wille, Hongyan Zhang, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| pp. 120-125, Chennai, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» An Introduction to Reversible Circuit Design
|
|
|
|
Autor:
|
|
Robert Wille |
| Konferenz: |
|
Saudi International Electronics, Communications and Photonics Conference (SIECPC) |
Referenz:
|
| Riyadh, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Encoding OCL Data Types for SAT-based Verification of UML/OCL Models
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
5th International Conference on Tests & Proofs (TAP) |
Referenz:
|
| pp. 152-170, Zurich, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Latency Analysis for Sequential Circuits
|
|
|
|
Autor:
|
|
Alexander Finder, André Sülflow, Görschwin Fey |
| Konferenz: |
|
16th IEEE European Test Symposium (ETS) |
Referenz:
|
| pp. 129-134, Trondheim, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automatic Property Generation for the Formal Verification of Bus Bridges
|
|
|
|
Autor:
|
|
Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 417-422, Cottbus, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» TLM Protocol Compliance Checking at the Electronic System Level
|
|
|
|
Autor:
|
|
Mohamed Bawadekji, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 435-440, Cottbus, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Designing a RISC CPU in Reversible Logic
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler |
| Konferenz: |
|
41st International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 170-175, Tuusula, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits
|
|
|
|
Autor:
|
|
Rolf Drechsler, Robert Wille |
| Konferenz: |
|
41st International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 78-85, Tuusula, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Elementary Quantum Gate Realizations for Multiple-Control Toffoli Gates
|
|
|
|
Autor:
|
|
D. Michael Miller, Robert Wille, Z. Sasanian |
| Konferenz: |
|
41st International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 288-293, Tuusula, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Simulation-based Equivalence Checking between SystemC Models at different Levels of Abstraction
|
|
|
|
Autor:
|
|
Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 223-228, Lausanne, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Verifying Dynamic Aspects of UML Models
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1077-1082, Grenoble, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Determining the Minimal Number of Lines for Large Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Oliver Keszöcze, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1204-1207, Grenoble, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1291-1296, Grenoble, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automatic Fault Localization for Programmable Logic Controllers
|
|
|
|
Autor:
|
|
Andre Sülflow, Rolf Drechsler |
| Konferenz: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT) |
Referenz:
|
| pp. 247-256, Braunschweig, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automated Formal Verification of Processors Based on Architectural Models
|
|
|
|
Autor:
|
|
Ulrich Kühne, Sven Beyer, Jörg Bormann, John Barstow |
| Konferenz: |
|
Formal Methods in Computer Aided Design (FMCAD) |
Referenz:
|
| Lugano, Switzerland, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Robust Algorithms for High Quality Test Pattern Generation Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
International Test Conference (ITC) |
Referenz:
|
| pp. 1-10, Austin, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Polynomial Datapath Optimization using Constraint Solving and Formal Modelling
|
|
|
|
Autor:
|
|
Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler |
| Konferenz: |
|
IEEE/ACM International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| San Jose, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» SyReC: A Programming Language for Synthesis of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Sebastian Offermann, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 184-189, Southampton, 2010
Received Best Paper Award
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Evaluating Debugging Algorithms from a Qualitative Perspective
|
|
|
|
Autor:
|
|
Alexander Finder, Görschwin Fey |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 37-42, Southampton, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Kompositionelle Formale Robustheitsprüfung
|
|
|
|
Autor:
|
|
Stefan Frehse, Görschwin Fey |
| Konferenz: |
|
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) |
Referenz:
|
| Wildbad Kreuth, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Proving Transaction and System-level Properties of Untimed SystemC TLM Designs
|
|
|
|
Autor:
|
|
Daniel Große, Hoang M. Le, Rolf Drechsler |
| Konferenz: |
|
International Conference on
Formal Methods and Models for Codesign (MEMOCODE) |
Referenz:
|
| pp. 113-122, Grenoble, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» RobuCheck: A Robustness Checker for Digital Circuits
|
|
|
|
Autor:
|
|
Stefan Frehse, Görschwin Fey, Andre Sülflow and Rolf Drechsler
|
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 226-231, Lille, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Reducing the Number of Lines in Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| pp. 647-652, Anaheim, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Graph Transformation Units Guided by a SAT Solver
|
|
|
|
Autor:
|
|
Hans-Jörg Kreowski, Susanne Kuske, Robert Wille |
| Konferenz: |
|
International Conference on Graph Transformations (ICGT) |
Referenz:
|
| pp. 27-42, Enschede, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Synthesizing Multiplier in Reversible Logic
|
|
|
|
Autor:
|
|
Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 335-340, Vienna, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Window Optimization of Reversible and Quantum Circuits
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 431-435, Vienna, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» A Better-Than-Worst-Case Robustness Measure
|
|
|
|
Autor:
|
|
Stefan Frehse, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 78-83, Vienna, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Enhancing Debugging of Multiple Missing Control Errors in Reversible Logic
|
|
|
|
Autor:
|
|
Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler
|
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 465-470, Rhode Island, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Improving CNF Representations in SAT-based ATPG for Industrial Circuits using BDDs
|
|
|
|
Autor:
|
|
Daniel Tille, Stephan Eggersglüß, René Krenz-Bååth, Juergen Schloeffel, Rolf Drechsler |
| Konferenz: |
|
15th IEEE European Test Symposium (ETS) |
Referenz:
|
| pp. 176-181, Prag, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions
|
|
|
|
Autor:
|
|
Alexander Finder, Rolf Drechsler |
| Konferenz: |
|
40th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 150-155, Barcelona, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Efficient Simulation-based Debugging of Reversible Logic
|
|
|
|
Autor:
|
|
Stefan Frehse, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
40th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 156-161, Barcelona, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Reducing Reversible Circuit Cost by Adding Lines
|
|
|
|
Autor:
|
|
D. Michael Miller, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
40th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 217-222, Barcelona, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Efficient Test Generation with Maximal Crosstalk-Induced Noise using Unconstrained Aggressor Excitation
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS) |
Referenz:
|
| pp. 649-652, Paris, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Using QBF to Increase Accuracy of SAT-Based Debugging
|
|
|
|
Autor:
|
|
Andre Sülflow, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS) |
Referenz:
|
| pp.641-644, Paris, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Verifying UML/OCL Models Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1341-1344, Dresden, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Timing Arc Based Logic Analysis for False Noise Reduction
|
|
|
|
Autor:
|
|
Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler |
| Konferenz: |
|
IEEE/ACM International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| pp. 225-230, San Jose, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Anwendungsbezogene Analyse der Robustheit von Digitalen Schaltungen
|
|
|
|
Autor:
|
|
Andre Sülflow, Stefan Frehse, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) |
Referenz:
|
| pp. 45-52, Stuttgart, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Structural Heuristics for SAT-based ATPG
|
|
|
|
Autor:
|
|
Daniel Tille, Stephan Eggersglüß, Hoang M. Le, Rolf Drechsler |
| Konferenz: |
|
17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2009) |
Referenz:
|
| pp. 77-82, Florianópolis, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Speeding up SAT-based ATPG using Dynamic Clause Activation
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
| Konferenz: |
|
18th Asian Test Symposium (ATS'09) |
Referenz:
|
| pp. 177-182, Taichung, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Deterministc Algorithms for ATPG under Leakage Constraints
|
|
|
|
Autor:
|
|
Görschwin Fey |
| Konferenz: |
|
18th Asian Test Symposium (ATS'09) |
Referenz:
|
| Taichung, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automatic Debugging of System-on-a-Chip Designs
|
|
|
|
Autor:
|
|
Frank Rogin, Rolf Drechsler, Steffen Rülke |
| Konferenz: |
|
IEEE International SOC Conference (SOCC) |
Referenz:
|
| Belfast, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» SAT-Based ATPG Testing of Inter- and Intra-Gate Bridging Faults
|
|
|
|
Autor:
|
|
Toru Nakura, Yutaro Tatemura, Görschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada |
| Konferenz: |
|
European Conference on Circuit Theory and Design |
Referenz:
|
| Antalya, 2009
|
» SMT-based Stimuli Generation in the SystemC Verification Library
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 1-6, Sophia Antipolis, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Robustness Check for Multiple Faults using Formal Techniques
|
|
|
|
Autor:
|
|
Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 85-90, Patras, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Synthesizing Reversible Circuits for Irreversible Functions
|
|
|
|
Autor:
|
|
D. Michael Miller, Robert Wille, Gerhard W. Dueck |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 749-756, Patras, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» BDD-based Synthesis of Reversible Logic for Large Functions
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| pp. 270-275, San Francisco, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Computing Bounds for Fault Tolerance using Formal Techniques
|
|
|
|
Autor:
|
|
Görschwin Fey, Andre Sülflow, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| pp. 190-195, San Francisco, USA, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Generating an Efficient Instruction Set Simulator from a Complete Property Suite
|
|
|
|
Autor:
|
|
Ulrich Kühne, Sven Beyer, Christian Pichler |
| Konferenz: |
|
IEEE/IFIP International Symposium on Rapid System Prototyping (RSP) |
Referenz:
|
| pp. 109-115, Paris, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» WoLFram - A Word Level Framework for Formal Verification
|
|
|
|
Autor:
|
|
Andre Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
IEEE/IFIP International Symposium on Rapid System Prototyping (RSP) |
Referenz:
|
| pp. 11-17, Paris, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» A Fast Untestability Proof for SAT-based ATPG
|
|
|
|
Autor:
|
|
Daniel Tille, Rolf Drechsler |
| Konferenz: |
|
12th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems |
Referenz:
|
| pp. 38-43, Liberec, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Increasing Robustness of SAT-based Delay Test Generation using Efficient Dynamic Learning Techniques
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
14th IEEE European Test Symposium (ETS) |
Referenz:
|
| pp. 81-86, Sevilla, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Contradictory Antecedent Debugging in Bounded Model Checking
|
|
|
|
Autor:
|
|
Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 173-176, Boston, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Evaluation of Cardinality Constraints on SMT-based Debugging
|
|
|
|
Autor:
|
|
Andre Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
39th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 298-303, Naha, Okinawa, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Equivalence Checking of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler |
| Konferenz: |
|
39th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 324-330, Naha, Okinawa, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Approximate BDD Minimization by Weighted A*
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'09) |
Referenz:
|
| Taipei, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Overcoming Limitations of the SystemC Data Introspection
|
|
|
|
Autor:
|
|
Christian Genz, Rolf Drechsler |
| Konferenz: |
|
Design Automation and Test in Europe (DATE)
|
Referenz:
|
| pp. 590-593, Nice, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Property Analysis and Design Understanding
|
|
|
|
Autor:
|
|
Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE)
|
Referenz:
|
| pp. 1246-1249, Nice, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Debugging of Toffoli Networks
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1284-1289, Nice, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Increasing the Accuracy of SAT-based Debugging
|
|
|
|
Autor:
|
|
Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1326-1332, Nice, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Reversible Logic Synthesis with Output Permutation
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
22nd International Conference on VLSI Design |
Referenz:
|
| pp. 189-194, New Delhi, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Formaler Nachweis der Fehlertoleranz von Schaltkreisen
|
|
|
|
Autor:
|
|
Görschwin Fey, Andre Sülflow, Stefan Frehse, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
GMM/GI/ITG-Fachtagung: Zuverlässigkeit und Entwurf (ZuE 2008) |
Referenz:
|
| pp. 75-82, Ingolstadt, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Targeting Leakage Constraints during ATPG
|
|
|
|
Autor:
|
|
Görschwin Fey, Sathoshi Komatsu, Yasuo Furukawa, Masahiro Fujita |
| Konferenz: |
|
Asian Test Symposium (ATS) |
Referenz:
|
| pp. 225-230, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Fault Effects in FlexRay-Based Networks with Hybrid Topology
|
|
|
|
Autor:
|
|
Mehdi Dehbashi, Vahid Lari, Seyed Ghassem Miremadi, Mohammad Shokrollah-Shirazi |
| Konferenz: |
|
3rd IEEE International Conference on Availability, Reliability and Security (ARES) |
Referenz:
|
| pp. 491-496, Barcelona, Spain, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Verification of PLC Programs using Formal Proof Techniques
|
|
|
|
Autor:
|
|
Andre Sülflow, Rolf Drechsler |
| Konferenz: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008) |
Referenz:
|
| pp. 43-50, Budapest, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Efficient Formal Verification of Track Vacancy Detection Sections
|
|
|
|
Autor:
|
|
Sebastian Kinder und Rolf Drechsler |
| Konferenz: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008)
|
Referenz:
|
| pp. 233-240, Budapest, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking
|
|
|
|
Autor:
|
|
Robert Wille, Görschwin Fey, Marc Messing, Gerhard
Angst, Lothar Linhard, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 542-549, Parma, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Contradiction Analysis for Constraint-based Random Simulation
|
|
|
|
Autor:
|
|
Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 130-135, Stuttgart, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| pp. 411-416, Montpellier, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» RevLib: An Online Resource for
Reversible Functions and Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Referenz:
|
| pp. 220-225, Dallas, 2008
RevLib is available at www.revlib.org
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Exact Synthesis of Elementary Quantum Gate
Circuits for Reversible Functions with Don’t Cares
|
|
|
|
Autor:
|
|
Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Referenz:
|
| pp. 214-219, Dallas, 2008
Received IEEE Young Researcher Award
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» On the Influence of Boolean Encodings in SAT-based ATPG for Path Delay Faults
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Referenz:
|
| pp. 94-99, Dallas, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Using Unsatisfiable Cores to Debug Multiple Design Errors
|
|
|
|
Autor:
|
|
Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
| Konferenz: |
|
IEEE Great Lakes Symposium on VLSI (GLSVLSI'08) |
Referenz:
|
| pp. 77-82, Orlando, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Process Variations Aware Robust on-Chip Bus Architecture Synthesis for MPSoCs
|
|
|
|
Autor:
|
|
Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'08) |
Referenz:
|
| Seattle, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
» A Basis for Formal Robustness Checking
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler
|
| Konferenz: |
|
International Symposium on Quality of Electronic Design (ISQED) |
Referenz:
|
| San Jose, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Adaptive Branch and Bound using SAT to Estimate False Crosstalk
|
|
|
|
Autor:
|
|
Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler
|
| Konferenz: |
|
International Symposium on Quality of Electronic Design (ISQED) |
Referenz:
|
| San Jose, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Automatic Generation of Complex Properties for Hardware Designs
|
|
|
|
Autor:
|
|
Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler Steffen Rülke |
| Konferenz: |
|
Design, Automation, and Test in Europe (DATE) |
Referenz:
|
| Munich, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs
|
|
|
|
Autor:
|
|
Sujan Pandey, Rolf Drechsler |
| Konferenz: |
|
Design, Automation, and Test in Europe (DATE) |
Referenz:
|
| Munich, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Quantified Synthesis of Reversible Logic
|
|
|
|
Autor:
|
|
Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große |
| Konferenz: |
|
Design, Automation, and Test in Europe (DATE) |
Referenz:
|
| pp. 1015-1020, Munich, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Robust On-Chip Bus architecture Synthesis for MPSoCs Under Random Tasks Arrival
|
|
|
|
Autor:
|
|
Sujan Pandey, Rolf Drechsler |
| Konferenz: |
|
13th Asia and South Pacific Design Automation Conference, (ASP-DAC 2008) |
Referenz:
|
| Seoul, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Fast Exact Toffoli Network Synthesis of Reversible Logic
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große |
| Konferenz: |
|
IEEE International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| pp. 60-64, San Jose, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» SWORD: A SAT like Prover Using Word Level Information
|
|
|
|
Autor:
|
|
Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC) |
Referenz:
|
| pp. 88-93, Atlanta, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Co-Synthesis of Custom On-Chip Bus and Memory for
MPSoC Architectures
|
|
|
|
Autor:
|
|
Sujan Pandey, Christian Genz, Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration Systems and Systems on Chip (VLSI-SoC) |
Referenz:
|
| pp. 304-307, Atlanta, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Improving Test Pattern Compactness in SAT-based ATPG
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
16th Asian Test Symposium (ATS’07) |
Referenz:
|
| pp. 445-450, Beijing, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» An Integrated SystemC Debugging Environment
|
|
|
|
Autor:
|
|
Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke |
| Konferenz: |
|
Forum on Specification & Design Languages (FDL) |
Referenz:
|
| pp. 140-145, Barcelona, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Measuring the Quality of a SystemC Testbench by using Code Coverage Technqiues
|
|
|
|
Autor:
|
|
Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 146-151, Barcelona, 2007
Received Best Paper Award
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Evaluation of Babbling Idiot Failures in FlexRay-Based Networks
|
|
|
|
Autor:
|
|
Vahid Lari, Mehdi Dehbashi, Seyed Ghassem Miremadi, Mojtaba Amiri |
| Konferenz: |
|
7th IFAC International Conference on Fieldbuses and Networks in Industrial and Embedded Systems (FET) |
Referenz:
|
| pp. 399-406, Toulouse, France, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Assessment of Message Missing Failures in FlexRay-Based Networks
|
|
|
|
Autor:
|
|
Vahid Lari, Mehdi Dehbashi, Seyed Ghassem Miremadi, Navid Farazmand |
| Konferenz: |
|
13th IEEE/IFIP Pacific Rim International Symposium on Dependable Computing (PRDC) |
Referenz:
|
| pp. 191-194, Melbourne, Australia, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Proving Completeness of Properties in Formal Verification of Counting Heads for Railways
|
|
|
|
Autor:
|
|
Sebastian Kinder and Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD)
Architectures, Methods and Tools |
Referenz:
|
| Lübeck, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» On the Construction of Small Fully Testable Circuits with Low Depth
|
|
|
|
Autor:
|
|
Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD)
Architectures, Methods and Tools |
Referenz:
|
| Lübeck, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Hardware Project Management - What we Can Learn from the Software Development Process for Hardware Design?
|
|
|
|
Autor:
|
|
Rolf Drechsler, Andreas Breiter |
| Konferenz: |
|
2nd International Conference on Software and Data Technologies |
Referenz:
|
| Barcelona, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel |
| Konferenz: |
|
Fifth ACM-IEEE International Conference on
Formal Methods and Models for Codesign (MEMOCODE'2007) |
Referenz:
|
| pp. 181-187, Nice, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
|
|
|
|
Autor:
|
|
Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07) |
Referenz:
|
| pp. 165-170, Porto Alegre, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^m) in SystemC
|
|
|
|
Autor:
|
|
Andre Sülflow, Rolf Drechsler |
| Konferenz: |
|
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07) |
Referenz:
|
| pp. 42, Oslo, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL
|
|
|
|
Autor:
|
|
Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler |
| Konferenz: |
|
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07) |
Referenz:
|
| Oslo, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Experimental Studies on SAT-based ATPG for Gate Delay Faults
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
| Konferenz: |
|
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07) |
Referenz:
|
| Oslo, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Visualization of SystemC Designs
|
|
|
|
Autor:
|
|
Christian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS) |
Referenz:
|
| pp. 413-416,
New Orleans, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» SAT-based ATPG for Path Delay Faults in Sequential Circuits
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'07) |
Referenz:
|
| pp. 3671-3674, New Orleans, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Improvements for Constraint Solving in the SystemC Verification Library
|
|
|
|
Autor:
|
|
Daniel Große, Rüdiger Ebendt, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 493-496, Stresa, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Exact SAT-based Toffoli Network Synthesis
|
|
|
|
Autor:
|
|
Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 96-101, Stresa, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Ein formaler Ansatz zum Robustheitsnachweis
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
Zuverlässigkeit und Entwurf |
Referenz:
|
| München, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Robust Multi-Objective Optimization in High Dimensional Spaces
|
|
|
|
Autor:
|
|
André Sülflow, Nicole Drechsler, Rolf Drechsler |
| Konferenz: |
|
Fourth International Conference on Evolutionary Multi-Criterion Optimization |
Referenz:
|
| pp. 715-726, Matsushima, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Estimating Functional Coverage in Bounded Model Checking
|
|
|
|
Autor:
|
|
Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1176-1181, Nice, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Modeling and Formal Verification of Counting Heads for Railways
|
|
|
|
Autor:
|
|
Sebastian Kinder, Rolf Drechsler |
| Konferenz: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2007) |
Referenz:
|
| Braunschweig, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Reusing Learned Information in SAT-based ATPG
|
|
|
|
Autor:
|
|
Görschwin Fey, Tim Warode, Rolf Drechsler |
| Konferenz: |
|
20th International Conference on VLSI Design |
Referenz:
|
| Bangalore, 2007
|
Hyperlink:
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| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automatic Fault Localization for Property Checking
|
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|
|
Autor:
|
|
Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
| Konferenz: |
|
Haifa Verification Conference |
Referenz:
|
| Haifa, 2006
|
Hyperlink:
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| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Technical Documentation of Software and Hardware
in Embedded Systems
|
|
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Autor:
|
|
Beate Muranko, Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC 2006) |
Referenz:
|
| Nice, France 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» A Framework for Quasi-Exact Optimization using Relaxed Best-First Search
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Rolf Drechsler |
| Konferenz: |
|
29th Annual German Conference on Artificial Intelligence (KI'06) |
Referenz:
|
| Bremen, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Non-Intrusive High-level SystemC Debugging
|
|
|
|
Autor:
|
|
Frank Rogin, Erhard Fehlauer, Steffen Ruelke, Sebastian Ohnewald, Thomas Berndt |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Darmstadt, 2006
|
Hyperlink:
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| [Link zur Konferenz]
|
» HW/SW Co-Verification of Embedded Systems using Bounded Model Checking
|
|
|
|
Autor:
|
|
Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 43-48, Philadelphia, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Efficiency of Multiple-Valued Encoding in SAT-based ATPG
|
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|
|
Autor:
|
|
Görschwin Fey, Junhao Shi, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multiple-Valued Logic (ISMVL '06) |
Referenz:
|
| Singapore, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Integrating Observability Don't Cares in All-Solution SAT Solvers
|
|
|
|
Autor:
|
|
Sean Safarpour, Andreas Veneris, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'06) |
Referenz:
|
| Kos, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» On the Sensitivity of BDDs with Respect to Path-Related Objective Functions
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'06) |
Referenz:
|
| Kos, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» System Exploration of SystemC Designs
|
|
|
|
Autor:
|
|
Christian Genz, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| pp. 335-340, Karlsruhe, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» On the Relation Between Simulation-based and SAT-based Diagnosis
|
|
|
|
Autor:
|
|
Görschwin Fey, Sean Safarpour, Andreas Veneris, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1139-1144, Munich, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Efficient Minimization of Fully Testable 2-SPP Networks
|
|
|
|
Autor:
|
|
Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1300-1305, Munich, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks
|
|
|
|
Autor:
|
|
Görschwin Fey, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1225-1226, Munich, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» An Integrated Approach for Combining BDD and SAT Provers
|
|
|
|
Autor:
|
|
Rolf Drechsler, Görschwin Fey, Sebastian Kinder |
| Konferenz: |
|
International Conference on VLSI Design |
Referenz:
|
| Hyderabad, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Experimental Studies on SAT-based Test Pattern Generation for Industrial Circuits
|
|
|
|
Autor:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke |
| Konferenz: |
|
International Conference on ASIC (ASICON 2005)
|
Referenz:
|
| pp. 967-970, Shanghai, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Post-Verification Debugging of Hierarchical Designs
|
|
|
|
Autor:
|
|
Moayad Ali, Sean Safarpour, Andreas Veneris, Magdy Abadir, Rolf Drechsler |
| Konferenz: |
|
IEEE International Conference on Computer Aided Design (ICCAD'05) |
Referenz:
|
| pp. 871-876, San Jose, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Exact BDD Minimization for Path-Related Objective Functions
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC 2005) |
Referenz:
|
| pp. 525-530, Perth, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PS:
|
| [hier ansehen]
|
» Acceleration of SAT-based Iterative Property Checking
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Correct Hardware Design and Verification Methods (CHARME) |
Referenz:
|
| pp. 349-353, Saarbrücken, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Quasi-Exact BDD Minimization using Relaxed Best-First Search
|
|
|
|
Autor:
|
|
Rüdiger Ebendt and Rolf Drechsler |
| Konferenz: |
|
IEEE Annual Symposium on VLSI (ISVLSI '05) |
Referenz:
|
| pp. 59-64, Tampa, Florida, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» PASSAT: Efficient SAT-based Test Pattern Generation
|
|
|
|
Autor:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
| Konferenz: |
|
IEEE Annual Symposium on VLSI (ISVLSI '05) |
Referenz:
|
| pp.212-217, Tampa, Florida, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PS:
|
| [hier ansehen]
|
» Controlling the Memory During Manipulation of Word-Level Decision Diagrams
|
|
|
|
Autor:
|
|
Sebastian Kinder, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL 2005) |
Referenz:
|
| pp. 250-255, Calgary, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PS:
|
| [hier ansehen]
|
» Utilizing Don't Care States in SAT-based Bounded Sequential Problems
|
|
|
|
Autor:
|
|
Sean Safarpour, Görschwin Fey, Andreas Veneris, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI'05) |
Referenz:
|
| Chicago, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» CheckSyC: An Efficient Property Checker for RTL SystemC Designs
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'05) |
Referenz:
|
| pp. 4167-4170, Kobe, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Bridging Fault Testability of BDD Circuits
|
|
|
|
Autor:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005) |
Referenz:
|
| pp. 188-191 Shanghai, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Lower Bounds for Dynamic BDD Reordering
|
|
|
|
Autor:
|
|
Rüdiger Ebendt and Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005) |
Referenz:
|
| pp. 579-582, Shanghai, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automated Verification For Train Control Systems
|
|
|
|
Autor:
|
|
Jan Peleska, Daniel Große, Anne E. Haxthausen, Rolf Drechsler |
| Konferenz: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2004) |
Referenz:
|
| pp. 252-265, Braunschweig, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Debugging Sequential Circuits Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Moayad Ali, Andreas Veneris, Sean Safarpour, Magdy Abadir, Rolf Drechsler, Alexander Smith |
| Konferenz: |
|
IEEE International Conference on Computer Aided Design (ICCAD'04) |
Referenz:
|
| pp. 204-209, San Jose, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» BDD Circuit Optimization for Path Delay Fault Testability
|
|
|
|
Autor:
|
|
Görschwin Fey, Junhao Shi, Rolf Drechsler |
| Konferenz: |
|
Euromicro Symposium on Digital System Design (DSD'2004) |
Referenz:
|
| pp. 168-172, Rennes, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PS:
|
| [hier ansehen]
|
» Checkers for SystemC Designs
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Second ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2004) |
Referenz:
|
| pp. 171-178, San Diego, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Reduction of Sizes of Multiple-Valued Decision Diagrams by Copy Properties
|
|
|
|
Autor:
|
|
Dragan Jankovic, Radomir Stankovic, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2004) |
Referenz:
|
| pp. 229-234, Toronto, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Algorithms for Taylor Expansion Diagrams
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler, Maciej Ciesielski |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2004) |
Referenz:
|
| pp. 235-240, Toronto, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PS:
|
| [hier ansehen]
|
» Placement and Routing Optimization for Circuits Derived from BDDs
|
|
|
|
Autor:
|
|
Thomas Eschbach, Rolf Drechsler, Bernd Becker |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'04) |
Referenz:
|
| Vancouver, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Cost-Efficient Block Verification for a UMTS Up-Link
Chip-Rate Coprocessor
|
|
|
|
Autor:
|
|
Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey |
| Konferenz: |
|
IEEE Design, Automation and Test in Europe
|
Referenz:
|
| Vol. I, pp. 162-167, Paris, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Managing Don't Cares in Boolean
Satisfiability
|
|
|
|
Autor:
|
|
Sean Safarpour, Andreas Veneris, Rolf Drechsler, Joanne Hang |
| Konferenz: |
|
IEEE Design, Automation and Test in Europe
|
Referenz:
|
| Vol. I, pp. 260-265, Paris, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Improving Simulation-Based Verification by Means of Formal Methods
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
|
Referenz:
|
| pp. 640-643, Yokohama, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Minimization of the Expected Path Length in BDDs Based on Local Changes
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
|
Referenz:
|
| pp. 866-871, Yokohama, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Combining Ordered Best-First Search with Branch and Bound for Exact BDD Minimization
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
|
Referenz:
|
| pp. 876-879, Yokohama, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Hardware Project Management – What we Can Learn from the Software Development Process for Hardware Design?
|
|
|
|
Autor:
|
|
Rolf Drechsler, Andreas Breiter |
| Konferenz: |
|
4th Conference of Informatics and Information Technologies |
Referenz:
|
| Bitola, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Minimizing the Number of One-Paths in BDDs by an Evolutionary Algorithm
|
|
|
|
Autor:
|
|
Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler |
| Konferenz: |
|
Congress on Evolutionary Computation 2003 (CEC2003) |
Referenz:
|
| Vol.3, pp.1724-1731, Canberra, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» Testability of SPP Three-Level Logic Networks
|
|
|
|
Autor:
|
|
Valentina Ciriani, Anna Bernasconi, Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (VLSI'03) |
Referenz:
|
| pp. 331-336, Darmstadt, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Exploration of Sequential Depth by Evolutionary Algorithms
|
|
|
|
Autor:
|
|
Nicole Drechsler, Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (VLSI'03) |
Referenz:
|
| pp. 81-85, Darmstadt, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
|
|
|
|
Autor:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
Twelfth Asian Test Symposium (ATS03)
|
Referenz:
|
| p.290-293,
Xi'an, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PS:
|
| [hier ansehen]
|
» Efficient Automatic Visualization of SystemC Designs
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst |
| Konferenz: |
|
Forum on Specification & Design Languages (FDL'03) |
Referenz:
|
| pp. 646-657, Frankfurt, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Finding Good Counter-Examples to Aid Design Verification
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
First ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2003) |
Referenz:
|
| pp. 51-52, Mont Saint-Michel, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» Fast Heuristics for the Edge Coloring of Large Graphs
|
|
|
|
Autor:
|
|
Mario Hilgemeier, Nicole Drechsler and Rolf Drechsler |
| Konferenz: |
|
Euromicro Symposium on Digital System Design (DSD'2003) |
Referenz:
|
| pp. 230-237, Antalya, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits
|
|
|
|
Autor:
|
|
Rolf Drechsler, Junhao Shi and Görschwin Fey |
| Konferenz: |
|
IEEE Great Lakes Symposium on VLSI (GLSV'03) |
Referenz:
|
| p. 80-83, Washington, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» Efficient Minimization of Multi-Valued Decision Diagrams for Incompletely Specified Functions
|
|
|
|
Autor:
|
|
Denis Popel and Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003) |
Referenz:
|
| pp. 241-246, Tokyo, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PS:
|
| [hier ansehen]
|
» Augmented Sifting for Multiple-Valued Decision Diagrams
|
|
|
|
Autor:
|
|
Michael Miller and Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003) |
Referenz:
|
| pp. 375-382, Tokyo, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Modeling Multi-Valued Circuits in SystemC
|
|
|
|
Autor:
|
|
Daniel Große, Görschwin Fey and Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003) |
Referenz:
|
| pp. 281-286, Tokyo, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» Using Games for Benchmarking and Representing the Complete Solution Space Using Symbolic Techniques
|
|
|
|
Autor:
|
|
Görschwin Fey, Sebastian Kinder and Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003) |
Referenz:
|
| pp. 361-366, Tokyo, 2003
|
PS:
|
| [hier ansehen]
|
» Formal Verification of LTL Formulas for SystemC Designs
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'03) |
Referenz:
|
| pp. V:245-V:248, Bangkok, 2003
|
PDF:
|
| [hier ansehen]
|
» Reducing the Number of Variable Movements in Exact BDD Minimization
|
|
|
|
Autor:
|
|
Rüdiger Ebendt |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'03) |
Referenz:
|
| pp. V:605-V:608, Bangkok, 2003
|
PDF:
|
| [hier ansehen]
|
» Synthesizing Checkers for On-line Verification of System-on-Chip Designs
|
|
|
|
Autor:
|
|
Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'03) |
Referenz:
|
| pp. IV:748-IV:751, Bangkok, 2003
|
PDF:
|
| [hier ansehen]
|
» Minimization of Transitions by Complementation and Resequencing using Evolutionary Algorithms
|
|
|
|
Autor:
|
|
Rolf Drechsler and Nicole Drechsler |
| Konferenz: |
|
21st IASTED International Multi-Conference Applied Informatics (AI 2003) |
Referenz:
|
| Innsbruck, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PS:
|
| [hier ansehen]
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» Combination of Lower Bounds in Exact BDD Minimization
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Autor:
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Rüdiger Ebendt, Wolfgang Günther and Rolf Drechsler |
| Konferenz: |
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IEEE Design, Automation and Test in Europe (DATE'03) |
Referenz:
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| pp. 758-763, Munich, 2003
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» SPIHT implemented in a XC4000 device
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Autor:
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Jörg Ritter, Görschwin Fey and Paul Molitor |
| Konferenz: |
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IEEE The 45rd Midwest Symposium on Circuits and Systems (MWSCAS'2002) |
Referenz:
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| volume I, pages 239-242, Tulsa, 2002
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PDF:
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| [hier ansehen]
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» Utilizing BDDs for disjoint SOP minimization
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Autor:
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Görschwin Fey and Rolf Drechsler |
| Konferenz: |
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IEEE The 45rd Midwest Symposium on Circuits and Systems (MWSCAS'2002) |
Referenz:
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| volume II, pages 306-309, Tulsa, 2002
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PS:
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| [hier ansehen]
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» Minimizing the Number of Paths in BDDs
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Autor:
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Görschwin Fey and Rolf Drechsler |
| Konferenz: |
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15th Symposium on Integrated Circuits and System Design |
Referenz:
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| pages 359-364, Porto Alegre, 2002
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
|
| [hier ansehen]
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PS:
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| [hier ansehen]
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» Crossing Reduction by Windows Optimization
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Autor:
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Thomas Eschbach, Wolfgang Günther, Rolf Drechsler and Bernd Becker |
| Konferenz: |
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10th International Symposium on Graph Drawing (GD'2002) |
Referenz:
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| LNCS 2528, pp. 285-294, Irvine, 2002
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PDF:
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| [hier ansehen]
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PS:
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| [hier ansehen]
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» Reachability Analysis for Formal Verification of SystemC
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Autor:
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Rolf Drechsler and Daniel Große |
| Konferenz: |
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Euromicro Symposium on Digital System Design (DSD'2002) |
Referenz:
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| pages 337-340, Dortmund, 2002
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Decision Diagrams Optimization Using Copy Properties
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Autor:
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Dragan Jankovic, Radomir Stankovic and Rolf Drechsler |
| Konferenz: |
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Euromicro Symposium on Digital System Design (DSD'2002) |
Referenz:
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| pages 236-243, Dortmund, 2002
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Recursive Bi-Partitioning of Netlists for Large Number of Partitions
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Autor:
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Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard and Gerhard Angst |
| Konferenz: |
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Euromicro Symposium on Digital System Design (DSD'2002) |
Referenz:
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| pages 38-44, Dortmund, 2002
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» JADE: Implementation and Visualization of a BDD Package in JAVA
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Autor:
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Rolf Drechsler |
| Konferenz: |
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IEEE Design, Automation and Test in Europe (DATE'02) - User Forum |
Referenz:
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| page 259, Paris, 2002
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Computing Walsh, Arithmetic and Reed-Muller Spectral Decision Diagrams Using Graph Transformations
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Autor:
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Whitney Townsend, Mitch Thornton, Rolf Drechsler and Michael Miller |
| Konferenz: |
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IEEE Great Lakes Symposium on VLSI (GLSV'02) |
Referenz:
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| pp. 178-183, New York, 2002
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PDF:
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| [hier ansehen]
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» Switching Activity Estimation for Finite State Machines for Low Power Synthesis (Poster)
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Autor:
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Mikael Kerttu, Per Lindgren, Mitch Thornton and Rolf Drechsler |
| Konferenz: |
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IEEE International Symposium on Circuits and Systems (ISCAS'02) |
Referenz:
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| Scottsdale, 2002
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
|
| [hier ansehen]
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PS:
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| [hier ansehen]
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» Multi-Output Timed Shannon Circuits
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Autor:
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Mitch Thorton, Rolf Drechsler and Michael Miller |
| Konferenz: |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002) |
Referenz:
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| pages 47-52, Pittsburgh, 2002
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
|
| [hier ansehen]
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PS:
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| [hier ansehen]
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» Evaluation of Static Variable Ordering Heuristics for MDD Construction
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Autor:
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Rolf Drechsler |
| Konferenz: |
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IEEE International Symposium on Multi-Valued Logic (ISMVL'2002) |
Referenz:
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| pages 254-260, Boston, 2002
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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PS:
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| [hier ansehen]
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» On the Construction of Multi-Valued Decision Diagrams
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Autor:
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Michael Miller and Rolf Drechsler |
| Konferenz: |
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IEEE International Symposium on Multi-Valued Logic (ISMVL'2002) |
Referenz:
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| pages 245-253, Boston, 2002
|
Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Efficient Calculation of Fixed-Polarity Polynomial Expressions for Multi-Valued Logic Functions
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Autor:
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Dragan Jankovic, Radomir Stankovic and Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2002) |
Referenz:
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| pages 76-82, Boston, 2002
|
Hyperlink:
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| [Link zur Konferenz]
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PDF:
|
| [hier ansehen]
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PS:
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| [hier ansehen]
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» On the Relation Between SAT and BDDs for Equivalence Checking
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Autor:
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Sherif Reda, Rolf Drechsler and Alex Orailoglu |
| Konferenz: |
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International Symposium on Quality of Electronic Design (ISQED 2002) |
Referenz:
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| pages 394-399, San Jose, 2002
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
|
| [hier ansehen]
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» RTL-Datapath Verification using Integer Linear Programming
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Autor:
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Raik Brinkmann and Rolf Drechsler |
| Konferenz: |
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IEEE VLSI Design'02 & Asia and South Pacific Design Automation Conference |
Referenz:
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| pages 741-746, Bangalore, 2002
|
Hyperlink:
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| [Link zur Konferenz]
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PDF:
|
| [hier ansehen]
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PS:
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| [hier ansehen]
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» Fast and Efficient Equivalence Checking based on NAND-BDDs
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Autor:
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Rolf Drechsler and Mitch Thornton |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (VLSI'01) |
Referenz:
|
| pages 401-405, Montpellier, 2001
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
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» Formal Verification on Register Transfer Level - Utilizing High-Level Information for Hardware Verification
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Autor:
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Peer Johannsen and Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (VLSI'01) |
Referenz:
|
| pages 127-132, Montpellier, 2001
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
