» Complete and Effective Robustness Checking by Means of Interpolation
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Autor:
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Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav and Rolf Drechsler |
| Konferenz: |
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Formal Methods in Computer-Aided Design (FMCAD'12) |
Referenz:
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| Cambridge, UK, 2012, page 82-90
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Determining the Minimal Number of SWAP Gates for Multi-dimensional Nearest Neighbor Quantum Circuits
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Autor:
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Aaron Lye, Robert Wille, Rolf Drechsler |
| Konferenz: |
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Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
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| Chiba/Tokyo, 2015
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Towards a Cost Metric for Nearest Neighbor Constraints in Reversible Circuits
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Autor:
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Abhoy Kole, Kamalika Datta, Indranil Sengupta, Robert Wille
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| Konferenz: |
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Reversible Computation |
Referenz:
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| Grenoble, France, 2015
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Exact Synthesis of Ternary Reversible Functions using Ternary Toffoli Gates
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Autor:
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Abhoy Kole, P. Mercy Nesa Rani, Kamalika Datta, Indranil Sengupta, Rolf Drechsler |
| Konferenz: |
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47th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| Novi Sad, Serbia, 2017
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Hyperlink:
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| [Link zur Konferenz]
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» Latency Analysis for Sequential Circuits
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Autor:
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Alexander Finder, André Sülflow, Görschwin Fey |
| Konferenz: |
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16th IEEE European Test Symposium (ETS) |
Referenz:
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| pp. 129-134, Trondheim, 2011
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Evaluating Debugging Algorithms from a Qualitative Perspective
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Autor:
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Alexander Finder, Görschwin Fey |
| Konferenz: |
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Forum on specification & Design Languages (FDL) |
Referenz:
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| pp. 37-42, Southampton, 2010
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Debugging HDL Designs Based on Functional Equivalences with High-Level Specifications
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Autor:
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Alexander Finder, Jan-Philipp Witte, Görschwin Fey |
| Konferenz: |
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16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
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| Karlovy Vary, Czech Republic, 2013
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions
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Autor:
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Alexander Finder, Rolf Drechsler |
| Konferenz: |
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40th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| pp. 150-155, Barcelona, 2010
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» On the problems of realizing reliable and efficient ring oscillator PUFs on FPGAs.
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Autor:
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Alexander Wild, Georg T. Becker, Tim Güneysu |
| Konferenz: |
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Hardware-Oriented Security and Trust (HOST) 2016: 103-108 |
Referenz:
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| http://dx.doi.org/10.1109/HST.2016.7495565
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» Equivalence Checking Using Gröbner Bases
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Autor:
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Amr Sayed Ahmed, Daniel Große, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
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Formal Methods in Computer Aided Design (FMCAD) |
Referenz:
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| Mountain View, USA, 2016
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Formal Verification of Integer Multipliers by Combining Gröbner Basis with Logic Reduction
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Autor:
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Amr Sayed Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1048-1053, Dresden, Germany, 2016
Best Paper Candidate
|
Hyperlink:
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| [Link zur Konferenz]
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PDF:
|
| [hier ansehen]
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» Verification of the Decimal Floating-Point Square Root Operation,
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Autor:
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Amr Sayed Ahmed, Hossam Fahmy, Ulrich Kühne |
| Konferenz: |
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19th IEEE European Test Symposium, |
Referenz:
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| Paderborn, Germany, 2014.
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits
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Autor:
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Amr Sayed Ahmed, Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Konferenz: |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2015). |
Referenz:
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| pp. 1-6, Montpellier, France, 2015.
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Hyperlink:
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| [Link zur Konferenz]
|
PDF:
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| [hier ansehen]
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» Increasing the Accuracy of SAT-based Debugging
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Autor:
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Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1326-1332, Nice, 2009
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Hyperlink:
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| [Link zur Konferenz]
|
PDF:
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| [hier ansehen]
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» Using Unsatisfiable Cores to Debug Multiple Design Errors
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Autor:
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Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
| Konferenz: |
|
IEEE Great Lakes Symposium on VLSI (GLSVLSI'08) |
Referenz:
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| pp. 77-82, Orlando, 2008
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Hyperlink:
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| [Link zur Konferenz]
|
PDF:
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| [hier ansehen]
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» Using QBF to Increase Accuracy of SAT-Based Debugging
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Autor:
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Andre Sülflow, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
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IEEE International Symposium on Circuits and Systems (ISCAS) |
Referenz:
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| pp.641-644, Paris, 2010
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Hyperlink:
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| [Link zur Konferenz]
|
PDF:
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| [hier ansehen]
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» Robust Multi-Objective Optimization in High Dimensional Spaces
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Autor:
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André Sülflow, Nicole Drechsler, Rolf Drechsler |
| Konferenz: |
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Fourth International Conference on Evolutionary Multi-Criterion Optimization |
Referenz:
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| pp. 715-726, Matsushima, 2007
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Evaluation of Cardinality Constraints on SMT-based Debugging
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Autor:
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Andre Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
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39th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| pp. 298-303, Naha, Okinawa, 2009
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Automatic Fault Localization for Programmable Logic Controllers
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Autor:
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Andre Sülflow, Rolf Drechsler |
| Konferenz: |
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Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT) |
Referenz:
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| pp. 247-256, Braunschweig, 2010
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^m) in SystemC
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Autor:
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Andre Sülflow, Rolf Drechsler |
| Konferenz: |
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37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07) |
Referenz:
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| pp. 42, Oslo, 2007
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Verification of PLC Programs using Formal Proof Techniques
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Autor:
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Andre Sülflow, Rolf Drechsler |
| Konferenz: |
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Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008) |
Referenz:
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| pp. 43-50, Budapest, 2008
|
Hyperlink:
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| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
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» Anwendungsbezogene Analyse der Robustheit von Digitalen Schaltungen
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Autor:
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Andre Sülflow, Stefan Frehse, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
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GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) |
Referenz:
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| pp. 45-52, Stuttgart, 2009
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» WoLFram - A Word Level Framework for Formal Verification
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Autor:
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Andre Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler |
| Konferenz: |
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IEEE/IFIP International Symposium on Rapid System Prototyping (RSP) |
Referenz:
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| pp. 11-17, Paris, 2009
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Constraint-based Platform Variants Specification for Early System Verification
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Autor:
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Andreas Burger, Alexander Viehl, Andreas Braun, Finn Haedicke, Daniel Große, Oliver Bringmann, Wolgang Rosenstiel |
| Konferenz: |
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Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
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| pp. 800-805, Singapore, 2014
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Efficient Minimization of Fully Testable 2-SPP Networks
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Autor:
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Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa |
| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| pp. 1300-1305, Munich, 2006
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure
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Autor:
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Arighna Deb, Debesh Kumar Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
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| pp. 182-195, Victoria, Canada, 2013
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Hyperlink:
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| [Link zur Konferenz]
|
PDF:
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| [hier ansehen]
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» OR-Inverter Graphs for the Synthesis of Optical Circuits
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Autor:
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Arighna Deb, Robert Wille, Rolf Drechsler |
| Konferenz: |
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47th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| Novi Sad, Serbia, 2017
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Hyperlink:
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| [Link zur Konferenz]
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» An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization
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Autor:
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Arighna Deb, Robert Wille, Rolf Drechsler, Debesh Das |
| Konferenz: |
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45th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| Waterloo, Canada, 2015
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Hyperlink:
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| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
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» Requirement Phrasing Assistance using Automatic Quality Assessment
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Autor:
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Arman Allahyari-Abhari, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
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IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15) |
Referenz:
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| Belgrade, Serbia, 2015
|
Hyperlink:
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| [Link zur Konferenz]
|
PDF:
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| [hier ansehen]
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» An Examination of the NCV-v1 Quantum Library Based on Minimal Circuits
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Autor:
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Arman Allahyari-Abhari, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
45th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| Waterloo, Canada, 2015
|
Hyperlink:
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| [Link zur Konferenz]
|
PDF:
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| [hier ansehen]
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» Precise Error Determination of Approximated Components in Sequential Circuits with Model Checking
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Autor:
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Arun Chandrasekharan,
Mathias Soeken,
Daniel Große,
Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| Austin, USA, 2016
|
Hyperlink:
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| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
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» ProACt: A Processor for High Performance On-demand Approximate Computing
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Autor:
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Arun Chandrasekharan, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
27th ACM Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
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| Banff, Alberta, Canada, 2017
|
Hyperlink:
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| [Link zur Konferenz]
|
PDF:
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| [hier ansehen]
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» Yise - A novel Framework for Boolean Networks using Y-Inverter Graphs
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Autor:
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Arun Chandrasekharan, Daniel Große, Rolf Drechsler |
| Konferenz: |
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15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) |
Referenz:
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| Vienna, Austria, 2017
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Hyperlink:
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| [Link zur Konferenz]
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» Ensuring Safety and Reliability of IP-based System
Design – A Container Approach
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Autor:
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Arun Chandrasekharan, Kenneth Schmitz, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
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IEEE International Symposium on Rapid System Protoyping (RSP), 2015 |
Hyperlink:
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| [Link zur Konferenz]
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PDF:
|
| [hier ansehen]
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» Approximation-aware Rewriting of AIGs for Error Tolerant Applications
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Autor:
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Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
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| Konferenz: |
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International Conference on Computer Aided Design (ICCAD) |
Referenz:
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| Austin, USA, 2016
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
|
| [hier ansehen]
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» Technical Documentation of Software and Hardware
in Embedded Systems
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Autor:
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Beate Muranko, Rolf Drechsler |
| Konferenz: |
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IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC 2006) |
Referenz:
|
| Nice, France 2006
|
Hyperlink:
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| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
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» Recent Advances in SAT-based ATPG: Non-Standard Fault Models, Multi Constraints and Optimization
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Autor:
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Bernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer |
| Konferenz: |
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International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) |
Referenz:
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| pp. 1-10, Santorini, Greece, 2014
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Hyperlink:
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| [Link zur Konferenz]
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PDF:
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| [hier ansehen]
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» A Cube Pairing Approach for Synthesis of ESOP based Reversible Circuit
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Autor:
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Chandan Bandyopadhyay, Hafizur Rahaman, Rolf Drechsler |
| Konferenz: |
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44rd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Bremen, 2014
|
Hyperlink:
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| [Link zur Konferenz]
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» Overcoming Limitations of the SystemC Data Introspection
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Autor:
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Christian Genz, Rolf Drechsler |
| Konferenz: |
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Design Automation and Test in Europe (DATE)
|
Referenz:
|
| pp. 590-593, Nice, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
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» System Exploration of SystemC Designs
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Autor:
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Christian Genz, Rolf Drechsler |
| Konferenz: |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| pp. 335-340, Karlsruhe, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
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» Visualization of SystemC Designs
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Autor:
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Christian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard |
| Konferenz: |
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IEEE International Symposium on Circuits and Systems (ISCAS) |
Referenz:
|
| pp. 413-416,
New Orleans, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
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PS:
|
| [hier ansehen]
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» A Unified Formulation of Behavioral Semantics for SysML Models
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Autor:
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Christoph Hilken, Jan Peleska, Robert Wille |
| Konferenz: |
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International Conference on Model-Driven Engineering and Software Development |
Referenz:
|
| Angers, France, 2015
|
Hyperlink:
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| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
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» Verifying Consistency between Activity Diagrams and Their Corresponding OCL Contracts
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Autor:
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Christoph Hilken, Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Munich, Germany, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Secure and Private, yet Lightweight, Authentication for the IoT via PUF and CBKA
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|
Autor:
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|
Christopher Huth, Aydin Aysu, Jorge Guajardo, Paul Duplys, Tim Güneysu |
| Konferenz: |
|
ICISC 2016: 28-48 |
Referenz:
|
| http://dx.doi.org/10.1007/978-3-319-53177-9_2
|
» Secure software update and IP protection for untrusted devices in the Internet of Things via physically unclonable functions
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Autor:
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|
Christopher Huth, Paul Duplys, Tim Güneysu |
| Konferenz: |
|
IEEE International Conference on Pervasive Computing and Communication Workshops (PerCom Workshops) |
Referenz:
|
| pages 1-6, Sydney, Australia
|
Hyperlink:
|
| [Link zur Konferenz]
|
» On the Energy Cost of Channel Based Key Agreement
|
|
|
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Autor:
|
|
Christopher Huth, René Guillaume, Paul Duplys, Kumaragurubaran Velmurugan, Tim Güneysu |
| Konferenz: |
|
TrustED@CCS 2016: 31-41 |
Referenz:
|
| http://doi.acm.org/10.1145/2995289.2995291
|
» Mapping NCV Circuits to Optimized Clifford+T Circuits
|
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|
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Autor:
|
|
D. Michael Miller, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Kyoto, Japan, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Synthesizing Reversible Circuits for Irreversible Functions
|
|
|
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Autor:
|
|
D. Michael Miller, Robert Wille, Gerhard W. Dueck |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 749-756, Patras, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Reducing Reversible Circuit Cost by Adding Lines
|
|
|
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Autor:
|
|
D. Michael Miller, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
40th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 217-222, Barcelona, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Elementary Quantum Gate Realizations for Multiple-Control Toffoli Gates
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|
|
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Autor:
|
|
D. Michael Miller, Robert Wille, Z. Sasanian |
| Konferenz: |
|
41st International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 288-293, Tuusula, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Modeling Multi-Valued Circuits in SystemC
|
|
|
|
Autor:
|
|
Daniel Große, Görschwin Fey and Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003) |
Referenz:
|
| pp. 281-286, Tokyo, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» Measuring the Quality of a SystemC Testbench by using Code Coverage Technqiues
|
|
|
|
Autor:
|
|
Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 146-151, Barcelona, 2007
Received Best Paper Award
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Guided Lightweight Software Test Qualification for IP Integration using Virtual Prototypes
|
|
|
|
Autor:
|
|
Daniel Große, Hoang M. Le, Muhammad Hassan, Rolf Drechsler |
| Konferenz: |
|
IEEE International Conference on Computer Design (ICCD) |
Referenz:
|
| Phoenix, USA, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Proving Transaction and System-level Properties of Untimed SystemC TLM Designs
|
|
|
|
Autor:
|
|
Daniel Große, Hoang M. Le, Rolf Drechsler |
| Konferenz: |
|
International Conference on
Formal Methods and Models for Codesign (MEMOCODE) |
Referenz:
|
| pp. 113-122, Grenoble, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Simulation-based Equivalence Checking between SystemC Models at different Levels of Abstraction
|
|
|
|
Autor:
|
|
Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 223-228, Lausanne, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Exact Synthesis of Elementary Quantum Gate
Circuits for Reversible Functions with Don’t Cares
|
|
|
|
Autor:
|
|
Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Referenz:
|
| pp. 214-219, Dallas, 2008
Received IEEE Young Researcher Award
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Contradiction Analysis for Constraint-based Random Simulation
|
|
|
|
Autor:
|
|
Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 130-135, Stuttgart, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Contradictory Antecedent Debugging in Bounded Model Checking
|
|
|
|
Autor:
|
|
Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 173-176, Boston, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Acceleration of SAT-based Iterative Property Checking
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Correct Hardware Design and Verification Methods (CHARME) |
Referenz:
|
| pp. 349-353, Saarbrücken, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Checkers for SystemC Designs
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Second ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2004) |
Referenz:
|
| pp. 171-178, San Diego, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» CheckSyC: An Efficient Property Checker for RTL SystemC Designs
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'05) |
Referenz:
|
| pp. 4167-4170, Kobe, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Formal Verification of LTL Formulas for SystemC Designs
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'03) |
Referenz:
|
| pp. V:245-V:248, Bangkok, 2003
|
PDF:
|
| [hier ansehen]
|
» Efficient Automatic Visualization of SystemC Designs
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst |
| Konferenz: |
|
Forum on Specification & Design Languages (FDL'03) |
Referenz:
|
| pp. 646-657, Frankfurt, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Improvements for Constraint Solving in the SystemC Verification Library
|
|
|
|
Autor:
|
|
Daniel Große, Rüdiger Ebendt, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 493-496, Stresa, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Estimating Functional Coverage in Bounded Model Checking
|
|
|
|
Autor:
|
|
Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1176-1181, Nice, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» HW/SW Co-Verification of Embedded Systems using Bounded Model Checking
|
|
|
|
Autor:
|
|
Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 43-48, Philadelphia, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Exact SAT-based Toffoli Network Synthesis
|
|
|
|
Autor:
|
|
Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 96-101, Stresa, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» A Fast Untestability Proof for SAT-based ATPG
|
|
|
|
Autor:
|
|
Daniel Tille, Rolf Drechsler |
| Konferenz: |
|
12th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems |
Referenz:
|
| pp. 38-43, Liberec, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Structural Heuristics for SAT-based ATPG
|
|
|
|
Autor:
|
|
Daniel Tille, Stephan Eggersglüß, Hoang M. Le, Rolf Drechsler |
| Konferenz: |
|
17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2009) |
Referenz:
|
| pp. 77-82, Florianópolis, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Improving CNF Representations in SAT-based ATPG for Industrial Circuits using BDDs
|
|
|
|
Autor:
|
|
Daniel Tille, Stephan Eggersglüß, René Krenz-Bååth, Juergen Schloeffel, Rolf Drechsler |
| Konferenz: |
|
15th IEEE European Test Symposium (ETS) |
Referenz:
|
| pp. 176-181, Prag, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Task-Driven Software Summarization
|
|
|
|
Autor:
|
|
Dave Binkley,
Dawn Lawrie,
Emily Hill,
Janet Burge,
Ian Harris,
Regina Hebig,
Oliver Keszöcze,
Karl Reed,
John Slankas |
| Konferenz: |
|
29th IEEE International Conference on Software Maintenance (ICSM) |
Referenz:
|
| Eindhoven, The Netherlands, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Efficient Minimization of Multi-Valued Decision Diagrams for Incompletely Specified Functions
|
|
|
|
Autor:
|
|
Denis Popel and Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003) |
Referenz:
|
| pp. 241-246, Tokyo, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PS:
|
| [hier ansehen]
|
» Decision Diagrams Optimization Using Copy Properties
|
|
|
|
Autor:
|
|
Dragan Jankovic, Radomir Stankovic and Rolf Drechsler |
| Konferenz: |
|
Euromicro Symposium on Digital System Design (DSD'2002) |
Referenz:
|
| pages 236-243, Dortmund, 2002
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Efficient Calculation of Fixed-Polarity Polynomial Expressions for Multi-Valued Logic Functions
|
|
|
|
Autor:
|
|
Dragan Jankovic, Radomir Stankovic and Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2002) |
Referenz:
|
| pages 76-82, Boston, 2002
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» Reduction of Sizes of Multiple-Valued Decision Diagrams by Copy Properties
|
|
|
|
Autor:
|
|
Dragan Jankovic, Radomir Stankovic, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2004) |
Referenz:
|
| pp. 229-234, Toronto, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
» BDD-based Synthesis for All-optical Mach-Zehnder Interferometer Circuits
|
|
|
|
Autor:
|
|
Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler |
| Konferenz: |
|
International Conference on VLSI Design (VLSI Design) |
Referenz:
|
| Bengaluru, India, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Optimizing DD-based Synthesis of Reversible Circuits using Negative Control Lines
|
|
|
|
Autor:
|
|
Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler |
| Konferenz: |
|
IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 129-134, Warschau, Polen, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Strong 8-bit Sboxes with Efficient Masking in Hardware
|
|
|
|
Autor:
|
|
Erik Boss, Vincent Grosso, Tim Güneysu, Gregor Leander, Amir Moradi, Tobias Schneider |
| Konferenz: |
|
CHES 2016: 171-193 |
Referenz:
|
| http://dx.doi.org/10.1007/978-3-662-53140-2_9
|
» IMITATOR 2.5: A Tool for Analyzing Robustness in Scheduling Problems (Tool Paper)
|
|
|
|
Autor:
|
|
Étienne André, Laurent Fribourg, Ulrich Kühne, Romain Soulat |
| Konferenz: |
|
International Symposium on Formal Methods (FM) |
Referenz:
|
| Paris, France, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Parametric Analysis of Hybrid Systems Using HyMITATOR (Tool Presentation)
|
|
|
|
Autor:
|
|
Étienne André, Ulrich Kühne |
| Konferenz: |
|
International Conference on Integrated Formal Methods (iFM)
|
Referenz:
|
| Pisa, Italy, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Quantitative Timing Analysis of UML Activity Diagrams Using Statistical Model Checking
|
|
|
|
Autor:
|
|
Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Große,
Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 780-785, Dresden, Germany, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Polynomial Datapath Optimization using Constraint Solving and Formal Modelling
|
|
|
|
Autor:
|
|
Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler |
| Konferenz: |
|
IEEE/ACM International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| San Jose, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» A Guiding Coverage Metric for Formal Verification
|
|
|
|
Autor:
|
|
Finn Haedicke, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Dresden, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC
|
|
|
|
Autor:
|
|
Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
International Symposium on System-on-Chip (SoC) |
Referenz:
|
| pp. 1-7, Tampere, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Filmstripping and Unrolling: A Comparison of Verification Approaches for UML and OCL Behavioral Models
|
|
|
|
Autor:
|
|
Frank Hilken, Philipp Niemann, Martin Gogolla, Robert Wille |
| Konferenz: |
|
8th International Conference on Tests & Proofs (TAP) |
Referenz:
|
| pp. 99-116, York, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» From UML/OCL to Base Models: Transformation Concepts for Generic Validation and Verification
|
|
|
|
Autor:
|
|
Frank Hilken, Philipp Niemann, Martin Gogolla, Robert Wille |
| Konferenz: |
|
International Conference on Model Transformation (ICMT) |
Referenz:
|
| pp. 149-165, L’Aquila, Italy, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Towards a Catalog of Structural and Behavioral
Verification Tasks for UML/OCL Models
|
|
|
|
Autor:
|
|
Frank Hilken, Philipp Niemann, Martin Gogolla, Robert Wille |
| Konferenz: |
|
Modellierung |
Referenz:
|
| Karlsruhe, Germany, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» An Integrated SystemC Debugging Environment
|
|
|
|
Autor:
|
|
Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke |
| Konferenz: |
|
Forum on Specification & Design Languages (FDL) |
Referenz:
|
| pp. 140-145, Barcelona, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Non-Intrusive High-level SystemC Debugging
|
|
|
|
Autor:
|
|
Frank Rogin, Erhard Fehlauer, Steffen Ruelke, Sebastian Ohnewald, Thomas Berndt |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Darmstadt, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Automatic Debugging of System-on-a-Chip Designs
|
|
|
|
Autor:
|
|
Frank Rogin, Rolf Drechsler, Steffen Rülke |
| Konferenz: |
|
IEEE International SOC Conference (SOCC) |
Referenz:
|
| Belfast, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automatic Generation of Complex Properties for Hardware Designs
|
|
|
|
Autor:
|
|
Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler Steffen Rülke |
| Konferenz: |
|
Design, Automation, and Test in Europe (DATE) |
Referenz:
|
| Munich, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Unintrusive Aging Analysis based on Offline Learning
|
|
|
|
Autor:
|
|
Frank Sill Torres, Pedro F. R. Leite Junior and Rolf Drechsler |
| Konferenz: |
|
30th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) |
Referenz:
|
| Cambridge, UK, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Ein formaler Ansatz zum Robustheitsnachweis
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
Zuverlässigkeit und Entwurf |
Referenz:
|
| München, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Distributed and Coupled Electrothermal Model of Power Semiconductor Devices
|
|
|
|
Autor:
|
|
G. Belkacem, D. Labrousse, S. Lefebvre, P.-Y. Joubert, U. Kühne, L. Fribourg, R. Soulat, E. Florentin, C. Rey |
| Konferenz: |
|
International Conference on Renewable Energies and Vehicular Technology |
Referenz:
|
| Hammamet, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Designing Reliable Cyber-Physical Systems
|
|
|
|
Autor:
|
|
Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon Ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
|
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Bremen, Germany, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Empirical Results on Parity-based Soft Error Detection with Software-based Retry
|
|
|
|
Autor:
|
|
Gökçe Aydos, Görschwin Fey |
| Konferenz: |
|
IEEE Nordic Circuits and Systems Conference (NORCAS) |
Referenz:
|
| Oslo, Norway, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Exploiting Error Detection Latency for Parity-based Soft Error Detection
|
|
|
|
Autor:
|
|
Gökçe Aydos, Görschwin Fey |
| Konferenz: |
|
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| Košice, Slovakia, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Deterministc Algorithms for ATPG under Leakage Constraints
|
|
|
|
Autor:
|
|
Görschwin Fey |
| Konferenz: |
|
18th Asian Test Symposium (ATS'09) |
Referenz:
|
| Taichung, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Orchestrated Multi-level Information Flow Analysis to Understand SoCs
|
|
|
|
Autor:
|
|
Görschwin Fey |
| Konferenz: |
|
48th Design Automation Conference (DAC)
|
Referenz:
|
| San Diego, USA, 2011
Promotion video on YouTube
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Minimizing the Number of Paths in BDDs
|
|
|
|
Autor:
|
|
Görschwin Fey and Rolf Drechsler |
| Konferenz: |
|
15th Symposium on Integrated Circuits and System Design |
Referenz:
|
| pages 359-364, Porto Alegre, 2002
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» Utilizing BDDs for disjoint SOP minimization
|
|
|
|
Autor:
|
|
Görschwin Fey and Rolf Drechsler |
| Konferenz: |
|
IEEE The 45rd Midwest Symposium on Circuits and Systems (MWSCAS'2002) |
Referenz:
|
| volume II, pages 306-309, Tulsa, 2002
|
PS:
|
| [hier ansehen]
|
» Computing Bounds for Fault Tolerance using Formal Techniques
|
|
|
|
Autor:
|
|
Görschwin Fey, Andre Sülflow, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| pp. 190-195, San Francisco, USA, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Formaler Nachweis der Fehlertoleranz von Schaltkreisen
|
|
|
|
Autor:
|
|
Görschwin Fey, Andre Sülflow, Stefan Frehse, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
GMM/GI/ITG-Fachtagung: Zuverlässigkeit und Entwurf (ZuE 2008) |
Referenz:
|
| pp. 75-82, Ingolstadt, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» On the Construction of Small Fully Testable Circuits with Low Depth
|
|
|
|
Autor:
|
|
Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD)
Architectures, Methods and Tools |
Referenz:
|
| Lübeck, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks
|
|
|
|
Autor:
|
|
Görschwin Fey, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1225-1226, Munich, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» BDD Circuit Optimization for Path Delay Fault Testability
|
|
|
|
Autor:
|
|
Görschwin Fey, Junhao Shi, Rolf Drechsler |
| Konferenz: |
|
Euromicro Symposium on Digital System Design (DSD'2004) |
Referenz:
|
| pp. 168-172, Rennes, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PS:
|
| [hier ansehen]
|
» Efficiency of Multiple-Valued Encoding in SAT-based ATPG
|
|
|
|
Autor:
|
|
Görschwin Fey, Junhao Shi, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multiple-Valued Logic (ISMVL '06) |
Referenz:
|
| Singapore, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» A Basis for Formal Robustness Checking
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler
|
| Konferenz: |
|
International Symposium on Quality of Electronic Design (ISQED) |
Referenz:
|
| San Jose, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Finding Good Counter-Examples to Aid Design Verification
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
First ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2003) |
Referenz:
|
| pp. 51-52, Mont Saint-Michel, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» Improving Simulation-Based Verification by Means of Formal Methods
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
|
Referenz:
|
| pp. 640-643, Yokohama, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Algorithms for Taylor Expansion Diagrams
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler, Maciej Ciesielski |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2004) |
Referenz:
|
| pp. 235-240, Toronto, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PS:
|
| [hier ansehen]
|
» Targeting Leakage Constraints during ATPG
|
|
|
|
Autor:
|
|
Görschwin Fey, Sathoshi Komatsu, Yasuo Furukawa, Masahiro Fujita |
| Konferenz: |
|
Asian Test Symposium (ATS) |
Referenz:
|
| pp. 225-230, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» On the Relation Between Simulation-based and SAT-based Diagnosis
|
|
|
|
Autor:
|
|
Görschwin Fey, Sean Safarpour, Andreas Veneris, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1139-1144, Munich, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Using Games for Benchmarking and Representing the Complete Solution Space Using Symbolic Techniques
|
|
|
|
Autor:
|
|
Görschwin Fey, Sebastian Kinder and Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003) |
Referenz:
|
| pp. 361-366, Tokyo, 2003
|
PS:
|
| [hier ansehen]
|
» Reusing Learned Information in SAT-based ATPG
|
|
|
|
Autor:
|
|
Görschwin Fey, Tim Warode, Rolf Drechsler |
| Konferenz: |
|
20th International Conference on VLSI Design |
Referenz:
|
| Bangalore, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Graph Transformation Units Guided by a SAT Solver
|
|
|
|
Autor:
|
|
Hans-Jörg Kreowski, Susanne Kuske, Robert Wille |
| Konferenz: |
|
International Conference on Graph Transformations (ICGT) |
Referenz:
|
| pp. 27-42, Enschede, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Machine Learning Based Test Pattern Analysis for
Localizing Critical Power Activity Areas
|
|
|
|
Autor:
|
|
Harshad Dhotre, Stephan Eggersglüß, Mehdi Dehbashi, Ulrike Pfannkuchen, Rolf Drechsler |
| Konferenz: |
|
30th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) |
Referenz:
|
| Cambridge, UK, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Identification of Efficient Clustering Techniques for Test Power Activity on the Layout
|
|
|
|
Autor:
|
|
Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
26th IEEE Asian Test Symposium (ATS) |
Referenz:
|
| Taipei, Taiwan, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Exact Diagnosis Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Heinz Riener, Görschwin Fey |
| Konferenz: |
|
International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| Austin, USA, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Model-Based Diagnosis versus Error Explanation
|
|
|
|
Autor:
|
|
Heinz Riener, Görschwin Fey |
| Konferenz: |
|
10th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'12) |
Referenz:
|
| pp. 43-52, Arlington, Virginia, USA, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» metaSMT: A Unified Interface to SMT-LIB2
|
|
|
|
Autor:
|
|
Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler
|
| Konferenz: |
|
Forum on specification & Design Languages (FDL'14) |
Referenz:
|
| pp. 1-6, Munich, Germany, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» CEGAR-based EF Synthesis of Boolean Functions with an Application to Circuit Rectification
|
|
|
|
Autor:
|
|
Heinz Riener, Rüdiger Ehlers, Görschwin Fey |
| Konferenz: |
|
22nd Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| Chiba/Tokyo, Japan, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Improving Fault Tolerance Utilizing Hardware-Software-Co-Synthesis
|
|
|
|
Autor:
|
|
Heinz Riener, Stefan Frehse, Görschwin Fey |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE'13) |
Referenz:
|
| pp. 939-943, Grenoble, France, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» From Requirements and Scenarios to ESL Design in SystemC
|
|
|
|
Autor:
|
|
Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
International Symposium on Electronic System Design (ISED) |
Referenz:
|
| pp. 183-187, Kolkata, WB, India, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Scalable Fault Localization for SystemC TLM Designs
|
|
|
|
Autor:
|
|
Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE'13) |
Referenz:
|
| pp. 35-38, Grenoble, France, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Verifying SystemC using an Intermediate Verification Language and Symbolic Simulation
|
|
|
|
Autor:
|
|
Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| pp. 116:1-6 Austin, Texas, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven Generation
|
|
|
|
Autor:
|
|
Hoang M. Le, Rolf Drechsler
|
| Konferenz: |
|
Design and Verification Conference and Exhibition Europe (DVCon Europe) |
Referenz:
|
| Munich, Germany, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemC
|
|
|
|
Autor:
|
|
Hoang M. Le, Rolf Drechsler
|
| Konferenz: |
|
Design and Verification Conference and Exhibition Europe (DVCon Europe) |
Referenz:
|
| Munich, Germany, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Towards Verifying Determinism of SystemC Designs
|
|
|
|
Autor:
|
|
Hoang M. Le, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE'14) |
Referenz:
|
| pp. 153:1-4, Dresden, Germany, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Towards Formal Verification of Real-World SystemC TLM Peripheral Models - A Case Study
|
|
|
|
Autor:
|
|
Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1160-1163, Dresden, Germany, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Improved Fault Diagnosis for Reversible Circuits
|
|
|
|
Autor:
|
|
Hongyan Zhang, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Asian Test Symposium (ATS) |
Referenz:
|
| New Delhi, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Determining Minimal Testsets for Reversible Circuits Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Hongyan Zhang, Stefan Frehse, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
10th IEEE Africon |
Referenz:
|
| Livingstone, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» IND-CCA Secure Hybrid Encryption from QC-MDPC Niederreiter
|
|
|
|
Autor:
|
|
Ingo von Maurich, Lukas Heberle, Tim Güneysu |
| Konferenz: |
|
Post-Quantum Cryptography (PQCrypto 2016) |
Referenz:
|
| pages 1-17, LNCS Vol. 9606, Fukuoka, Japan
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Standard lattices in hardware
|
|
|
|
Autor:
|
|
James Howe, Ciara Moore, Máire O'Neill, Francesco Regazzoni, Tim Güneysu, K. Beeden |
| Konferenz: |
|
Design Automation Conference (DAC), Austin, USA, 2016, 162:1-162:6 |
Referenz:
|
| http://doi.acm.org/10.1145/2903150.2907756
|
» Analyse dynamischer Abhängigkeitsgraphen zum
Debugging von Hardwaredesigns
|
|
|
|
Autor:
|
|
Jan Malburg
Alexander Finder
Görschwin Fey |
| Konferenz: |
|
7. ITG/GMM/GI-Fachtagung Zuverlässigkeit und Entwurf (ZuE2013)
|
Referenz:
|
| pp. 59-66, Dresden, Germany, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automatically Connecting Hardware Blocks
via Light-Weight Matching Techniques
|
|
|
|
Autor:
|
|
Jan Malburg
Niklas Krafczyk
Görschwin Fey |
| Konferenz: |
|
IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 21-26, Warschau, Polen, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automated Feature Localization for Hardware Designs
using Coverage Metrics
|
|
|
|
Autor:
|
|
Jan Malburg, Alexander Finder, Görschwin Fey |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| pp. 941-946, San Francisco, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Tuning Dynamic Data Flow Analysis to Support Design Understanding
|
|
|
|
Autor:
|
|
Jan Malburg, Alexander Finder, Görschwin Fey |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE'13) |
Referenz:
|
| pp. 1179-1184, Grenoble, France, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Property mining using dynamic dependency
graphs
|
|
|
|
Autor:
|
|
Jan Malburg, Tino Flenker, Goerschwin Fey |
| Konferenz: |
|
22nd Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| Chiba/Tokyo, Japan, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automated Verification For Train Control Systems
|
|
|
|
Autor:
|
|
Jan Peleska, Daniel Große, Anne E. Haxthausen, Rolf Drechsler |
| Konferenz: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2004) |
Referenz:
|
| pp. 252-265, Braunschweig, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State-of-the-Art and Research Challenges
|
|
|
|
Autor:
|
|
Jan-Hendrik Oetjens,
Nico Bannow,
Markus Becker,
Oliver Bringmann,
Andreas Burger,
Moomen Chaari,
Samarjit Chakraborty,
Rolf Drechsler,
Wolfgang Ecker,
Kim Gruettner,
Thomas Kruse,
Christoph Kuznik,
Hoang M. Le,
Andreas Mauderer,
Wolfgang Mueller,
Daniel Mueller-Gritschneder,
Frank Poppen,
Hendrik Post,
Sebastian Reiter,
Wolfgang Rosenstiel,
Simon Roth,
Ulf Schlichtmann,
Andreas von Schwerin,
Bogdan-Andrei Tabacaru,
Alexander Viehl |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| pp. 113:1-6, San Francisco, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
» BioViz: An Interactive Visualization Engine for Digital Microfluidic Biochips
|
|
|
|
Autor:
|
|
Jannis Stoppe, Oliver Keszöcze, Maximilian Luenert, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| Bochum, Germany, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automated Feature Localization for Dynamically Generated SystemC Designs
|
|
|
|
Autor:
|
|
Jannis Stoppe, Robert Wille, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE'15) |
Referenz:
|
| Grenoble, France, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Cone of Influence Analysis at the Electronic System Level Using Machine Learning
|
|
|
|
Autor:
|
|
Jannis Stoppe, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| Santander, Spain, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Data Extraction from SystemC Designs using Debug Symbols and the SystemC API
|
|
|
|
Autor:
|
|
Jannis Stoppe, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| Natal, Brazil, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Validating SystemC Implementations Against Their Formal Specifications
|
|
|
|
Autor:
|
|
Jannis Stoppe, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Symposium on Integrated Circuits and System Design (SBCCI) |
Referenz:
|
| Aracaju, Brazil, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Enhancing Debugging of Multiple Missing Control Errors in Reversible Logic
|
|
|
|
Autor:
|
|
Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler
|
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 465-470, Rhode Island, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» High-Performance and Lightweight Lattice-Based Public-Key Encryption
|
|
|
|
Autor:
|
|
Johannes A. Buchmann, Florian Göpfert, Tim Güneysu, Tobias Oder, Thomas Pöppelmann |
| Konferenz: |
|
IoTPTS@AsiaCCS 2016: 2-9 |
Referenz:
|
| http://doi.acm.org/10.1145/2899007.2899011
|
» Towards a Model-Based Verification Methodology
for Complex Swarm Systems
|
|
|
|
Autor:
|
|
Jonas Gomes Filho, Nils Przigoda, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
International Symposium on Electronic System Design (ISED) |
Referenz:
|
| Patna, Indien, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Clocks vs. Instants Relations: Verifying CCSL Time Constraints in UML/MARTE Models
|
|
|
|
Autor:
|
|
Judith Peters, Nils Przigoda, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) |
Referenz:
|
| Indian Institute of Technology, Kanpur, India, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» A Generic Representation of CCSL Time Constraints for UML/MARTE Models
|
|
|
|
Autor:
|
|
Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| San Francisco, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Generating SystemC Implementations for Clock Constraints specified in UML/MARTE CCSL
|
|
|
|
Autor:
|
|
Judith Peters, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
International Conference on Engineering of Complex Computer Systems (ICECCS) |
Referenz:
|
| pp. 116-125, Tianjin, China, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Determining Relevant Model Elements for the Verification of UML/OCL Specifications
|
|
|
|
Autor:
|
|
Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1189-1192, Grenoble, France, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automatic Refinement Checking for Formal System Models
|
|
|
|
Autor:
|
|
Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Munich, Germany, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
|
|
|
|
Autor:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
Twelfth Asian Test Symposium (ATS03)
|
Referenz:
|
| p.290-293,
Xi'an, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PS:
|
| [hier ansehen]
|
» Bridging Fault Testability of BDD Circuits
|
|
|
|
Autor:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005) |
Referenz:
|
| pp. 188-191 Shanghai, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» PASSAT: Efficient SAT-based Test Pattern Generation
|
|
|
|
Autor:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
| Konferenz: |
|
IEEE Annual Symposium on VLSI (ISVLSI '05) |
Referenz:
|
| pp.212-217, Tampa, Florida, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PS:
|
| [hier ansehen]
|
» Experimental Studies on SAT-based Test Pattern Generation for Industrial Circuits
|
|
|
|
Autor:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke |
| Konferenz: |
|
International Conference on ASIC (ASICON 2005)
|
Referenz:
|
| pp. 967-970, Shanghai, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» SPIHT implemented in a XC4000 device
|
|
|
|
Autor:
|
|
Jörg Ritter, Görschwin Fey and Paul Molitor |
| Konferenz: |
|
IEEE The 45rd Midwest Symposium on Circuits and Systems (MWSCAS'2002) |
Referenz:
|
| volume I, pages 239-242, Tulsa, 2002
|
PDF:
|
| [hier ansehen]
|
» Exploiting Negative Control Lines in the Optimization of Reversible Circuits
|
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|
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Autor:
|
|
Kamalika Datta, Gaurav Rathi, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| pp. 209-220, Victoria, Canada, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» An Evolutionary Approach to Reversible Logic Synthesis using Output Permutation
|
|
|
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Autor:
|
|
Kamalika Datta, Indranil Sen Gupta, Hafizur Rahaman, Rolf Drechsler |
| Konferenz: |
|
IEEE Design and Test Symposium 2012 (IDT) |
Referenz:
|
| Doha, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Trust is good, Control is better: Hardware-based Instruction-Replacement for Reliable Processor-IPs
|
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|
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Autor:
|
|
Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
22nd Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| Chiba/Tokyo, Japan, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Effects of Cell Shapes on the Routability of Digital Microfluidic Biochips
|
|
|
|
Autor:
|
|
Kevin Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Lausanne, Switzerland, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Cost-Efficient Block Verification for a UMTS Up-Link
Chip-Rate Coprocessor
|
|
|
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Autor:
|
|
Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey |
| Konferenz: |
|
IEEE Design, Automation and Test in Europe
|
Referenz:
|
| Vol. I, pp. 162-167, Paris, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Debugging of Reversible Circuits using πDDs
|
|
|
|
Autor:
|
|
Laura Tague, Mathias Soeken, Shin-ichi Minato, Rolf Drechsler |
| Konferenz: |
|
43rd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 316-321, Toyama, Japan, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation
|
|
|
|
Autor:
|
|
Laxmidhar Biswal, Chandan Bandyopadhyay, Anupam Chattopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman |
| Konferenz: |
|
46th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Sapporo, Japan, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library
|
|
|
|
Autor:
|
|
Laxmidhar Biswal, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman |
| Konferenz: |
|
International Conference on VLSI Design (VLSI Design) |
Referenz:
|
| Kolkata, India, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Exploiting Inherent Characteristics of Reversible Circuits for Faster Combinational Equivalence Checking
|
|
|
|
Autor:
|
|
Luca Amaru, Pierre-Emmanuel Gaillardon, Robert Wille, Giovanni De Micheli |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Dresden, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL
|
|
|
|
Autor:
|
|
Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler |
| Konferenz: |
|
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07) |
Referenz:
|
| Oslo, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Secure architectures of future emerging cryptography SAFEcrypto
|
|
|
|
Autor:
|
|
Máire O'Neill, Elizabeth O'Sullivan, Gavin McWilliams, Markku-Juhani Saarinen, Ciara Moore, Ayesha Khalid, James Howe, Rafaël Del Pino, Michel Abdalla, Francesco Regazzoni, Felipe Valencia, Tim Güneysu, Tobias Oder, Adrian Waller, Glyn Jones, Anthony Barnett, Robert Griffin, Andrew Byrne, Bassem Ammar, David Lund |
| Konferenz: |
|
Conf. Computing Frontiers 2016: 315-322 |
Referenz:
|
| http://doi.acm.org/10.1145/2903150.2907756
|
» Analyzing Dependability Measures at the Electronic System Level
|
|
|
|
Autor:
|
|
Marc Michael, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 1-8, Oldenburg, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Localizing Features of ESL Models for Design Understanding
|
|
|
|
Autor:
|
|
Marc Michael, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Vienna, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» The System Verification Methodology for
Advanced TLM Verification
|
|
|
|
Autor:
|
|
Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler, Wolfgang Ecker, Volkan Esen |
| Konferenz: |
|
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) |
Referenz:
|
| pp. 313-322, Tampere, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Fast Heuristics for the Edge Coloring of Large Graphs
|
|
|
|
Autor:
|
|
Mario Hilgemeier, Nicole Drechsler and Rolf Drechsler |
| Konferenz: |
|
Euromicro Symposium on Digital System Design (DSD'2003) |
Referenz:
|
| pp. 230-237, Antalya, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» Minimizing the Number of One-Paths in BDDs by an Evolutionary Algorithm
|
|
|
|
Autor:
|
|
Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler |
| Konferenz: |
|
Congress on Evolutionary Computation 2003 (CEC2003) |
Referenz:
|
| Vol.3, pp.1724-1731, Canberra, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» Fredkin-Enabled Transformation-based Reversible Logic Synthesis
|
|
|
|
Autor:
|
|
Mathias Soeken, Anupam Chattopadhyay |
| Konferenz: |
|
45th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Waterloo, Canada, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Reverse Engineering with Simulation Graphs
|
|
|
|
Autor:
|
|
Mathias Soeken, Baruch Sterin, Rolf Drechsler, Robert K. Brayton |
| Konferenz: |
|
Formal Methods in Computer Aided Design (FMCAD) |
Referenz:
|
| Austin, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automating the Translation of Assertions Using Natural Language Processing Techniques
|
|
|
|
Autor:
|
|
Mathias Soeken, Christopher B. Harris, Nabila Abdessaied, Ian G. Harris and Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Munich, Germany, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» BDD Minimization for Approximate Computing
|
|
|
|
Autor:
|
|
Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| pp. 474-479, Macao, China, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Coverage of OCL Operation Specifications and Invariants
|
|
|
|
Autor:
|
|
Mathias Soeken, Julia Seiter, Rolf Drechsler |
| Konferenz: |
|
9th International Conference on Tests & Proofs (TAP) |
Referenz:
|
| L’Aquila, Italy, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» White Dots do Matter: Rewriting Reversible Logic Circuits
|
|
|
|
Autor:
|
|
Mathias Soeken, Michael Kirkedal Thomsen |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| pp. 196-208, Victoria, Canada, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Quality Assessment for Requirements based on Natural Language Processing
|
|
|
|
Autor:
|
|
Mathias Soeken, Nabila Abdessaied, Arman Allahyari-Abhari, Andi Buzo, Liana Musat, Georg Pelz, Rolf Drechsler |
| Konferenz: |
|
Special Session at the Forum on Specification & Design Languages (FDL'14) |
Referenz:
|
| Munich, Germany, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Enumeration of reversible functions and its application to circuit complexity
|
|
|
|
Autor:
|
|
Mathias Soeken, Nabila Abdessaied, Giovanni De Micheli |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Bologna, Italy, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Optimizing Majority-Inverter Graphs With Functional Hashing
|
|
|
|
Autor:
|
|
Mathias Soeken, Pierre-Emmanuel Gaillardon, Luca Amaru, Giovanni De Micheli |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Dresden, Germany, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
» A Synthesis Flow for Sequential Reversible Circuits
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler |
| Konferenz: |
|
42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 299-304, Victoria, Canada, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Synthesis of Reversible Circuits with Minimal Lines for Large Functions
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| pp. 85-92, Sydney, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Window Optimization of Reversible and Quantum Circuits
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 431-435, Vienna, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Verifying UML/OCL Models Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1341-1344, Dresden, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Eliminating Invariants in UML/OCL Models
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1142-1145, Dresden, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Assisted Behavior Driven Development Using Natural Language Processing
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
50th International Conference on Objects, Models, Components, Patterns (TOOLS) |
Referenz:
|
| pp. 269-287, Prague, Czech Republic, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Encoding OCL Data Types for SAT-based Verification of UML/OCL Models
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
5th International Conference on Tests & Proofs (TAP) |
Referenz:
|
| pp. 152-170, Zurich, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Verifying Dynamic Aspects of UML Models
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1077-1082, Grenoble, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Grammar-based Program Generation Based on Model Finding
|
|
|
|
Autor:
|
|
Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
IEEE Design and Test Symposium 2013 (IDT) |
Referenz:
|
| Marrakesch, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» An MIG-based Compiler for Programmable Logic-in-Memory Architectures
|
|
|
|
Autor:
|
|
Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli
|
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| Austin, USA, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automatic Property Generation for the Formal Verification of Bus Bridges
|
|
|
|
Autor:
|
|
Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 417-422, Cottbus, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits
|
|
|
|
Autor:
|
|
Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler |
| Konferenz: |
|
42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 173-178, Victoria, Canada, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Self-practicing of logic circuits through mobile devices: Lecturers' and students' perceptions
|
|
|
|
Autor:
|
|
Mazyar Seraj, Cornelia Große, Rolf Drechsler |
| Konferenz: |
|
9th annual International Conference on Education and New Learning Technologies (EduLearn17) |
Referenz:
|
| Barcelona, Spain, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Dynamic Template Matching with Mixed-polarity Toffoli Gates
|
|
|
|
Autor:
|
|
Md Mazder Rahman, Mathias Soeken, Gerhard W. Dueck |
| Konferenz: |
|
45th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Waterloo, Canada, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits
|
|
|
|
Autor:
|
|
Md. Mazder Rahman, Gerhard W. Dueck, Anupam Chattopadhyay, Robert Wille |
| Konferenz: |
|
46th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Sapporo, Japan, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automated Design Debugging in a Testbench-Based Verification Environment
|
|
|
|
Autor:
|
|
Mehdi Dehbashi, André Sülflow, Görschwin Fey |
| Konferenz: |
|
14th Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 479-486, Oulu, Finland, 2011
Best Paper Candidate
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automated Formal Verification of X Propagation with Respect to Testability Issues
|
|
|
|
Autor:
|
|
Mehdi Dehbashi, Daniel Tille, Ulrike Pfannkuchen, Stephan Eggersglüß |
| Konferenz: |
|
IEEE International Design and Test Symposium 2014 (IDT) |
Referenz:
|
| pp. 106-111, Algiers, Algerien, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Application of Timing Variation Modeling to Speedpath Diagnosis
|
|
|
|
Autor:
|
|
Mehdi Dehbashi, Görschwin Fey |
| Konferenz: |
|
4th International Conference on System, Software, SoC and Silicon Debug (S4D) |
Referenz:
|
| pp. 34-37, Vienna, Austria, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automated Debugging from Pre-Silicon to Post-Silicon
|
|
|
|
Autor:
|
|
Mehdi Dehbashi, Görschwin Fey |
| Konferenz: |
|
15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 324-329, Tallinn, Estonia, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automated Post-Silicon Debugging of Design Bugs
|
|
|
|
Autor:
|
|
Mehdi Dehbashi, Görschwin Fey |
| Konferenz: |
|
3rd International Conference on System, Software, SoC and Silicon Debug (S4D) |
Referenz:
|
| pp. 67-71, Munich, Germany, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automated Post-Silicon Debugging of Failing
Speedpaths
|
|
|
|
Autor:
|
|
Mehdi Dehbashi, Görschwin Fey |
| Konferenz: |
|
21st IEEE Asian Test Symposium (ATS) |
Referenz:
|
| pp. 13-18, Niigata, Japan, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Debug Automation for Synchronization Bugs at RTL
|
|
|
|
Autor:
|
|
Mehdi Dehbashi, Görschwin Fey |
| Konferenz: |
|
27th International Conference on VLSI Design |
Referenz:
|
| pp. 44-49, Mumbai, India, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Efficient Automated Speedpath Debugging
|
|
|
|
Autor:
|
|
Mehdi Dehbashi, Görschwin Fey |
| Konferenz: |
|
16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 48-53, Karlovy Vary, Czech Republic, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» SAT-Based Speedpath Debugging Using Waveforms
|
|
|
|
Autor:
|
|
Mehdi Dehbashi, Görschwin Fey |
| Konferenz: |
|
19th IEEE European Test Symposium (ETS) |
Referenz:
|
| Paderborn, Germany, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Transaction-Based Online Debug for NoC-Based
Multiprocessor SoCs
|
|
|
|
Autor:
|
|
Mehdi Dehbashi, Görschwin Fey |
| Konferenz: |
|
22nd Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP) |
Referenz:
|
| Turin, Italy, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Functional Analysis of Circuits Under Timing
Variations
|
|
|
|
Autor:
|
|
Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
|
| Konferenz: |
|
17th IEEE European Test Symposium (ETS) |
Referenz:
|
| pp. 177, Annecy, France, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» On Modeling and Evaluation of Logic Circuits
Under Timing Variations
|
|
|
|
Autor:
|
|
Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan |
| Konferenz: |
|
15th Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 431-436, Izmir, Turkey, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Fault Effects in FlexRay-Based Networks with Hybrid Topology
|
|
|
|
Autor:
|
|
Mehdi Dehbashi, Vahid Lari, Seyed Ghassem Miremadi, Mohammad Shokrollah-Shirazi |
| Konferenz: |
|
3rd IEEE International Conference on Availability, Reliability and Security (ARES) |
Referenz:
|
| pp. 491-496, Barcelona, Spain, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» AIBA: an Automated Intra-Cycle Behavioral Analysis
for SystemC-based Design Exploration
|
|
|
|
Autor:
|
|
Mehran Goli, Jannis Stoppe, Rolf Drechsler |
| Konferenz: |
|
IEEE International Conference on Computer Design (ICCD) |
Referenz:
|
| Phoenix, USA, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automatic Equivalence Checking for SystemC-TLM 2.0 Models
Against their Formal Specifications
|
|
|
|
Autor:
|
|
Mehran Goli, Jannis Stoppe, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Lausanne, Switzerland, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Behaviour Driven Development for Tests and Verification
|
|
|
|
Autor:
|
|
Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
8th International Conference on Tests & Proofs (TAP) |
Referenz:
|
| pp. 61-77, York, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Ricercar: A Language for Describing and Rewriting Reversible Circuits with Ancillae and its Permutation Semantics
|
|
|
|
Autor:
|
|
Michael Kirkedal Thomsen, Mathias Soeken, Robin Kaarsgaard |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Grenoble, France, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Augmented Sifting for Multiple-Valued Decision Diagrams
|
|
|
|
Autor:
|
|
Michael Miller and Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003) |
Referenz:
|
| pp. 375-382, Tokyo, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» On the Construction of Multi-Valued Decision Diagrams
|
|
|
|
Autor:
|
|
Michael Miller and Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2002) |
Referenz:
|
| pages 245-253, Boston, 2002
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Switching Activity Estimation for Finite State Machines for Low Power Synthesis (Poster)
|
|
|
|
Autor:
|
|
Mikael Kerttu, Per Lindgren, Mitch Thornton and Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'02) |
Referenz:
|
| Scottsdale, 2002
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» Multi-Output Timed Shannon Circuits
|
|
|
|
Autor:
|
|
Mitch Thorton, Rolf Drechsler and Michael Miller |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002) |
Referenz:
|
| pages 47-52, Pittsburgh, 2002
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» Debugging Sequential Circuits Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Moayad Ali, Andreas Veneris, Sean Safarpour, Magdy Abadir, Rolf Drechsler, Alexander Smith |
| Konferenz: |
|
IEEE International Conference on Computer Aided Design (ICCAD'04) |
Referenz:
|
| pp. 204-209, San Jose, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Post-Verification Debugging of Hierarchical Designs
|
|
|
|
Autor:
|
|
Moayad Ali, Sean Safarpour, Andreas Veneris, Magdy Abadir, Rolf Drechsler |
| Konferenz: |
|
IEEE International Conference on Computer Aided Design (ICCAD'05) |
Referenz:
|
| pp. 871-876, San Jose, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» TLM Protocol Compliance Checking at the Electronic System Level
|
|
|
|
Autor:
|
|
Mohamed Bawadekji, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 435-440, Cottbus, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Early SoC Security Validation by VP-based Static Information Flow Analysis
|
|
|
|
Autor:
|
|
Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
|
| Konferenz: |
|
International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| Irvine, USA, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Data Flow Testing for Virtual Prototypes
|
|
|
|
Autor:
|
|
Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Lausanne, Switzerland, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Adaptive Branch and Bound using SAT to Estimate False Crosstalk
|
|
|
|
Autor:
|
|
Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler
|
| Konferenz: |
|
International Symposium on Quality of Electronic Design (ISQED) |
Referenz:
|
| San Jose, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Timing Arc Based Logic Analysis for False Noise Reduction
|
|
|
|
Autor:
|
|
Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler |
| Konferenz: |
|
IEEE/ACM International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| pp. 225-230, San Jose, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Reversible Circuit Rewriting with Simulated Annealing
|
|
|
|
Autor:
|
|
Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, and Rolf Drechsler |
| Konferenz: |
|
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) |
Referenz:
|
| Daejeon, Korea, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Exact Template Matching Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
43rd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 328-333, Toyama, Japan, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Quantum Circuit Optimization by Hadamard Gate Reduction
|
|
|
|
Autor:
|
|
Nabila Abdessaied, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Kyoto, Japan, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Technology mapping for quantum circuits using Boolean functional decomposition
|
|
|
|
Autor:
|
|
Nabila Abdessaied, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Grenoble, France, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Technology mapping of reversible circuits to Clifford+T quantum circuits
|
|
|
|
Autor:
|
|
Nabila Abdessaied, Matthew Amy, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
46rd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Sapporo, Japan, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Reducing the Depth of Quantum Circuits Using Additional Lines
|
|
|
|
Autor:
|
|
Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| pp. 221-233, Victoria, Canada, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Self-Adaptive Evolutionary Many-Objective Optimization based on Relation Epsilon-Preferred
|
|
|
|
Autor:
|
|
Nicole Drechsler |
| Konferenz: |
|
International Conference on Soft Computing MENDEL |
Referenz:
|
| Brno, Czech Republic, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Incorporating User Preferences in Many-Objective Optimization using Relation Epsilon-Preferred
|
|
|
|
Autor:
|
|
Nicole Drechsler, André Sülflow, Rolf Drechsler |
| Konferenz: |
|
International Conference on Evolutionary Computation Theory and Applications (ECTA) |
Referenz:
|
| Vilamoura, Portugal, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Exploration of Sequential Depth by Evolutionary Algorithms
|
|
|
|
Autor:
|
|
Nicole Drechsler, Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (VLSI'03) |
Referenz:
|
| pp. 81-85, Darmstadt, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Conservatively Analyzing Transient Faults
|
|
|
|
Autor:
|
|
Niels Thole,
Görschwin Fey,
Alberto Garcia-Ortiz |
| Konferenz: |
|
IEEE Computer Society
Annual Symposium
on VLSI (ISVLSI) |
Referenz:
|
| Montpelier, France, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Equivalence Checking on ESL Utilizing A Priori Knowledge
|
|
|
|
Autor:
|
|
Niels Thole, Heinz Riener, Görschwin Fey
|
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Bremen, Germany, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Equivalence Checking on System Level using A Priori Knowledge
|
|
|
|
Autor:
|
|
Niels Thole, Heinz Riener, Görschwin Fey |
| Konferenz: |
|
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15) |
Referenz:
|
| Belgrade, Serbia, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» A Hybrid Algorithm to Conservatively Check the
Robustness of Circuits
|
|
|
|
Autor:
|
|
Niels Thole, Lorena Anghel, Görschwin Fey |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| Pittsburgh, USA, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
» A Hybrid Algorithm to Conservatively Check the Robustness of Circuits
|
|
|
|
Autor:
|
|
Niels Thole, Lorena Anghel, Görschwin Fey |
| Konferenz: |
|
IEEE European Test Symposium (ETS) |
Referenz:
|
| Amsterdam, Niederlande, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» WCET Overapproximation for Software in the Context of Cyber-Physical Systems
|
|
|
|
Autor:
|
|
Niklas Krafczyk, Heinz Riener, Görschwin Fey |
| Konferenz: |
|
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) |
Referenz:
|
| Tallinn, Estonia, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Checking Concurrent Behavior in UML/OCL Models
|
|
|
|
Autor:
|
|
Nils Przigoda, Christoph Hilken, Robert Wille, Jan Peleska, Rolf Drechsler |
| Konferenz: |
|
ACM/IEEE 18th International Conference on Model Driven Engineering Languages and Systems (MoDELS) |
Referenz:
|
| Ottawa, Kanada, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Fault Detection in Parity Preserving Reversible Circuits
|
|
|
|
Autor:
|
|
Nils Przigoda, Gerhard Dueck, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
46th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Sapporo, Japan, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Verification-driven Design Across Abstraction Levels - A Case Study
|
|
|
|
Autor:
|
|
Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| Funchal, Madeira, Portugal, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Frame Conditions in Symbolic Representations of UML/OCL Models
|
|
|
|
Autor:
|
|
Nils Przigoda, Jonas Gomes Filho, Philipp Niemann, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) |
Referenz:
|
| Indian Institute of Technology, Kanpur, India, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» More than true or false: Native Support of Irregular Values in the Automatic Validation & Verification of UML/OCL Models
|
|
|
|
Autor:
|
|
Nils Przigoda, Philipp Niemann, Judith Peters, Frank Hilken, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) |
Referenz:
|
| Vienna, Austria, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Contradiction Analysis for Inconsistent Formal Models
|
|
|
|
Autor:
|
|
Nils Przigoda, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15) |
Referenz:
|
| Belgrade, Serbia, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Ground Setting Properties for an Efficient Translation of OCL in SMT-based Model Finding
|
|
|
|
Autor:
|
|
Nils Przigoda, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
ACM/IEEE 19th International Conference on Model Driven Engineering Languages and Systems (MoDELS) |
Referenz:
|
| Saint Malo, Brittany, France, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Leveraging the Analysis for Invariant Independence in Formal System Models
|
|
|
|
Autor:
|
|
Nils Przigoda, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| Funchal, Madeira, Portugal, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» (Semi-)Automatic Translation of Legal Regulations to Formal Representations: Expanding the Horizon of EDA Applications
|
|
|
|
Autor:
|
|
Oliver Keszöcze, Betina Keiner, Matthias Richter, Gottfried Antpöhler, Robert Wille
|
| Konferenz: |
|
Special Session at the Forum on specification & Design Languages (FDL'14) |
Referenz:
|
| Munich, Germany, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» A General and Exact Routing Methodology for Digital Microfluidic
Biochips
|
|
|
|
Autor:
|
|
Oliver Keszöcze, Robert Wille, Krishnendu Chakrabarty Rolf Drechsler
|
| Konferenz: |
|
International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| Austin, USA, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Exact Routing for Digital Microfluidic Biochips with Temporary Blockages
|
|
|
|
Autor:
|
|
Oliver Keszöcze, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| San Jose, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Exact One-pass Synthesis of Digital Microfluidic Biochips
|
|
|
|
Autor:
|
|
Oliver Keszöcze, Robert Wille, Tsung-Yi Ho, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| San Francisco, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Exact Routing for Micro-Electrode-Dot-Array Digital Microfluidic Biochips
|
|
|
|
Autor:
|
|
Oliver Keszöcze, Zipeng Li, Andreas Grimmer, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler |
| Konferenz: |
|
22nd Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| Chiba/Tokyo, Japan, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Hiding Higher-Order Side-Channel Leakage - Randomizing Cryptographic Implementations in Reconfigurable Hardware
|
|
|
|
Autor:
|
|
Pascal Sasdrich, Amir Moradi, Tim Güneysu |
| Konferenz: |
|
RSA Conference Cryptographers’ Track (CT-RSA) |
Referenz:
|
| San Francisco, US, 2017.
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» White-Box Cryptography in the Gray Box - A Hardware Implementation and its Side Channels
|
|
|
|
Autor:
|
|
Pascal Sasdrich, Amir Moradi, Tim Güneysu |
| Konferenz: |
|
FSE 2016: 185-203 |
Referenz:
|
| http://dx.doi.org/10.1007/978-3-662-52993-5_10
|
» A grain in the silicon: SCA-protected AES in less than 30 slices
|
|
|
|
Autor:
|
|
Pascal Sasdrich, Tim Güneysu |
| Konferenz: |
|
IEEE International Conference on
Application-specific Systems, Architectures and Processors (ASAP) 2016: 25-32 |
Referenz:
|
| http://dx.doi.org/10.1109/ASAP.2016.7760769
|
» Formal Verification on Register Transfer Level - Utilizing High-Level Information for Hardware Verification
|
|
|
|
Autor:
|
|
Peer Johannsen and Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (VLSI'01) |
Referenz:
|
| pages 127-132, Montpellier, 2001
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» Efficient Construction of QMDDs for Irreversible, Reversible and Quantum Functions
|
|
|
|
Autor:
|
|
Philipp Niemann, Alwin Zulehner, Robert Wille, Rolf Drechsler
|
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| pp. 214-231, Kolkata, India, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Assisted Generation of Frame Conditions for Formal Models
|
|
|
|
Autor:
|
|
Philipp Niemann, Frank Hilken, Martin Gogolla, Robert Wille
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE'15) |
Referenz:
|
| pp. 309-312, Grenoble, France, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Extracting Frame Conditions from Operation Contracts
|
|
|
|
Autor:
|
|
Philipp Niemann, Frank Hilken, Martin Gogolla, Robert Wille |
| Konferenz: |
|
ACM/IEEE 18th International Conference on Model Driven Engineering Languages and Systems (MoDELS) |
Referenz:
|
| pp. 266-275, Ottawa, Canada, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Logic Synthesis for Quantum State Generation
|
|
|
|
Autor:
|
|
Philipp Niemann, Rhitam Datta, Robert Wille |
| Konferenz: |
|
46th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Sapporo, Japan, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Efficient Synthesis of Quantum Circuits Implementing Clifford Group Operations
|
|
|
|
Autor:
|
|
Philipp Niemann, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| pp. 483-488, Singapore, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Equivalence Checking in Multi-level Quantum Systems
|
|
|
|
Autor:
|
|
Philipp Niemann, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| pp. 201-215, Kyoto, Japan, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» On the “Q” in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-structure
|
|
|
|
Autor:
|
|
Philipp Niemann, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| pp. 125-140, Victoria, Canada, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Synthesis of Quantum Circuits for Dedicated Physical Machine Descriptions
|
|
|
|
Autor:
|
|
Philipp Niemann, Saikat Basu, Amlan Chakrabarti, Niraj K. Jha, Robert Wille |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| pp. 248-264, Grenoble, France, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» RTL-Datapath Verification using Integer Linear Programming
|
|
|
|
Autor:
|
|
Raik Brinkmann and Rolf Drechsler |
| Konferenz: |
|
IEEE VLSI Design'02 & Asia and South Pacific Design Automation Conference |
Referenz:
|
| pages 741-746, Bangalore, 2002
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» Semi-Formal Cycle-Accurate Temporal Execution Traces Reconstruction
|
|
|
|
Autor:
|
|
Rehab Massoud, Jannis Stoppe, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
15th International Conference on Formal Modelling and Analysis of Timed Systems (FORMATS) |
Referenz:
|
| Berlin, Germany, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Reliability Analysis Reloaded: How Will We Survive?
|
|
|
|
Autor:
|
|
Robert Aitken, Görschwin Fey, Zbigniew T. Kalbarczyk, Frank Reichenbach, Matteo Sonza Reorda |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE'13) |
Referenz:
|
| Grenoble, France, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» An Introduction to Reversible Circuit Design
|
|
|
|
Autor:
|
|
Robert Wille |
| Konferenz: |
|
Saudi International Electronics, Communications and Photonics Conference (SIECPC) |
Referenz:
|
| Riyadh, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Optimal SWAP Gate Insertion for Nearest Neighbor Quantum Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Aaron Lye, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| pp. 489-494, Singapore, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» VisSAT: Visualization of SAT Solver Internals for Computer Aided Hardware Verification
|
|
|
|
Autor:
|
|
Robert Wille, André Sülflow, Rolf Drechsler |
| Konferenz: |
|
International Conference on Modeling, Simulation and Visualization Methods (MSV) |
Referenz:
|
| pp. 36-39, Las Vegas, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Fast Exact Toffoli Network Synthesis of Reversible Logic
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große |
| Konferenz: |
|
IEEE International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| pp. 60-64, San Jose, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Equivalence Checking of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler |
| Konferenz: |
|
39th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 324-330, Naha, Okinawa, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» SMT-based Stimuli Generation in the SystemC Verification Library
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 1-6, Sophia Antipolis, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Reversible Logic Synthesis with Output Permutation
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
22nd International Conference on VLSI Design |
Referenz:
|
| pp. 189-194, New Delhi, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» RevLib: An Online Resource for
Reversible Functions and Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Referenz:
|
| pp. 220-225, Dallas, 2008
RevLib is available at www.revlib.org
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| pp. 411-416, Montpellier, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Debugging of Toffoli Networks
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1284-1289, Nice, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» SWORD: A SAT like Prover Using Word Level Information
|
|
|
|
Autor:
|
|
Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC) |
Referenz:
|
| pp. 88-93, Atlanta, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking
|
|
|
|
Autor:
|
|
Robert Wille, Görschwin Fey, Marc Messing, Gerhard
Angst, Lothar Linhard, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 542-549, Parma, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Quantified Synthesis of Reversible Logic
|
|
|
|
Autor:
|
|
Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große |
| Konferenz: |
|
Design, Automation, and Test in Europe (DATE) |
Referenz:
|
| pp. 1015-1020, Munich, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» ATPG for Reversible Circuits Using Simulation,
Boolean Satisfiability, and Pseudo Boolean
Optimization
|
|
|
|
Autor:
|
|
Robert Wille, Hongyan Zhang, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| pp. 120-125, Chennai, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Hongyan Zhang, Rolf Drechsler |
| Konferenz: |
|
43rd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 29-34, Toyama, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» RevVis: Visualization of Structures and Properties in Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Jannis Stoppe, Eleonora Schönborn, Kamalika Datta, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Kyoto, Japan, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Towards a Generic Verification Methodology for System Models
|
|
|
|
Autor:
|
|
Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1193-1196, Grenoble, France, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Improving the Mapping of Reversible Circuits to Quantum Circuits Using Multiple Target Lines
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| pp. 145-150. Yokohama, Japan, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Designing a RISC CPU in Reversible Logic
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler |
| Konferenz: |
|
41st International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 170-175, Tuusula, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Circuit Line Minimization in the HDL-based Synthesis of Reversible Logic
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| pp. 213-218, Amherst, USA, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler |
| Konferenz: |
|
42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 69-74, Victoria, Canada, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Debugging of Inconsistent UML/OCL Models
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1078-1083, Dresden, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Reducing the Number of Lines in Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| pp. 647-652, Anaheim, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» A Compact and Efficient SAT Encoding for Quantum Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Nils Przigoda, Rolf Drechsler |
| Konferenz: |
|
IEEE Africon |
Referenz:
|
| Mauritius, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Reverse BDD-based Synthesis for Splitter-free Optical Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Oliver Keszöcze, Clemens Hopfmuller, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| Chiba/Tokyo, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Generating and Checking Control Logic in the HDL-based Design of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler |
| Konferenz: |
|
International Symposium on Electronic System Design (ISED) |
Referenz:
|
| Patna, Indien, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs
|
|
|
|
Autor:
|
|
Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Bologna, Italy, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Look-ahead Schemes for Nearest Neighbor Optimization of 1D and 2D Quantum Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Oliver Keszöcze, Marcel Walter, Patrick Rohrs, Anupam Chattopadhyay, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| Macao, China, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Determining the Minimal Number of Lines for Large Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Oliver Keszöcze, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1204—1207, Grenoble, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Synthesis of Approximate Coders
for On-chip Interconnects Using Reversible Logic
|
|
|
|
Autor:
|
|
Robert Wille, Oliver Keszöcze, Stefan Hillmich, Marcel Walter, Alberto Garcia-Ortiz |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Dresden, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Formal Methods for Emerging Technologies
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler
|
| Konferenz: |
|
International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| Austin, USA, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
» BDD-based Synthesis of Reversible Logic for Large Functions
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| pp. 270-275, San Francisco, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» The SyReC Hardware Description Language:
Enabling Scalable Synthesis of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler |
| Konferenz: |
|
International Midwest Symposium on Circuits and Systems (MWSCAS) |
Referenz:
|
| Columbus, USA, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler, Christof Oswald, Alberto Garcia-Ortiz |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Dresden, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» SyReC: A Programming Language for Synthesis of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Sebastian Offermann, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 184-189, Southampton, 2010
Received Best Paper Award
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Exploiting Reversibility in the Complete Simulation of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Simon Stelter, Rolf Drechsler |
| Konferenz: |
|
IEEE Africon |
Referenz:
|
| Mauritius, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» FoREnSiC - An Automatic Debugging Environment for C Programs
|
|
|
|
Autor:
|
|
Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow
|
| Konferenz: |
|
Haifa Verification Conference (HVC) |
Referenz:
|
| Haifa, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Towards Dialog Systems for Assisted Natural Language Processing in the Design of Embedded Systems
|
|
|
|
Autor:
|
|
Rolf Drechsler, Mathias Soeken, Robert Wille |
| Konferenz: |
|
IEEE Design and Test Symposium 2012 (IDT) |
Referenz:
|
| Doha, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Evaluation of Static Variable Ordering Heuristics for MDD Construction
|
|
|
|
Autor:
|
|
Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2002) |
Referenz:
|
| pages 254-260, Boston, 2002
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» JADE: Implementation and Visualization of a BDD Package in JAVA
|
|
|
|
Autor:
|
|
Rolf Drechsler |
| Konferenz: |
|
IEEE Design, Automation and Test in Europe (DATE'02) - User Forum |
Referenz:
|
| page 259, Paris, 2002
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Synthesizing Checkers for On-line Verification of System-on-Chip Designs
|
|
|
|
Autor:
|
|
Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'03) |
Referenz:
|
| pp. IV:748-IV:751, Bangkok, 2003
|
PDF:
|
| [hier ansehen]
|
» Reachability Analysis for Formal Verification of SystemC
|
|
|
|
Autor:
|
|
Rolf Drechsler and Daniel Große |
| Konferenz: |
|
Euromicro Symposium on Digital System Design (DSD'2002) |
Referenz:
|
| pages 337-340, Dortmund, 2002
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Fast and Efficient Equivalence Checking based on NAND-BDDs
|
|
|
|
Autor:
|
|
Rolf Drechsler and Mitch Thornton |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (VLSI'01) |
Referenz:
|
| pages 401-405, Montpellier, 2001
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» Minimization of Transitions by Complementation and Resequencing using Evolutionary Algorithms
|
|
|
|
Autor:
|
|
Rolf Drechsler and Nicole Drechsler |
| Konferenz: |
|
21st IASTED International Multi-Conference Applied Informatics (AI 2003) |
Referenz:
|
| Innsbruck, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PS:
|
| [hier ansehen]
|
» Hardware Project Management - What we Can Learn from the Software Development Process for Hardware Design?
|
|
|
|
Autor:
|
|
Rolf Drechsler, Andreas Breiter |
| Konferenz: |
|
2nd International Conference on Software and Data Technologies |
Referenz:
|
| Barcelona, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Hardware Project Management – What we Can Learn from the Software Development Process for Hardware Design?
|
|
|
|
Autor:
|
|
Rolf Drechsler, Andreas Breiter |
| Konferenz: |
|
4th Conference of Informatics and Information Technologies |
Referenz:
|
| Bitola, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Future SoC Verification Methodology: UVM
Evolution or Revolution?
|
|
|
|
Autor:
|
|
Rolf Drechsler, Christophe Chevallaz, Franco Fummi, Alan Hu, Ronny Morad, Frank Schirrmeister, Alex Goryachev |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE'14) |
Referenz:
|
| Dresden, Germany, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Synchronized Debugging across Different Abstraction Levels in System Design
|
|
|
|
Autor:
|
|
Rolf Drechsler, Daniel Große, Hoang M. Le, André Sülflow |
| Konferenz: |
|
embedded world Conference 2013 |
Referenz:
|
| Nürnberg, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» An Integrated Approach for Combining BDD and SAT Provers
|
|
|
|
Autor:
|
|
Rolf Drechsler, Görschwin Fey, Sebastian Kinder |
| Konferenz: |
|
International Conference on VLSI Design |
Referenz:
|
| Hyderabad, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Self-Verification as the Key Technology for Next Generation Electronic Systems
|
|
|
|
Autor:
|
|
Rolf Drechsler, Hoang M. Le, Mathias Soeken |
| Konferenz: |
|
Symposium on Integrated Circuits and System Design (SBCCI) |
Referenz:
|
| Aracaju, Brazil, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Hardware/Software Co-Visualization on the Electronic System Level using SystemC
|
|
|
|
Autor:
|
|
Rolf Drechsler, Jannis Stoppe |
| Konferenz: |
|
International Conference
on VLSI Design |
Referenz:
|
| Kolkata, India, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits
|
|
|
|
Autor:
|
|
Rolf Drechsler, Junhao Shi and Görschwin Fey |
| Konferenz: |
|
IEEE Great Lakes Symposium on VLSI (GLSV'03) |
Referenz:
|
| p. 80-83, Washington, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» Envisioning Self-Verification of Electronic Systems
|
|
|
|
Autor:
|
|
Rolf Drechsler, Martin Fränzle, Robert Wille |
| Konferenz: |
|
Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) |
Referenz:
|
| Bremen, Germany, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Hardware-Software Co-Visualization: Developing Systems in the Holodeck
|
|
|
|
Autor:
|
|
Rolf Drechsler, Mathias Soeken |
| Konferenz: |
|
16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 1-4, Karlovy Vary, Czech Republic, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Formal Specification Level: Towards Verification-driven Design Based on Natural Language Processing
|
|
|
|
Autor:
|
|
Rolf Drechsler, Mathias Soeken, Robert Wille |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 53-58, Vienna, Austria, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automated and Quality-driven Requirements Engineering
|
|
|
|
Autor:
|
|
Rolf Drechsler, Mathias Soeken, Robert Wille, |
| Konferenz: |
|
International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| San Jose, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Completeness-Driven Development
|
|
|
|
Autor:
|
|
Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille |
| Konferenz: |
|
International Conference on Graph Transformation |
Referenz:
|
| pp. 38-50, Bremen, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits
|
|
|
|
Autor:
|
|
Rolf Drechsler, Robert Wille |
| Konferenz: |
|
41st International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 78-85, Tuusula, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology
|
|
|
|
Autor:
|
|
Rolf Drechsler, Robert Wille |
| Konferenz: |
|
International Symposium on VLSI Design and Test (VDAT) |
Referenz:
|
| Shibpur, India, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Reversible Computation: An Alternative Computation Paradigm for Low Power Applications
|
|
|
|
Autor:
|
|
Rolf Drechsler, Robert Wille |
| Konferenz: |
|
International Green and Sustainable Computing Conference (IGSC) |
Referenz:
|
| Las Vegas, USA, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Synthesis of Reversible Circuits Using Decision Diagrams
|
|
|
|
Autor:
|
|
Rolf Drechsler, Robert Wille |
| Konferenz: |
|
International Symposium on Electronic System Design (ISED) |
Referenz:
|
| pp. 1-5, Kolkata, WB, India, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Exploring Superior Structural Materials Using Multi-Objective Optimization and Formal Techniques
|
|
|
|
Autor:
|
|
Rolf Drechsler, Stephan Eggersglüß, Nils Ellendt, Sebastian Huhn, Lutz Mädler |
| Konferenz: |
|
6th IEEE International Symposium on Embedded Computing & System Design (ISED) |
Referenz:
|
| Indian Institute of Technology, Patna, India, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Safe IP Integration Using Container Modules
|
|
|
|
Autor:
|
|
Rolf Drechsler, Ulrich Kühne
|
| Konferenz: |
|
International Symposium on Electronic System Design (ISED) |
Referenz:
|
| Mangalore, India, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Recursive Bi-Partitioning of Netlists for Large Number of Partitions
|
|
|
|
Autor:
|
|
Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard and Gerhard Angst |
| Konferenz: |
|
Euromicro Symposium on Digital System Design (DSD'2002) |
Referenz:
|
| pages 38-44, Dortmund, 2002
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Reducing the Number of Variable Movements in Exact BDD Minimization
|
|
|
|
Autor:
|
|
Rüdiger Ebendt |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'03) |
Referenz:
|
| pp. V:605-V:608, Bangkok, 2003
|
PDF:
|
| [hier ansehen]
|
» Lower Bounds for Dynamic BDD Reordering
|
|
|
|
Autor:
|
|
Rüdiger Ebendt and Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005) |
Referenz:
|
| pp. 579-582, Shanghai, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Quasi-Exact BDD Minimization using Relaxed Best-First Search
|
|
|
|
Autor:
|
|
Rüdiger Ebendt and Rolf Drechsler |
| Konferenz: |
|
IEEE Annual Symposium on VLSI (ISVLSI '05) |
Referenz:
|
| pp. 59-64, Tampa, Florida, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» A Framework for Quasi-Exact Optimization using Relaxed Best-First Search
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Rolf Drechsler |
| Konferenz: |
|
29th Annual German Conference on Artificial Intelligence (KI'06) |
Referenz:
|
| Bremen, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Approximate BDD Minimization by Weighted A*
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'09) |
Referenz:
|
| Taipei, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Exact BDD Minimization for Path-Related Objective Functions
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC 2005) |
Referenz:
|
| pp. 525-530, Perth, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PS:
|
| [hier ansehen]
|
» On the Sensitivity of BDDs with Respect to Path-Related Objective Functions
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'06) |
Referenz:
|
| Kos, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Combination of Lower Bounds in Exact BDD Minimization
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Wolfgang Günther and Rolf Drechsler |
| Konferenz: |
|
IEEE Design, Automation and Test in Europe (DATE'03) |
Referenz:
|
| pp. 758-763, Munich, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Combining Ordered Best-First Search with Branch and Bound for Exact BDD Minimization
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
|
Referenz:
|
| pp. 876-879, Yokohama, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Minimization of the Expected Path Length in BDDs Based on Local Changes
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
|
Referenz:
|
| pp. 866-871, Yokohama, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» An Adaptive Prioritized ε-Preferred Evolutionary Algorithm for Approximate BDD Optimization
|
|
|
|
Autor:
|
|
Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Genetic and Evolutionary Computation Conference (GECCO) |
Referenz:
|
| Berlin, Germany, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm
|
|
|
|
Autor:
|
|
Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Genetic and Evolutionary Computation Conference (GECCO) |
Referenz:
|
| Denver, USA, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Endurance Management for Resistive Logic-In-Memory Computing Architectures
|
|
|
|
Autor:
|
|
Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Lausanne, Switzerland, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Fast Logic Synthesis for RRAM-based In-Memory Computing using Majority-Inverter Graphs
|
|
|
|
Autor:
|
|
Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Dresden, Germany, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Multi-Objective BDD Optimization for RRAM based Circuit Design
|
|
|
|
Autor:
|
|
Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'16) |
Referenz:
|
| Košice, Slovakia, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Multi-Objective BDD Optimization with Evolutionary Algorithms
|
|
|
|
Autor:
|
|
Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Genetic and Evolutionary Computation Conference (GECCO) |
Referenz:
|
| Madrid, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Error Bounded Exact BDD Minimization in Approximate Computing
|
|
|
|
Autor:
|
|
Saman Froehlich, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
47th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Novi Sad, Serbia, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Integrating Observability Don't Cares in All-Solution SAT Solvers
|
|
|
|
Autor:
|
|
Sean Safarpour, Andreas Veneris, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'06) |
Referenz:
|
| Kos, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Managing Don't Cares in Boolean
Satisfiability
|
|
|
|
Autor:
|
|
Sean Safarpour, Andreas Veneris, Rolf Drechsler, Joanne Hang |
| Konferenz: |
|
IEEE Design, Automation and Test in Europe
|
Referenz:
|
| Vol. I, pp. 260-265, Paris, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Utilizing Don't Care States in SAT-based Bounded Sequential Problems
|
|
|
|
Autor:
|
|
Sean Safarpour, Görschwin Fey, Andreas Veneris, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI'05) |
Referenz:
|
| Chicago, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Enhancing Robustness of Sequential Circuits Using
Application-specific Knowledge and Formal Methods
|
|
|
|
Autor:
|
|
Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
22nd Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| Chiba/Tokyo, Japan, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers
|
|
|
|
Autor:
|
|
Sebastian Huhn, Stephan Eggersglüß and Rolf Drechsler |
| Konferenz: |
|
IEEE European Test Symposium (ETS) |
Referenz:
|
| Amsterdam, Niederlande, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Optimization of Retargeting for IEEE 1149.1 TAP Controllers with Embedded Compression
|
|
|
|
Autor:
|
|
Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Lausanne, Schweiz, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Reconfigurable TAP Controllers with Embedded Compression for Large Test Data Volume
|
|
|
|
Autor:
|
|
Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
30th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) |
Referenz:
|
| Cambridge, UK, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Proving Completeness of Properties in Formal Verification of Counting Heads for Railways
|
|
|
|
Autor:
|
|
Sebastian Kinder and Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD)
Architectures, Methods and Tools |
Referenz:
|
| Lübeck, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Efficient Formal Verification of Track Vacancy Detection Sections
|
|
|
|
Autor:
|
|
Sebastian Kinder und Rolf Drechsler |
| Konferenz: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008)
|
Referenz:
|
| pp. 233-240, Budapest, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Controlling the Memory During Manipulation of Word-Level Decision Diagrams
|
|
|
|
Autor:
|
|
Sebastian Kinder, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL 2005) |
Referenz:
|
| pp. 250-255, Calgary, 2005
|
Hyperlink:
|
| [Link zur Konferenz]
|
PS:
|
| [hier ansehen]
|
» Modeling and Formal Verification of Counting Heads for Railways
|
|
|
|
Autor:
|
|
Sebastian Kinder, Rolf Drechsler |
| Konferenz: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2007) |
Referenz:
|
| Braunschweig, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Synthesizing Multiplier in Reversible Logic
|
|
|
|
Autor:
|
|
Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 335-340, Vienna, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Efficient Realization of Control Logic in Reversible Circuits
|
|
|
|
Autor:
|
|
Sebastian Offermann, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Oldenburg, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Supporting Clinical Guidelines Using DL-Temporal Reasoning
|
|
|
|
Autor:
|
|
Serge Autexier, Mohamed Bawadekji, Dieter Hutter, Regine Wolters |
| Konferenz: |
|
International Conference & Expo on Emerging Technologies for a Smarter World (CEWIT) |
Referenz:
|
| Melville, NY, USA, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables
|
|
|
|
Autor:
|
|
Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Goerschwin Fey |
| Konferenz: |
|
IEEE Latin-American Test Symposium (LATS2016) |
Referenz:
|
| Foz do Iguaçu, Brazil, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» On the Relation Between SAT and BDDs for Equivalence Checking
|
|
|
|
Autor:
|
|
Sherif Reda, Rolf Drechsler and Alex Orailoglu |
| Konferenz: |
|
International Symposium on Quality of Electronic Design (ISQED 2002) |
Referenz:
|
| pages 394-399, San Jose, 2002
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» An Improved Gate Library for Logic Synthesis of Optical Circuits
|
|
|
|
Autor:
|
|
Shuchisman Burman, Kamalika Datta, Robert Wille, Indranil Sengupta, Rolf Drechsler |
| Konferenz: |
|
International Symposium on Electronic System Design (ISED) |
Referenz:
|
| Patna, Indien, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Minimal Stimuli Generation in Simulation-based Verification
|
|
|
|
Autor:
|
|
Shuo Yang, Robert Wille, Daniel Große and Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| Santander, Spain, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Coverage-driven Stimuli Generation
|
|
|
|
Autor:
|
|
Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
15th Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| Izmir, Turkey, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Determining Cases of Scenarios to Improve Coverage in Simulation-based Verication
|
|
|
|
Autor:
|
|
Shuo Yang, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Symposium on Integrated Circuits and System Design (SBCCI) |
Referenz:
|
| Aracaju, Brazil, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Improving Coverage of Simulation-based Verification by Dedicated Stimuli Generation
|
|
|
|
Autor:
|
|
Shuo Yang, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 599-606, Verona, Italy, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Hochoptimierter Ablauf zur Robustheitsprüfung
|
|
|
|
Autor:
|
|
Stefan Frehse, Finn Haedicke, Melanie Diepenbeck, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) |
Referenz:
|
| Hamburg-Harburg, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Kompositionelle Formale Robustheitsprüfung
|
|
|
|
Autor:
|
|
Stefan Frehse, Görschwin Fey |
| Konferenz: |
|
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) |
Referenz:
|
| Wildbad Kreuth, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
» RobuCheck: A Robustness Checker for Digital Circuits
|
|
|
|
Autor:
|
|
Stefan Frehse, Görschwin Fey, Andre Sülflow and Rolf Drechsler
|
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 226-231, Lille, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Robustness Check for Multiple Faults using Formal Techniques
|
|
|
|
Autor:
|
|
Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 85-90, Patras, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» A Better-Than-Worst-Case Robustness Measure
|
|
|
|
Autor:
|
|
Stefan Frehse, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 78-83, Vienna, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Hardware-Software-Co-Synthese zur Verbesserung der Fehlertoleranz
|
|
|
|
Autor:
|
|
Stefan Frehse, Heinz Riener, Görschwin Fey |
| Konferenz: |
|
6. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE'12) |
Referenz:
|
| pp. 90-96, Bremen, Germany, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Efficient Simulation-based Debugging of Reversible Logic
|
|
|
|
Autor:
|
|
Stefan Frehse, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
40th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 156-161, Barcelona, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automatic Fault Localization for Property Checking
|
|
|
|
Autor:
|
|
Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
| Konferenz: |
|
Haifa Verification Conference |
Referenz:
|
| Haifa, 2006
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Compact Test Set Generation for Test Compression-based Designs
|
|
|
|
Autor:
|
|
Stephan Eggersglüß |
| Konferenz: |
|
IEEE European Test Symposium (ETS) |
Referenz:
|
| Cluj-Napoca, Romania, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Peak Capture Power Reduction for Compact Test Sets Using Opt-Justification-Fill
|
|
|
|
Autor:
|
|
Stephan Eggersglüß |
| Konferenz: |
|
22nd IEEE Asian Test Symposium (ATS) |
Referenz:
|
| pp. 31-16, Yilan, Taiwan, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Experimental Studies on SAT-based ATPG for Gate Delay Faults
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
| Konferenz: |
|
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07) |
Referenz:
|
| Oslo, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Efficient Test Generation with Maximal Crosstalk-Induced Noise using Unconstrained Aggressor Excitation
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS) |
Referenz:
|
| pp. 649-652, Paris, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Speeding up SAT-based ATPG using Dynamic Clause Activation
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
| Konferenz: |
|
18th Asian Test Symposium (ATS'09) |
Referenz:
|
| pp. 177-182, Taichung, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» SAT-based ATPG for Path Delay Faults in Sequential Circuits
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'07) |
Referenz:
|
| pp. 3671-3674, New Orleans, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel |
| Konferenz: |
|
Fifth ACM-IEEE International Conference on
Formal Methods and Models for Codesign (MEMOCODE'2007) |
Referenz:
|
| pp. 181-187, Nice, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Optimization-based Multiple Target Test Generation for Highly Compacted Test Sets
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler |
| Konferenz: |
|
19th IEEE European Test Symposium (ETS) |
Referenz:
|
| Paderborn, Germany, 2014
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» SAT-Based Post-Processing for Regional Capture Power Reduction in At-Speed Scan Test Generation
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Kohei Miyase, Xiaoqing Wen |
| Konferenz: |
|
IEEE European Test Symposium (ETS) |
Referenz:
|
| Amsterdam, Niederlande, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Mahmut Yilmaz, Krishnendu Chakrabarty |
| Konferenz: |
|
21st IEEE Asian Test Symposium (ATS) |
Referenz:
|
| pp. 290-295, Niigata, Japan, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» A New SAT-based ATPG for Generating Highly Compacted Test Sets
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler |
| Konferenz: |
|
15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 230-235, Tallinn, Estonia, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Improved SAT-based ATPG: More Constraints, Better Compaction
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
IEEE/ACM International Conference on Computer-Aided Design (ICCAD) |
Referenz:
|
| pp. 85-90, San Jose, USA, 2013
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1291-1296, Grenoble, 2011
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Improving Test Pattern Compactness in SAT-based ATPG
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
16th Asian Test Symposium (ATS’07) |
Referenz:
|
| pp. 445-450, Beijing, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Increasing Robustness of SAT-based Delay Test Generation using Efficient Dynamic Learning Techniques
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
14th IEEE European Test Symposium (ETS) |
Referenz:
|
| pp. 81-86, Sevilla, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» On the Influence of Boolean Encodings in SAT-based ATPG for Path Delay Faults
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Referenz:
|
| pp. 94-99, Dallas, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Robust Algorithms for High Quality Test Pattern Generation Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
International Test Conference (ITC) |
Referenz:
|
| pp. 1-10, Austin, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen |
| Konferenz: |
|
IEEE Asian Test Symposium (ATS) |
Referenz:
|
| Hiroshima, Japan, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Co-Synthesis of Custom On-Chip Bus and Memory for
MPSoC Architectures
|
|
|
|
Autor:
|
|
Sujan Pandey, Christian Genz, Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration Systems and Systems on Chip (VLSI-SoC) |
Referenz:
|
| pp. 304-307, Atlanta, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Robust On-Chip Bus architecture Synthesis for MPSoCs Under Random Tasks Arrival
|
|
|
|
Autor:
|
|
Sujan Pandey, Rolf Drechsler |
| Konferenz: |
|
13th Asia and South Pacific Design Automation Conference, (ASP-DAC 2008) |
Referenz:
|
| Seoul, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs
|
|
|
|
Autor:
|
|
Sujan Pandey, Rolf Drechsler |
| Konferenz: |
|
Design, Automation, and Test in Europe (DATE) |
Referenz:
|
| Munich, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Process Variations Aware Robust on-Chip Bus Architecture Synthesis for MPSoCs
|
|
|
|
Autor:
|
|
Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'08) |
Referenz:
|
| Seattle, 2008
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Placement and Routing Optimization for Circuits Derived from BDDs
|
|
|
|
Autor:
|
|
Thomas Eschbach, Rolf Drechsler, Bernd Becker |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'04) |
Referenz:
|
| Vancouver, 2004
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Crossing Reduction by Windows Optimization
|
|
|
|
Autor:
|
|
Thomas Eschbach, Wolfgang Günther, Rolf Drechsler and Bernd Becker |
| Konferenz: |
|
10th International Symposium on Graph Drawing (GD'2002) |
Referenz:
|
| LNCS 2528, pp. 285-294, Irvine, 2002
|
PDF:
|
| [hier ansehen]
|
PS:
|
| [hier ansehen]
|
» Diagnostic Tests and Diagnosis for Delay Faults using Path Segmentation
|
|
|
|
Autor:
|
|
Tino Flenker, André Sülflow, Görschwin Fey |
| Konferenz: |
|
24th IEEE Asian Test Symposium (ATS) |
Referenz:
|
| Mumbai, India, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Mapping Abstract and Concrete Hardware Models for Design Understanding
|
|
|
|
Autor:
|
|
Tino Flenker, Görschwin Fey |
| Konferenz: |
|
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| Dresden, Germany, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects
|
|
|
|
Autor:
|
|
Tino Flenker, Jan Malburg, Goerschwin Fey, Serhiy Avramenko, Massimo Violante and Matteo Sonza Reorda |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| Bochum, Germany, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» ParTI - Towards Combined Hardware Countermeasures Against Side-Channel and Fault-Injection Attacks
|
|
|
|
Autor:
|
|
Tobias Schneider, Amir Moradi, Tim Güneysu |
| Konferenz: |
|
CRYPTO (2), Santa Barbara, USA, 2016: 302-332 |
Referenz:
|
| http://dx.doi.org/10.1007/978-3-662-53008-5_11
|
» Robust and One-Pass Parallel Computation of Correlation-Based Attacks at Arbitrary Order
|
|
|
|
Autor:
|
|
Tobias Schneider, Amir Moradi, Tim Güneysu |
| Konferenz: |
|
COSADE 2016, Graz, p. 199-217 |
Referenz:
|
| http://dx.doi.org/10.1007/978-3-319-43283-0_12
|
» SAT-Based ATPG Testing of Inter- and Intra-Gate Bridging Faults
|
|
|
|
Autor:
|
|
Toru Nakura, Yutaro Tatemura, Görschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada |
| Konferenz: |
|
European Conference on Circuit Theory and Design |
Referenz:
|
| Antalya, 2009
|
» Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
|
|
|
|
Autor:
|
|
Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07) |
Referenz:
|
| pp. 165-170, Porto Alegre, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Property Analysis and Design Understanding
|
|
|
|
Autor:
|
|
Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE)
|
Referenz:
|
| pp. 1246-1249, Nice, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» SyDe - a New Graduate School for
System Design in an Excellent Setting
|
|
|
|
Autor:
|
|
Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Informatics Europe (ECSS) |
Referenz:
|
| Barcelona, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Generating an Efficient Instruction Set Simulator from a Complete Property Suite
|
|
|
|
Autor:
|
|
Ulrich Kühne, Sven Beyer, Christian Pichler |
| Konferenz: |
|
IEEE/IFIP International Symposium on Rapid System Prototyping (RSP) |
Referenz:
|
| pp. 109-115, Paris, 2009
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Automated Formal Verification of Processors Based on Architectural Models
|
|
|
|
Autor:
|
|
Ulrich Kühne, Sven Beyer, Jörg Bormann, John Barstow |
| Konferenz: |
|
Formal Methods in Computer Aided Design (FMCAD) |
Referenz:
|
| Lugano, Switzerland, 2010
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Evaluation of Babbling Idiot Failures in FlexRay-Based Networks
|
|
|
|
Autor:
|
|
Vahid Lari, Mehdi Dehbashi, Seyed Ghassem Miremadi, Mojtaba Amiri |
| Konferenz: |
|
7th IFAC International Conference on Fieldbuses and Networks in Industrial and Embedded Systems (FET) |
Referenz:
|
| pp. 399-406, Toulouse, France, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Assessment of Message Missing Failures in FlexRay-Based Networks
|
|
|
|
Autor:
|
|
Vahid Lari, Mehdi Dehbashi, Seyed Ghassem Miremadi, Navid Farazmand |
| Konferenz: |
|
13th IEEE/IFIP Pacific Rim International Symposium on Dependable Computing (PRDC) |
Referenz:
|
| pp. 191-194, Melbourne, Australia, 2007
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Testability of SPP Three-Level Logic Networks
|
|
|
|
Autor:
|
|
Valentina Ciriani, Anna Bernasconi, Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (VLSI'03) |
Referenz:
|
| pp. 331-336, Darmstadt, 2003
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Lazy-CSeq-SP: Boosting Sequentialization-based Verification of Multi-Threaded C Programs via Symbolic Pruning of Redundant Schedules
|
|
|
|
Autor:
|
|
Vladimir Herdt, Hoang M. Le, Daniel Große and Rolf Drechsler |
| Konferenz: |
|
Automated Technology for Verification and Analysis (ATVA) |
Referenz:
|
| pp. 228-233, Shanghai, China, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Compiled Symbolic Simulation for SystemC
|
|
|
|
Autor:
|
|
Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
|
| Konferenz: |
|
International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| Austin, USA, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-based Error Effect Simulation - A Case Study
|
|
|
|
Autor:
|
|
Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Bremen, Germany, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» ParCoSS: Efficient Parallelized Compiled Symbolic Simulation
|
|
|
|
Autor:
|
|
Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
International Conference on Computer Aided Verification (CAV) |
Referenz:
|
| Toronto, Canada, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Towards Early Validation of Firmware-Based Power
Management using Virtual Prototypes:
A Constrained Random Approach
|
|
|
|
Autor:
|
|
Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Verona, Italy, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
» Verifying SystemC using Stateful Symbolic Simulation
|
|
|
|
Autor:
|
|
Vladimir Herdt, Hoang M. Le, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| San Francisco, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Computing Walsh, Arithmetic and Reed-Muller Spectral Decision Diagrams Using Graph Transformations
|
|
|
|
Autor:
|
|
Whitney Townsend, Mitch Thornton, Rolf Drechsler and Michael Miller |
| Konferenz: |
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IEEE Great Lakes Symposium on VLSI (GLSV'02) |
Referenz:
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| pp. 178-183, New York, 2002
|
PDF:
|
| [hier ansehen]
|
» Realizing Reversible Circuits Using a New Class of Quantum Gates
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Autor:
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Zahra Sasanian, Robert Wille, Michael Miller |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| San Francisco, 2012
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Towards Line-aware Realizations of Expressions for HDL-based Synthesis of Reversible Circuits
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Autor:
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Zaid Al-Wardi, Robert Wille, Rolf Drechsler
|
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Grenoble, France, 2015
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Towards VHDL-based Design of Reversible Circuits
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Autor:
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|
Zaid Al-Wardi, Robert Wille, Rolf Drechsler
|
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Kolkata, India, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Extensions to the Reversible Hardware Description Language SyReC
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|
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Autor:
|
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Zaid Al-Wardi, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
47th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Novi Sad, Serbia, 2017
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
» Re-writing HDL Descriptions for Line-aware Synthesis of Reversible Circuits
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Autor:
|
|
Zaid Al-Wardi, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
46th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Sapporo, Japan, 2016
|
Hyperlink:
|
| [Link zur Konferenz]
|
PDF:
|
| [hier ansehen]
|
