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Home « Team « Publikationen
» Publikationen von
André Sülflow
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BÜCHER |
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» WoLFram - A Word Level Framework for Formal Verification and its Application
[Lesen Sie hier mehr!]
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Verlag: |
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Shaker |
Autor:
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Andre Sülflow |
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Gebunden |
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2010
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» EXplayN - Strategieoptimierung und Analyse ausgewählter Spielprobleme
[Lesen Sie hier mehr!]
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Verlag: |
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Shaker Verlag |
Autor:
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Daniel Große, Andre Sülflow, Nicole Drechsler (Hrsg.) |
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gebunden |
Erscheinungsjahr:
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2008
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BUCHBEITRÄGE |
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ZEITSCHRIFTEN |
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» Automated Design Debugging in a Testbench-Based Verification Environment
[Link zur Zeitschriften-Homepage]
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Autor:
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Mehdi Dehbashi, André Sülflow, Görschwin Fey |
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Embedded Hardware Design - Microprocessors and Microsystems (MICPRO) |
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Volume 37, Issue 2, pp. 206-217 |
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2013
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» Effective Robustness Analysis using Bounded Model Checking Techniques
[Link zur Zeitschriften-Homepage]
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Autor:
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Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 30, Number 8, pp. 1239-1252
DOI: 10.1109/TCAD.2011.2120950 |
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2011
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» Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen
[Link zur Zeitschriften-Homepage]
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Autor:
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Görschwin Fey, Andre Sülflow, Stefan Frehse, Rolf Drechsler |
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it-Information Technology |
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Volume 52, Number 4, pp. 216-223
PDF Download |
Jahr:
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2010
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KONFERENZEN |
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» Incorporating User Preferences in Many-Objective Optimization using Relation Epsilon-Preferred
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Autor:
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Nicole Drechsler, André Sülflow, Rolf Drechsler |
| Konferenz: |
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International Conference on Evolutionary Computation Theory and Applications (ECTA) |
Referenz:
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| Vilamoura, Portugal, 2013
| Hyperlink:
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| [Link zur Konferenz]
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» Synchronized Debugging across Different Abstraction Levels in System Design
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Autor:
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Rolf Drechsler, Daniel Große, Hoang M. Le, André Sülflow |
| Konferenz: |
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embedded world Conference 2013 |
Referenz:
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| Nürnberg, 2013
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» FoREnSiC - An Automatic Debugging Environment for C Programs
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Autor:
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Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow
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Haifa Verification Conference (HVC) |
Referenz:
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| Haifa, 2012
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| [Link zur Konferenz]
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| [hier ansehen]
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» Automated Design Debugging in a Testbench-Based Verification Environment
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Autor:
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Mehdi Dehbashi, André Sülflow, Görschwin Fey |
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14th Euromicro Conference on Digital System Design (DSD) |
Referenz:
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| pp. 479-486, Oulu, Finland, 2011
Best Paper Candidate
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» VisSAT: Visualization of SAT Solver Internals for Computer Aided Hardware Verification
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Autor:
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Robert Wille, André Sülflow, Rolf Drechsler |
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International Conference on Modeling, Simulation and Visualization Methods (MSV) |
Referenz:
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| pp. 36-39, Las Vegas, 2011
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Latency Analysis for Sequential Circuits
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Autor:
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Alexander Finder, André Sülflow, Görschwin Fey |
| Konferenz: |
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16th IEEE European Test Symposium (ETS) |
Referenz:
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| pp. 129-134, Trondheim, 2011
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Automatic Fault Localization for Programmable Logic Controllers
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Autor:
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Andre Sülflow, Rolf Drechsler |
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Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT) |
Referenz:
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| pp. 247-256, Braunschweig, 2010
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» RobuCheck: A Robustness Checker for Digital Circuits
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Autor:
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Stefan Frehse, Görschwin Fey, Andre Sülflow and Rolf Drechsler
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| Konferenz: |
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Euromicro Conference on Digital System Design (DSD) |
Referenz:
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| pp. 226-231, Lille, 2010
| Hyperlink:
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| [Link zur Konferenz]
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| [hier ansehen]
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» Using QBF to Increase Accuracy of SAT-Based Debugging
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Autor:
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Andre Sülflow, Görschwin Fey, Rolf Drechsler |
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IEEE International Symposium on Circuits and Systems (ISCAS) |
Referenz:
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| pp.641-644, Paris, 2010
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Anwendungsbezogene Analyse der Robustheit von Digitalen Schaltungen
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Autor:
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Andre Sülflow, Stefan Frehse, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
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GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) |
Referenz:
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| pp. 45-52, Stuttgart, 2009
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Robustness Check for Multiple Faults using Formal Techniques
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Autor:
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Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler |
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Euromicro Conference on Digital System Design (DSD) |
Referenz:
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| pp. 85-90, Patras, 2009
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Computing Bounds for Fault Tolerance using Formal Techniques
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Autor:
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Görschwin Fey, Andre Sülflow, Rolf Drechsler |
| Konferenz: |
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Design Automation Conference (DAC) |
Referenz:
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| pp. 190-195, San Francisco, USA, 2009
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» WoLFram - A Word Level Framework for Formal Verification
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Autor:
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Andre Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler |
| Konferenz: |
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IEEE/IFIP International Symposium on Rapid System Prototyping (RSP) |
Referenz:
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| pp. 11-17, Paris, 2009
| Hyperlink:
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| [Link zur Konferenz]
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| [hier ansehen]
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» Evaluation of Cardinality Constraints on SMT-based Debugging
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Autor:
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Andre Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
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39th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| pp. 298-303, Naha, Okinawa, 2009
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Increasing the Accuracy of SAT-based Debugging
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Autor:
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Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| pp. 1326-1332, Nice, 2009
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Formaler Nachweis der Fehlertoleranz von Schaltkreisen
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Autor:
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Görschwin Fey, Andre Sülflow, Stefan Frehse, Ulrich Kühne, Rolf Drechsler |
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GMM/GI/ITG-Fachtagung: Zuverlässigkeit und Entwurf (ZuE 2008) |
Referenz:
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| pp. 75-82, Ingolstadt, 2008
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Verification of PLC Programs using Formal Proof Techniques
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Autor:
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Andre Sülflow, Rolf Drechsler |
| Konferenz: |
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Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008) |
Referenz:
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| pp. 43-50, Budapest, 2008
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Using Unsatisfiable Cores to Debug Multiple Design Errors
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Autor:
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Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
| Konferenz: |
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IEEE Great Lakes Symposium on VLSI (GLSVLSI'08) |
Referenz:
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| pp. 77-82, Orlando, 2008
| Hyperlink:
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| [Link zur Konferenz]
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| [hier ansehen]
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» Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^m) in SystemC
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Autor:
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Andre Sülflow, Rolf Drechsler |
| Konferenz: |
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37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07) |
Referenz:
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| pp. 42, Oslo, 2007
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Robust Multi-Objective Optimization in High Dimensional Spaces
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Autor:
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André Sülflow, Nicole Drechsler, Rolf Drechsler |
| Konferenz: |
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Fourth International Conference on Evolutionary Multi-Criterion Optimization |
Referenz:
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| pp. 715-726, Matsushima, 2007
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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WORKSHOPS |
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» Latency Analysis for Sequential Circuits
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Autor:
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Alexander Finder, André Sülflow, Görschwin Fey |
| Workshop: |
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23. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2011 |
Referenz:
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| Passau, 2011
| PDF:
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| [hier ansehen]
| Hyperlink:
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| [Link zum Workshop]
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» Towards Unifying Localization and Explanation for Automated Debugging
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Autor:
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Görschwin Fey, André Sülflow, Rolf Drechsler |
| Workshop: |
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11th International Workshop on Microprocessor Test and Verification (MTV) |
Referenz:
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| pp. 3-8, Austin, Texas, 2010
| PDF:
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| [hier ansehen]
| Hyperlink:
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| [Link zum Workshop]
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» RobuCheck: A Robustness Checker for Digital Circuits
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Autor:
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Stefan Frehse, Görschwin Fey, Andre Sülflow and Rolf Drechsler
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The First International Workshop on Dynamic Aspects
in Dependability Models for Fault-Tolerant Systems (DYADEM-FTS) |
Referenz:
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| Valencia, 2010
| Hyperlink:
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| [Link zum Workshop]
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» VisSAT: Visualization of SAT Solver Internals
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Autor:
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Robert Wille, Andre Sülflow, Christian Genz, Rolf Drechsler |
| Workshop: |
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University Booth at Design, Automation and Test in Europe (DATE10) |
Referenz:
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| Dresden, 2010
| PDF:
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| [hier ansehen]
| Hyperlink:
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| [Link zum Workshop]
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» Using QBF to Increase the Accuracy of SAT-Based Debugging
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Autor:
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Andre Sülflow, Görschwin Fey, Rolf Drechsler |
| Workshop: |
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International Workshop on Constraints in Formal Verification (CFV) |
Referenz:
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| Grenoble, France, 2009
| PDF:
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| [hier ansehen]
| Hyperlink:
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| [Link zum Workshop]
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» Model-Based Diagnosis for Programmable Logic Controllers
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Autor:
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Andre Sülflow, Rolf Drechsler |
| Workshop: |
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Gemeinsamer Workshop der Informatik-Graduiertenkollegs und Forschungskollegs |
Referenz:
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| Dagstuhl, 2009
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» Robustness Check for Multiple Faults using Formal Techniques
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Autor:
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Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler |
| Workshop: |
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Constraints in Formal Verification (CFV) |
Referenz:
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| Grenoble, France, 2009
| PDF:
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| [hier ansehen]
| Hyperlink:
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| [Link zum Workshop]
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» FormED: A Formal Environment for Debugging
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Autor:
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Andre Sülflow, Robert Wille, Christian Genz, Görschwin Fey, Rolf Drechsler |
| Workshop: |
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University Booth at Design, Automation and Test in Europe (DATE09) |
Referenz:
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| Nizza, 2009
| PDF:
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| [hier ansehen]
| Hyperlink:
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| [Link zum Workshop]
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» Increasing the Accuracy of SAT-based Debugging
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Autor:
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Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
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12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
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| pp. 47-56, Berlin, 2009
| PDF:
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| [hier ansehen]
| Hyperlink:
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| [Link zum Workshop]
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» Computing Bounds for Fault Tolerance using Formal Techniques
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Autor:
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Andre Sülflow, Görschwin Fey, Stefan Frehse, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
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IEEE Workshop on Design for Reliability and Variability (DRV) |
Referenz:
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| Santa Clara, USA, 2008
| PDF:
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| [hier ansehen]
| Hyperlink:
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| [Link zum Workshop]
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» Experimental Studies on SMT-based Debugging
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Autor:
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Andre Sülflow, Görschwin Fey, Rolf Drechsler |
| Workshop: |
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IEEE 9th Workshop on RTL and High Level Testing (WRTLT'08) |
Referenz:
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| pp. 93-98, Japan, 2008
| PDF:
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| [hier ansehen]
| Hyperlink:
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| [Link zum Workshop]
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» Debugging Design Errors by Using Unsatisfiable Cores
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Autor:
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Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
| Workshop: |
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11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen
zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
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| pp. 159-168, Freiburg, 2008
| PDF:
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| [hier ansehen]
| Hyperlink:
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| [Link zum Workshop]
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» Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits
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Autor:
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Andre Sülflow, Ulrich Kühne, Robert Wille, Daniel Große, Rolf Drechsler |
| Workshop: |
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IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07) |
Referenz:
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| pp. 31-36, Beijing, P.R.China, 2007
| PDF:
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| [hier ansehen]
| Hyperlink:
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| [Link zum Workshop]
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» Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse
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Autor:
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Andre Sülflow, Görschwin Fey, Rolf Drechsler |
| Workshop: |
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GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Referenz:
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| pp. 101-110, Erlangen, 2007
| PDF:
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| [hier ansehen]
| Hyperlink:
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| [Link zum Workshop]
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