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Home « Team « Publikationen
» Publikationen von
Daniel Große
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BÜCHER |
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» Quality-Driven SystemC Design
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Daniel Große, Rolf Drechsler |
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Hardcover |
Erscheinungsjahr:
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2010
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» EXplayN - Strategieoptimierung und Analyse ausgewählter Spielprobleme
[Lesen Sie hier mehr!]
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Verlag: |
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Shaker Verlag |
Autor:
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Daniel Große, Andre Sülflow, Nicole Drechsler (Hrsg.) |
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gebunden |
Erscheinungsjahr:
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2008
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» SATRIX - Algorithmen für Boolesche Erfüllbarkeit
[Lesen Sie hier mehr!]
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Verlag: |
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Shaker Verlag |
Autor:
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Daniel Große, Görschwin Fey, Rolf Drechsler (Hrsg.) |
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Gebunden |
Erscheinungsjahr:
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2007
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BUCHBEITRÄGE |
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| » Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis |
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Autor:
| Daniel Große, Görschwin Fey, Rolf Drechsler
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| Herausgeber: | Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus |
| Buchtitel: | Design and Test Technology for Dependable Systems-on-Chip |
| Verlag: | Information Science Reference |
| Seiten: | 119-129 |
| Erscheinungsjahr: | 2011 |
| Format: | Hardcover |
| » SMT-based Stimuli Generation in the SystemC Verification Library |
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Autor:
| Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler
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| Herausgeber: | Dominique Borrione |
| Buchtitel: | Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s: Selected Contributions on Specification, Design, and Verification from FDL 2009 |
| Verlag: | Springer |
| Seiten: | 227-244 |
| Erscheinungsjahr: | 2010 |
| Format: | Hardcover |
| » Debugging Contradictory Constraints in Constraint-based Random Simulation |
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Autor:
| Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
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| Herausgeber: | Martin Radetzki |
| Buchtitel: | Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL'08 |
| Verlag: | Springer |
| Seiten: | 273-290 |
| Erscheinungsjahr: | 2009 |
| Format: | gebunden |
| » SWORD: A SAT like Prover Using Word Level Information |
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Autor:
| Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
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| Herausgeber: | Ricardo Reis, Vincent Mooney, Paul Hasler |
| Buchtitel: | VLSI-SoC: Advanced Topics on Systems on a Chip:
A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip |
| Verlag: | Springer |
| Seiten: | 175-192 |
| Erscheinungsjahr: | 2009 |
| Format: | Hardcover |
| » Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques |
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Autor:
| Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler
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| Herausgeber: | Eugenio Villar |
| Buchtitel: | Embedded Systems Specification and Design Languages: Selected contributions from FDL'07 |
| Verlag: | Springer |
| Seiten: | 73-86 |
| Erscheinungsjahr: | 2008 |
| Format: | gebunden |
| » Processor Verification |
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Autor:
| Daniel Große, Robert Siegmund, Rolf Drechsler
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| Herausgeber: | Paolo Ienne, Rainer Leupers |
| Buchtitel: | Customizable Embedded Processors |
| Verlag: | Elsevier |
| Seiten: | 281-302 |
| Erscheinungsjahr: | 2006 |
| Format: | gebunden |
| » System-level validation using formal techniques |
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Autor:
| Rolf Drechsler, Daniel Große
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| Herausgeber: | Bashir M. Al-Hashimi |
| Buchtitel: | System-on-Chip: Next Generation Electronics |
| Verlag: | The IEE |
| Seiten: | 715-745 |
| Erscheinungsjahr: | 2006 |
| Format: | gebunden |
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ZEITSCHRIFTEN |
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» Automatic TLM Fault Localization for SystemC
[Link zur Zeitschriften-Homepage]
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Autor:
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Hoang M. Le, Daniel Große, Rolf Drechsler |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 31, Number 8, pp. 1249-1262,
DOI: 10.1109/TCAD.2012.2188800
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Jahr:
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2012
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» Debugging Reversible Circuits
[Link zur Zeitschriften-Homepage]
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Autor:
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Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler |
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INTEGRATION, the VLSI Journal |
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Volume 44, Number 1, pp. 51-61, JanuaryDOI: 10.1016/j.vlsi.2010.08.002 |
Jahr:
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2011
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» Towards Fully Automatic Synthesis of Embedded Software
[Link zur Zeitschriften-Homepage]
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Autor:
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Ulrich Kühne, Daniel Große, Rolf Drechsler |
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IEEE Embedded Systems Letters |
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Volume 2, Number 3, pp. 53-57, September |
Jahr:
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2010
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» Exact Synthesis of Elementary Quantum Gate Circuits
[Link zur Zeitschriften-Homepage]
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Autor:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
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Multiple-Valued Logic and Soft Computing |
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Volume 15, Number 4, pp. 283-300 |
Jahr:
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2009
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» Exact Multiple Control Toffoli Network Synthesis with SAT Techniques
[Link zur Zeitschriften-Homepage]
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Autor:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 28, Number 5, pp. 703-715, MayDOI: 10.1109/TCAD.2009.2017215 |
Jahr:
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2009
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» Analyzing Functional Coverage in Bounded Model Checking
[Link zur Zeitschriften-Homepage]
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Autor:
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Daniel Große, Ulrich Kühne, Rolf Drechsler |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 27, Number 7, pp. 1305-1314, July |
Jahr:
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2008
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» BDD-based Verification of Scalable Designs
[Link zur Zeitschriften-Homepage]
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Autor:
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Daniel Große, Rolf Drechsler |
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Facta Universitatis, Series: Electronics and Energetics |
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Volume 20, Number 3, pp. 367-379 |
Jahr:
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2007
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» System Level Validation Using Formal Techniques
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler, Daniel Große |
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IEE Proceedings Computer & Digital Techniques, Special Issue on Embedded Microelectronic Systems: Status and Trends |
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Volume 152, Number 3, pp. 393-406, May |
Jahr:
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2005
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» Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC
[Link zur Zeitschriften-Homepage]
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Autor:
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Daniel Große, Rolf Drechsler |
| Zeitschrift: |
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it - information technology |
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Number 4, pp. 219-226, August |
Jahr:
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2003
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» Heuristic Learning based on Genetic Programming
[Link zur Zeitschriften-Homepage]
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Autor:
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Frank Schmiedle, Nicole Drechsler, Daniel Große and Rolf Drechsler |
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Genetic Programming and Evolvable Machines |
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Volume 3, pp. 363-388, December |
Jahr:
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2002
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KONFERENZEN |
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» Minimal Stimuli Generation in Simulation-based Verification
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Autor:
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Shuo Yang, Robert Wille, Daniel Große and Rolf Drechsler |
| Konferenz: |
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Euromicro Conference on Digital System Design (DSD) |
Referenz:
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| Santander, Spain, 2013
| Hyperlink:
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| [Link zur Konferenz]
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» Verifying SystemC using an Intermediate Verification Language and Symbolic Simulation
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Autor:
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Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler |
| Konferenz: |
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Design Automation Conference (DAC) |
Referenz:
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| Austin, Texas, 2013
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Synchronized Debugging across Different Abstraction Levels in System Design
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Autor:
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Rolf Drechsler, Daniel Große, Hoang M. Le, André Sülflow |
| Konferenz: |
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embedded world Conference 2013 |
Referenz:
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| Nürnberg, 2013
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Scalable Fault Localization for SystemC TLM Designs
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Autor:
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Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
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Design, Automation and Test in Europe (DATE'13) |
Referenz:
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| pp. 35-38, Grenoble, France, 2013
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» From Requirements and Scenarios to ESL Design in SystemC
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Autor:
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Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
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International Symposium on Electronic System Design (ISED) |
Referenz:
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| Kolkata, WB, India, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» The System Verification Methodology for
Advanced TLM Verification
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Autor:
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Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler, Wolfgang Ecker, Volkan Esen |
| Konferenz: |
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International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) |
Referenz:
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| pp. 313-322, Tampere, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Completeness-Driven Development
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Autor:
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Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille |
| Konferenz: |
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International Conference on Graph Transformation |
Referenz:
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| pp. 38-50, Bremen, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC
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Autor:
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Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
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International Symposium on System-on-Chip (SoC) |
Referenz:
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| pp. 1-7, Tampere, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Localizing Features of ESL Models for Design Understanding
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Autor:
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Marc Michael, Daniel Große, Rolf Drechsler |
| Konferenz: |
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Forum on specification & Design Languages (FDL) |
Referenz:
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| Vienna, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Coverage-driven Stimuli Generation
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Autor:
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Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler |
| Konferenz: |
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15th Euromicro Conference on Digital System Design (DSD) |
Referenz:
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| Izmir, Turkey, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» A Guiding Coverage Metric for Formal Verification
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Autor:
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Finn Haedicke, Daniel Große, Rolf Drechsler |
| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| Dresden, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Analyzing Dependability Measures at the Electronic System Level
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Autor:
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Marc Michael, Daniel Große, Rolf Drechsler |
| Konferenz: |
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Forum on specification & Design Languages (FDL) |
Referenz:
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| pp. 1-8, Oldenburg, 2011
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» TLM Protocol Compliance Checking at the Electronic System Level
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Autor:
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Mohamed Bawadekji, Daniel Große, Rolf Drechsler |
| Konferenz: |
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14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
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| pp. 435-440, Cottbus, 2011
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Designing a RISC CPU in Reversible Logic
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Autor:
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Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler |
| Konferenz: |
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41st International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| pp. 170-175, Tuusula, 2011
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Simulation-based Equivalence Checking between SystemC Models at different Levels of Abstraction
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Autor:
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Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
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Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
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| pp. 223-228, Lausanne, 2011
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Proving Transaction and System-level Properties of Untimed SystemC TLM Designs
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Autor:
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Daniel Große, Hoang M. Le, Rolf Drechsler |
| Konferenz: |
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International Conference on
Formal Methods and Models for Codesign (MEMOCODE) |
Referenz:
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| pp. 113-122, Grenoble, 2010
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» SMT-based Stimuli Generation in the SystemC Verification Library
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Autor:
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Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler |
| Konferenz: |
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Forum on specification & Design Languages (FDL) |
Referenz:
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| pp. 1-6, Sophia Antipolis, 2009
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» WoLFram - A Word Level Framework for Formal Verification
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Autor:
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Andre Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler |
| Konferenz: |
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IEEE/IFIP International Symposium on Rapid System Prototyping (RSP) |
Referenz:
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| pp. 11-17, Paris, 2009
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Contradictory Antecedent Debugging in Bounded Model Checking
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Autor:
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Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
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Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
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| pp. 173-176, Boston, 2009
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Equivalence Checking of Reversible Circuits
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Autor:
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Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler |
| Konferenz: |
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39th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| pp. 324-330, Naha, Okinawa, 2009
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Property Analysis and Design Understanding
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Autor:
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Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Konferenz: |
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Design, Automation and Test in Europe (DATE)
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Referenz:
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| pp. 1246-1249, Nice, 2009
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Debugging of Toffoli Networks
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Autor:
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Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
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| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| pp. 1284-1289, Nice, 2009
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Reversible Logic Synthesis with Output Permutation
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Autor:
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Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
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22nd International Conference on VLSI Design |
Referenz:
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| pp. 189-194, New Delhi, 2009
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Contradiction Analysis for Constraint-based Random Simulation
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Autor:
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Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler |
| Konferenz: |
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Forum on specification & Design Languages (FDL) |
Referenz:
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| pp. 130-135, Stuttgart, 2008
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability
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Autor:
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Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
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| pp. 411-416, Montpellier, 2008
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» RevLib: An Online Resource for
Reversible Functions and Reversible Circuits
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Autor:
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Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
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38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Referenz:
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| pp. 220-225, Dallas, 2008
RevLib is available at www.revlib.org
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Exact Synthesis of Elementary Quantum Gate
Circuits for Reversible Functions with Don’t Cares
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Autor:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
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38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Referenz:
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| pp. 214-219, Dallas, 2008
Received IEEE Young Researcher Award
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Quantified Synthesis of Reversible Logic
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Autor:
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Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große |
| Konferenz: |
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Design, Automation, and Test in Europe (DATE) |
Referenz:
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| pp. 1015-1020, Munich, 2008
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Fast Exact Toffoli Network Synthesis of Reversible Logic
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Autor:
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Robert Wille, Daniel Große |
| Konferenz: |
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IEEE International Conference on Computer Aided Design (ICCAD) |
Referenz:
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| pp. 60-64, San Jose, 2007
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» SWORD: A SAT like Prover Using Word Level Information
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Autor:
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Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
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IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC) |
Referenz:
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| pp. 88-93, Atlanta, 2007
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Measuring the Quality of a SystemC Testbench by using Code Coverage Technqiues
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Autor:
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Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler |
| Konferenz: |
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Forum on specification & Design Languages (FDL) |
Referenz:
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| pp. 146-151, Barcelona, 2007
Received Best Paper Award
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
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Autor:
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Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Konferenz: |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07) |
Referenz:
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| pp. 165-170, Porto Alegre, 2007
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL
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Autor:
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Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler |
| Konferenz: |
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37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07) |
Referenz:
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| Oslo, 2007
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Improvements for Constraint Solving in the SystemC Verification Library
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Autor:
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Daniel Große, Rüdiger Ebendt, Rolf Drechsler |
| Konferenz: |
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Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
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| pp. 493-496, Stresa, 2007
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Exact SAT-based Toffoli Network Synthesis
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Autor:
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Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
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Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
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| pp. 96-101, Stresa, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Estimating Functional Coverage in Bounded Model Checking
|
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|
Autor:
|
|
Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1176-1181, Nice, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» HW/SW Co-Verification of Embedded Systems using Bounded Model Checking
|
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Autor:
|
|
Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 43-48, Philadelphia, 2006
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks
|
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Autor:
|
|
Görschwin Fey, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1225-1226, Munich, 2006
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Acceleration of SAT-based Iterative Property Checking
|
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Autor:
|
|
Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Correct Hardware Design and Verification Methods (CHARME) |
Referenz:
|
| pp. 349-353, Saarbrücken, 2005
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» CheckSyC: An Efficient Property Checker for RTL SystemC Designs
|
|
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|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'05) |
Referenz:
|
| pp. 4167-4170, Kobe, 2005
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Automated Verification For Train Control Systems
|
|
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|
Autor:
|
|
Jan Peleska, Daniel Große, Anne E. Haxthausen, Rolf Drechsler |
| Konferenz: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2004) |
Referenz:
|
| pp. 252-265, Braunschweig, 2004
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Checkers for SystemC Designs
|
|
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|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Second ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2004) |
Referenz:
|
| pp. 171-178, San Diego, 2004
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Efficient Automatic Visualization of SystemC Designs
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst |
| Konferenz: |
|
Forum on Specification & Design Languages (FDL'03) |
Referenz:
|
| pp. 646-657, Frankfurt, 2003
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Modeling Multi-Valued Circuits in SystemC
|
|
|
|
Autor:
|
|
Daniel Große, Görschwin Fey and Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003) |
Referenz:
|
| pp. 281-286, Tokyo, 2003
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
| PS:
|
| [hier ansehen]
|
» Formal Verification of LTL Formulas for SystemC Designs
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'03) |
Referenz:
|
| pp. V:245-V:248, Bangkok, 2003
| PDF:
|
| [hier ansehen]
|
» Reachability Analysis for Formal Verification of SystemC
|
|
|
|
Autor:
|
|
Rolf Drechsler and Daniel Große |
| Konferenz: |
|
Euromicro Symposium on Digital System Design (DSD'2002) |
Referenz:
|
| pages 337-340, Dortmund, 2002
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
|
WORKSHOPS |
|
» Towards Automatic Scenario Generation from Coverage Information
|
|
|
|
Autor:
|
|
Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler |
| Workshop: |
|
8th International Workshop on Automation of Software Test (AST) |
Referenz:
|
| pp. 82-88, San Francisco, 2013
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» SystemC Verifikation mittels symbolischer Simulation einer Zwischensprache
|
|
|
|
Autor:
|
|
Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler |
| Workshop: |
|
edaWorkshop |
Referenz:
|
| pp. 53-58, Dresden, 2013
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Behavior Driven Development for Circuit Design and Verification
|
|
|
|
Autor:
|
|
Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler |
| Workshop: |
|
IEEE International Workshop on High-Level Design Validation and Test (HLDVT) |
Referenz:
|
| Huntington Beach, USA, 2012
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Design Understanding by Feature Localization on ESL
|
|
|
|
Autor:
|
|
Marc Michael, Daniel Große, Rolf Drechsler |
| Workshop: |
|
9. GMM/ITG/GI-Workshop Cyber-Physical Systems – Enabling Multi-Nature Systems (CPMNS) |
Referenz:
|
| pp. 19-24, Dresden, 2012
| Hyperlink:
|
| [Link zum Workshop]
|
» Compilation of Methodologies to Speed up the Verification Process
at System Level
|
|
|
|
Autor:
|
|
Stephan Radke, Steffen Rülke, Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Müller, Wolfgang Ecker, Volkan Esen, Simon Hufnagel, Nico Bannow, Helmut Brazdrum, Peter Janssen, Hoang M. Le, Daniel Große, Rolf Drechsler, Erhard Fehlauer, Gernot Koch, Andreas Burger, Oliver Bringmann, Wolfgang Rosenstiel, Finn Haedicke, Ralph Görgen, Jan-Hendrik Oetjens |
| Workshop: |
|
edaWorkshop |
Referenz:
|
| pp. 57-62, Hannover, 2012
| Hyperlink:
|
| [Link zum Workshop]
|
» SystemC-based ESL Verification Flow
Integrating Property Checking and Automatic
Debugging
|
|
|
|
Autor:
|
|
Hoang M. Le, Daniel Große, Rolf Drechsler |
| Workshop: |
|
DATE Friday Workshop: OSCI and Accellera Core Technologies for the Next Generation of System-Level Design |
Referenz:
|
| Dresden, 2012
| Hyperlink:
|
| [Link zum Workshop]
|
» CRAVE: An Advanced Constrained Random Verification Environment for SystemC
|
|
|
|
Autor:
|
|
Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler |
| Workshop: |
|
15. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) |
Referenz:
|
| Kaiserslautern, 2012
Software and benchmarks available at www.systemc-verification.org
| Hyperlink:
|
| [Link zum Workshop]
|
» Towards Proving TLM Properties with Local Variables
|
|
|
|
Autor:
|
|
Hoang M. Le, Daniel Große, Rolf Drechsler |
| Workshop: |
|
7th International Workshop on Constraints in Formal Verification (CFV) |
Referenz:
|
| San Jose, 2011
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» metaSMT: Focus on Your Application not on Solver Integration
|
|
|
|
Autor:
|
|
Finn Haedicke, Stefan Frehse, Görschwin Fey, Daniel Große, Rolf Drechsler |
| Workshop: |
|
DIFTS'11: 1st International workshop on design and implementation of formal tools and systems |
Referenz:
|
| pp. 22-29, Austin, USA, 2011
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines
|
|
|
|
Autor:
|
|
Kim Grüttner, Andreas Herrholz, Ulrich Kühne, Daniel Große, Achim Rettberg, Wolfgang Nebel, Rolf Drechsler |
| Workshop: |
|
SORT 2011: 2nd IEEE Workshop on Self-Organizing Real-Time Systems |
Referenz:
|
| pp. 181-188, Newport Beach, 2011
| Hyperlink:
|
| [Link zum Workshop]
|
» Protocol Compliance Checking of SystemC TLM Models
|
|
|
|
Autor:
|
|
Mohamed Bawadekji, Daniel Große, Rolf Drechsler |
| Workshop: |
|
8. GMM/ITG/GI-Workshop Cyber-Physical Systems – Enabling Multi-Nature Systems (CPMNS) |
Referenz:
|
| pp. 27-32, Bremen, 2011
| Hyperlink:
|
| [Link zum Workshop]
|
» Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction
|
|
|
|
Autor:
|
|
Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
|
14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
|
| pp. 269-278, Oldenburg, 2011
| Hyperlink:
|
| [Link zum Workshop]
|
» Designing a RISC CPU in Reversible Logic
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler |
| Workshop: |
|
14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
|
| pp. 249-258, Oldenburg, 2011
| Hyperlink:
|
| [Link zum Workshop]
|
» Automatic Fault Localization for SystemC TLM Designs
|
|
|
|
Autor:
|
|
Hoang M. Le, Daniel Große, Rolf Drechsler |
| Workshop: |
|
11th International Workshop on Microprocessor Test and Verification (MTV) |
Referenz:
|
| pp. 35-40, Austin, Texas, 2010
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Towards Analyzing Functional Coverage in SystemC TLM Property Checking
|
|
|
|
Autor:
|
|
Hoang M. Le, Daniel Große, Rolf Drechsler |
| Workshop: |
|
IEEE International Workshop on High-Level Design Validation and Test (HLDVT) |
Referenz:
|
| pp. 67-74, Anaheim, 2010
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Induction-based Formal Verification of SystemC TLM Designs
|
|
|
|
Autor:
|
|
Daniel Große, Hoang M. Le, Rolf Drechsler |
| Workshop: |
|
10th International Workshop on Microprocessor Test and Verification (MTV) |
Referenz:
|
| pp. 101-106, Austin, Texas, 2009
| Hyperlink:
|
| [Link zum Workshop]
|
» Equivalence Checking of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler |
| Workshop: |
|
12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
|
| 2009
| Hyperlink:
|
| [Link zum Workshop]
|
» Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow
|
|
|
|
Autor:
|
|
Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Workshop: |
|
9th International Workshop on Microprocessor Test and Verification (MTV) |
Referenz:
|
| pp. 88-93, Austin, Texas, 2008
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Reversible Logic Synthesis with Output Permutation
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
| Workshop: |
|
International Workshop on Boolean Problems |
Referenz:
|
| Freiberg, 2008
| Hyperlink:
|
| [Link zum Workshop]
|
» Contradiction Analysis for Constraint-based Random Simulation
|
|
|
|
Autor:
|
|
Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler |
| Workshop: |
|
Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS)
|
Referenz:
|
| pp. 25-30, Dresden, 2008
| Hyperlink:
|
| [Link zum Workshop]
|
» Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking
|
|
|
|
Autor:
|
|
Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
|
11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen
zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
|
| pp. 169-178, Freiburg, 2008
| Hyperlink:
|
| [Link zum Workshop]
|
» Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits
|
|
|
|
Autor:
|
|
Andre Sülflow, Ulrich Kühne, Robert Wille, Daniel Große, Rolf Drechsler |
| Workshop: |
|
IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07) |
Referenz:
|
| pp. 31-36, Beijing, P.R.China, 2007
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Formal Verification on the Word Level using SAT-like Proof
Techniques
|
|
|
|
Autor:
|
|
Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Referenz:
|
| pp. 165-173, Erlangen, 2007
| Hyperlink:
|
| [Link zum Workshop]
|
» Exact Toffoli Network Synthesis of Reversible Logic using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Daniel Große, Xiaobo Chen, Rolf Drechsler |
| Workshop: |
|
Fifth IEEE Dallas Circuits and Systems Workshop |
Referenz:
|
| pp. 51-54, Dallas, 2006
| Hyperlink:
|
| [Link zum Workshop]
|
» Complete Formal Verification of Multi Core Embedded Systems using Bounded Model Checking
|
|
|
|
Autor:
|
|
Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Workshop: |
|
Fifth IEEE Dallas Circuits and Systems Workshop |
Referenz:
|
| pp. 147-150, Dallas, 2006
| Hyperlink:
|
| [Link zum Workshop]
|
» HW/SW Co-Verification of a RISC CPU using Bounded Model Checking
|
|
|
|
Autor:
|
|
Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
|
6th International Workshop on Microprocessor Test and Verification (MTV'05) |
Referenz:
|
| pp. 133-137, Austin, 2005
| PDF:
|
| [hier ansehen]
|
» Bounded Model Checking of Tram Control Systems
|
|
|
|
Autor:
|
|
Sebastian Kinder, Daniel Große, Jan Peleska, Rolf Drechsler |
| Workshop: |
|
TRain Workshop @ SEFM2005 |
Referenz:
|
| Koblenz, 2005
|
» Formale Verifikation des Befehlssatzes eines in SystemC modellierten Mikroprozessors
|
|
|
|
Autor:
|
|
Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
|
Entwurfsmethoden für Nanometer VLSI Design |
Referenz:
|
| pp. 308-312, Bonn, 2005
| PDF:
|
| [hier ansehen]
|
» Acceleration of SAT-based Iterative Property Checking
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Referenz:
|
| München, 2005
| PDF:
|
| [hier ansehen]
|
» Modellierung eines Mikroprozessors in SystemC
|
|
|
|
Autor:
|
|
Daniel Große, Ulrich Kühne, Christian Genz, Frank Schmiedle, Bernd Becker, Rolf Drechsler, Paul Molitor |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Referenz:
|
| München, 2005
| PDF:
|
| [hier ansehen]
|
» SyCE: An Integrated Environment for System Design in SystemC
|
|
|
|
Autor:
|
|
Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große |
| Workshop: |
|
16th IEEE International Workshop on Rapid System Prototyping (RSP) |
Referenz:
|
| pp. 258-260, Montreal, 2005
| PDF:
|
| [hier ansehen]
|
» ParSyC: An Efficient SystemC Parser
|
|
|
|
Autor:
|
|
Görschwin Fey, Daniel Große, Tim Cassens, Christian Genz, Tim Warode, Rolf Drechsler |
| Workshop: |
|
12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2004) |
Referenz:
|
| pp. 148-154, Kanazawa, 2004
| PDF:
|
| [hier ansehen]
|
» BDD-Based Verification of Scalable Designs
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Workshop: |
|
IEEE International High Level Design Validation and Test Workshop (HLDVT'2003) |
Referenz:
|
| pp. 123-128, San Francisco, 2003
| PDF:
|
| [hier ansehen]
|
» Formale Verifikation von LTL-Formeln für SystemC-Beschreibungen
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Referenz:
|
| pp. 229-238, Bremen, 2003
| PDF:
|
| [hier ansehen]
|
|
|
|
