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Home « Team « Publikationen
» Publikationen von
Daniel Tille
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BÜCHER |
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» Test Pattern Generation using Boolean Proof Engines
[Lesen Sie hier mehr!]
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Springer |
Autor:
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Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille |
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Hardcover |
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2009
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BUCHBEITRÄGE |
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ZEITSCHRIFTEN |
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» Incremental Solving Techniques for SAT-based ATPG
[Link zur Zeitschriften-Homepage]
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Autor:
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Daniel Tille, Stephan Eggersglüß, Rolf Drechsler |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 29, Number 7, pp. 1125-1130, July |
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2010
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» Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille |
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it - information technology |
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Volume 51, Number 2, pp. 102-111
Pdf download |
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2009
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» On Acceleration of SAT-based ATPG for Industrial Designs
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Daniel Tille |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 27, Number 7, pp. 1329-1333, July |
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2008
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KONFERENZEN |
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» Improving CNF Representations in SAT-based ATPG for Industrial Circuits using BDDs
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Autor:
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Daniel Tille, Stephan Eggersglüß, René Krenz-Bååth, Juergen Schloeffel, Rolf Drechsler |
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15th IEEE European Test Symposium (ETS) |
Referenz:
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| pp. 176-181, Prag, 2010
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| [Link zur Konferenz]
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| [hier ansehen]
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» Efficient Test Generation with Maximal Crosstalk-Induced Noise using Unconstrained Aggressor Excitation
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Autor:
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Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
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IEEE International Symposium on Circuits and Systems (ISCAS) |
Referenz:
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| pp. 649-652, Paris, 2010
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| [Link zur Konferenz]
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| [hier ansehen]
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» Structural Heuristics for SAT-based ATPG
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Autor:
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Daniel Tille, Stephan Eggersglüß, Hoang M. Le, Rolf Drechsler |
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17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2009) |
Referenz:
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| pp. 77-82, Florianópolis, 2009
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| [Link zur Konferenz]
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| [hier ansehen]
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» Speeding up SAT-based ATPG using Dynamic Clause Activation
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Autor:
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Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
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18th Asian Test Symposium (ATS'09) |
Referenz:
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| pp. 177-182, Taichung, 2009
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| [Link zur Konferenz]
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| [hier ansehen]
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» A Fast Untestability Proof for SAT-based ATPG
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Autor:
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Daniel Tille, Rolf Drechsler |
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12th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems |
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| pp. 38-43, Liberec, 2009
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| [Link zur Konferenz]
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| [hier ansehen]
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» Experimental Studies on SAT-based ATPG for Gate Delay Faults
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Autor:
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Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
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37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07) |
Referenz:
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| Oslo, 2007
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| [Link zur Konferenz]
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| [hier ansehen]
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WORKSHOPS |
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» A Two-Stage SAT-based ATPG Approach with Reduced Switching Activity
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Autor:
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Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
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Second International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR) 2009 |
Referenz:
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| Sevilla, Spain, 2009
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| [hier ansehen]
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| [Link zum Workshop]
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» A Fast Untestability Proof for SAT-based ATPG
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Autor:
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Daniel Tille, Rolf Drechsler |
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21. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2009 |
Referenz:
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| Bremen, 2009
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| [hier ansehen]
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| [Link zum Workshop]
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» Robust Tests for Transition Faults with Long Propagation Paths Using Boolean Satisfiability
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Autor:
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Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
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IEEE European Test Symposium (ETS), Informal Digest of Papers |
Referenz:
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| Lago Maggiore, 2008
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| [hier ansehen]
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| [Link zum Workshop]
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» Incremental SAT Instance Generation for SAT-based ATPG
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Autor:
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Daniel Tille, Rolf Drechsler |
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11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems |
Referenz:
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| pp. 68-73, Bratislava, 2008
| PDF:
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| [hier ansehen]
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| [Link zum Workshop]
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» Improved Circuit-to-CNF Transformation for SAT-based ATPG
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Autor:
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Daniel Tille, René Krenz-Bååth, Jürgen Schlöffel, Rolf Drechsler |
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20. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
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Referenz:
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| Wien, 2008
| PDF:
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| [hier ansehen]
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| [Link zum Workshop]
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» Parallelisierung von SAT-basierter Testmustergenerierung
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Autor:
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Daniel Tille, Robert Wille, Rolf Drechsler |
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21. Workshop der GI/ITG-Fachgruppe Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS 2007) |
Referenz:
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| pp. 213-217, Hamburg, 2007
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| [Link zum Workshop]
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» Studies on Integrating SAT-based ATPG in an Industrial Environment
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Autor:
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Daniel Tille, Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
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19. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
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Referenz:
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| Erlangen, 2007
| PDF:
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| [hier ansehen]
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| [Link zum Workshop]
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» Instance Generation for SAT-based ATPG
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Autor:
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Daniel Tille, Görschwin Fey, Rolf Drechsler |
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10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems |
Referenz:
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| Krakau, 2007
| PDF:
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| [hier ansehen]
| Hyperlink:
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| [Link zum Workshop]
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