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Home « Team « Publikationen
» Publikationen von
Junhao Shi
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BÜCHER |
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BUCHBEITRÄGE |
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ZEITSCHRIFTEN |
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» Synthesis of Fully Testable Circuits from BDDs
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler, Junhao Shi, Görschwin Fey |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 23, Number 3, March |
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2004
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KONFERENZEN |
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» Efficiency of Multiple-Valued Encoding in SAT-based ATPG
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Autor:
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Görschwin Fey, Junhao Shi, Rolf Drechsler |
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IEEE International Symposium on Multiple-Valued Logic (ISMVL '06) |
Referenz:
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| Singapore, 2006
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Experimental Studies on SAT-based Test Pattern Generation for Industrial Circuits
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Autor:
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Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke |
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International Conference on ASIC (ASICON 2005)
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Referenz:
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| pp. 967-970, Shanghai, 2005
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| [Link zur Konferenz]
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| [hier ansehen]
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» PASSAT: Efficient SAT-based Test Pattern Generation
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Autor:
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Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
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IEEE Annual Symposium on VLSI (ISVLSI '05) |
Referenz:
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| pp.212-217, Tampa, Florida, 2005
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| [Link zur Konferenz]
| PS:
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| [hier ansehen]
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» Bridging Fault Testability of BDD Circuits
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Autor:
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Junhao Shi, Görschwin Fey, Rolf Drechsler |
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Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005) |
Referenz:
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| pp. 188-191 Shanghai, 2005
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| [Link zur Konferenz]
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| [hier ansehen]
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» BDD Circuit Optimization for Path Delay Fault Testability
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Autor:
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Görschwin Fey, Junhao Shi, Rolf Drechsler |
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Euromicro Symposium on Digital System Design (DSD'2004) |
Referenz:
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| pp. 168-172, Rennes, 2004
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| [Link zur Konferenz]
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| [hier ansehen]
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» BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
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Autor:
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Junhao Shi, Görschwin Fey, Rolf Drechsler |
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Twelfth Asian Test Symposium (ATS03)
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Referenz:
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| p.290-293,
Xi'an, 2003
| Hyperlink:
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| [Link zur Konferenz]
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| [hier ansehen]
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» MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits
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Autor:
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Rolf Drechsler, Junhao Shi and Görschwin Fey |
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IEEE Great Lakes Symposium on VLSI (GLSV'03) |
Referenz:
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| p. 80-83, Washington, 2003
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
| PS:
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WORKSHOPS |
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» Efficiency of Multi-Valued Encoding in SAT-based ATPG
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Autor:
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Görschwin Fey, Junhao Shi , Rolf Drechsler |
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18. Workshop „Testmethoden und Zuverlässigkeit von Schaltungen und Systemen“
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Referenz:
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| Titisee, 2006
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» PASSAT: Efficient SAT-based Test Pattern Generation
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Autor:
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Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
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IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
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| Sopron, 2005
| PS:
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| [hier ansehen]
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» Experimental Studies on Test Pattern Generation for BDD Circuits
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Autor:
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Junhao Shi, Görschwin Fey, Rolf Drechsler |
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International Workshop on Boolean Problems (IWSBP) |
Referenz:
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| pp. 71-76, Freiberg, 2004
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| [hier ansehen]
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» Random Pattern Testability of Circuits Derived from BDDs
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Autor:
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Junhao Shi, Göschwin Fey and Rolf Drechsler |
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4th Workshop on RTL and High Level Testing(WRTLT'03) |
Referenz:
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| p.70-78,
Xi'an, 2003
| PDF:
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| [hier ansehen]
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» BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
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Autor:
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Junhao Shi, Görschwin Fey and Rolf Drechsler |
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IEEE European Test Workshop (ETW'03) |
Referenz:
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| pp. 109-110, Maastricht, 2003
| PDF:
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| [hier ansehen]
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» BDD Circuit Optimization for Path Delay Fault-Testability
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Autor:
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Görschwin Fey, Junhao Shi, Rolf Drechsler |
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15th ITG/GMM/GI Workshop Test methods and Reliability of Circuits and Systems |
Referenz:
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| Timmendorfer Strand, 2003
| PS:
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| [hier ansehen]
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