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» Publikationen von Robert Wille


BÜCHER

» Automatic Methods for the Refinement of System Models
[Lesen Sie hier mehr!]



Verlag:


Springer International Publishing
Autor:

Julia Seiter, Robert Wille, Rolf Drechsler
Format:
Taschenbuch
Erscheinungsjahr:


2016



» Languages, Design Methods, and Tools for Electronic System Design
[Lesen Sie hier mehr!]



Verlag:


Springer International Publishing (Verlag)
Autor:

Rolf Drechsler, Robert Wille (Hrsg.)
Format:
Buch | Hardcover
Erscheinungsjahr:


2016



» Synthese- und Optimierungsverfahren für zukünftige Computerparadigmen
[Lesen Sie hier mehr!]



Verlag:


Shaker Verlag
Autor:

Robert Wille, Oliver Keszöcze, Rolf Drechsler (Hrsg.)
Format:
gebunden
Erscheinungsjahr:


2015



» Auf dem Weg zum Quantencomputer - Entwurf reversibler Logik
[Lesen Sie hier mehr!]



Verlag:


Shaker Verlag
Autor:

Rolf Drechsler, Mathias Soeken, Robert Wille (Hrsg.)
Format:
gebunden
Erscheinungsjahr:


2012



» Towards a Design Flow for Reversible Logic
[Lesen Sie hier mehr!]



Verlag:


Springer
Autor:

Robert Wille, Rolf Drechsler
Format:
Gebunden
Erscheinungsjahr:


2010




BUCHBEITRÄGE
» Exploiting Electronic Design Automation for Checking Legal Regulations: A Vision
Großformat des Buches: Languages, Design Methods, and Tools for Electronic System Design Autor:

Oliver Keszöcze, Robert Wille

Herausgeber:Frank Oppenheimer, Julio Luis Medina Pasaje
Buchtitel:Languages, Design Methods, and Tools for Electronic System Design
Verlag:Springer
Seiten:101—112
Erscheinungsjahr:2016
Format:gebunden

» Formal Specification Level
Großformat des Buches: Models, Methods, and Tools for Complex Chip Design: Selected Contributions from FDL 2012 Autor:

Rolf Drechsler, Mathias Soeken, Robert Wille

Herausgeber:Jan Haase
Buchtitel:Models, Methods, and Tools for Complex Chip Design: Selected Contributions from FDL 2012
Verlag:Springer
Seiten:37-52
Erscheinungsjahr:2014
Format:Hardcover

» SyReC: A Programming Language for Synthesis of Reversible Circuits
Großformat des Buches: System Specification and Design Languages: Selected Contributions from FDL 2010 Autor:

Robert Wille, Sebastian Offermann, Rolf Drechsler

Herausgeber:Tom J. Kazmierski, Adam Morawiec
Buchtitel:System Specification and Design Languages: Selected Contributions from FDL 2010
Verlag:Springer
Seiten:207-222
Erscheinungsjahr:2012
Format:Hardcover

» SMT-based Stimuli Generation in the SystemC Verification Library
Großformat des Buches: Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s: Selected Contributions on Specification, Design, and Verification from FDL 2009 Autor:

Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler

Herausgeber:Dominique Borrione
Buchtitel:Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s: Selected Contributions on Specification, Design, and Verification from FDL 2009
Verlag:Springer
Seiten:227-244
Erscheinungsjahr:2010
Format:Hardcover

» Ein Entwurfsablauf für Reversible Schaltkreise
Großformat des Buches: Ausgezeichnete Informatikdissertationen 2009 Autor:

Robert Wille

Herausgeber:S. Hölldobler et al.
Buchtitel:Ausgezeichnete Informatikdissertationen 2009
Verlag:GI
Seiten:291-300
Erscheinungsjahr:2010
Format:Paperback

» Synthesis of Boolean Functions in Reversible Logic
Großformat des Buches: Progress in Applications of Boolean Functions (Synthesis Lectures on Digital Circuits and Systems) Autor:

Robert Wille, Rolf Drechsler

Herausgeber:Tsutomu Sasao, Jon T. Butler, Mitchell Thornton
Buchtitel:Progress in Applications of Boolean Functions (Synthesis Lectures on Digital Circuits and Systems)
Verlag:Morgan and Claypool Publishers
Seiten:75-92
Erscheinungsjahr:2010
Format:Paperback

» Debugging Contradictory Constraints in Constraint-based Random Simulation
Großformat des Buches: Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL'08 Autor:

Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler

Herausgeber:Martin Radetzki
Buchtitel:Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL'08
Verlag:Springer
Seiten:273-290
Erscheinungsjahr:2009
Format:gebunden

» SWORD: A SAT like Prover Using Word Level Information
Großformat des Buches: VLSI-SoC: Advanced Topics on Systems on a Chip:
A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip Autor:

Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler

Herausgeber:Ricardo Reis, Vincent Mooney, Paul Hasler
Buchtitel:VLSI-SoC: Advanced Topics on Systems on a Chip: A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip
Verlag:Springer
Seiten:175-192
Erscheinungsjahr:2009
Format:Hardcover



ZEITSCHRIFTEN

» Synthesis of optical circuits using binary decision diagrams
[Link zur Zeitschriften-Homepage]




Autor:

Arighna Deb, Robert Wille, Oliver Keszöcze, Saeideh Shirinzadeh, Rolf Drechsler
Zeitschrift:
Integration, the VLSI Journal
Details:
Volume 59, September 2017, Pages 42–51
Jahr:


2017




» Towards a Verification Flow Across Abstraction Levels:
Verifying Implementations Against Their Formal Specification

[Link zur Zeitschriften-Homepage]




Autor:

Pablo Gonzalez-de-Aledo, Nils Przigoda, Robert Wille, Rolf Drechsler, Pablo Sanchez
Zeitschrift:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
36(3):475-488, DOI: 10.1109/TCAD.2016.2611494
Jahr:


2017




» Verifying the Structure and Behavior in UML/OCL Models Using Satisfiability Solvers
[Link zur Zeitschriften-Homepage]




Autor:

Nils Przigoda, Mathias Soeken, Robert Wille, Rolf Drechsler
Zeitschrift:
IET Cyber-Physical Systems: Theory & Applications
Details:
Volume 1, Issue 1, December 2016, pp. 49-59
DOI: 10.1049/iet-cps.2016.0022
Jahr:


2016




» Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits
[Link zur Zeitschriften-Homepage]




Autor:

Arighna Deb, Robert Wille, Oliver Keszöcze, Stefan Hillmich, Rolf Drechsler
Zeitschrift:
Journal on Emerging Technologies in Computing Systems (JETC)
Details:
Volume 13, Issue 1
Jahr:


2016




» Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability
[Link zur Zeitschriften-Homepage]




Autor:

Arighna Deb, Debesh K. Das, Hafizur Rahaman, Robert Wille, Rolf Drechsler, Bhargab B. Bhattacharya
Zeitschrift:
Journal on Emerging Technologies in Computing Systems (JETC)
Details:
Volume 12 Issue 4, Article No. 34
Jahr:


2016




» Analyzing Inconsistencies in UML/OCL Models
[Link zur Zeitschriften-Homepage]




Autor:

Nils Przigoda, Robert Wille, Rolf Drechsler
Zeitschrift:
Journal of Circuits, Systems and Computers
Details:
Volume 25, Issue 03, March 2016
DOI: 10.1142/S0218126616400211
Jahr:


2016




» SyReC: A Hardware Description Language for the Specification and Synthesis of Reversible Circuits
[Link zur Zeitschriften-Homepage]




Autor:

Robert Wille, Eleonora Schonborn, Mathias Soeken, Rolf Drechsler
Zeitschrift:
INTEGRATION, the VLSI Journal
Details:
53(3):39-53
Jahr:


2016




» Scalable One-Pass Synthesis for Digital Microfluidic Biochips
[Link zur Zeitschriften-Homepage]




Autor:

Robert Wille, Oliver Keszöcze, Tobias Boehnisch, Alexander Kroker, Rolf Drechsler
Zeitschrift:
IEEE Design & Test of Computers
Details:
Volume 32, Issue 66, Pages 41—50
Jahr:


2015




» QMDDs: Efficient Quantum Function Representation and Manipulation
[Link zur Zeitschriften-Homepage]




Autor:

Philipp Niemann, Robert Wille, D. Michael Miller, Mitchell A. Thornton, Rolf Drechsler
Zeitschrift:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 35, Number 1, pp. 86-99
DOI: 10.1109/TCAD.2015.2459034
Jahr:


2016




» Embedding of Large Boolean Functions for Reversible Logic
[Link zur Zeitschriften-Homepage]




Autor:

Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler
Zeitschrift:
Journal on Emerging Technologies in Computing Systems (JETC)
Details:
Volume 12, Issue 4
Preprint available at arXiv 1408.3586
Jahr:


2015




» Exact Reordering of Circuit Lines for Nearest Neighbor Quantum Architectures
[Link zur Zeitschriften-Homepage]




Autor:

Robert Wille, Aaron Lye, Rolf Drechsler
Zeitschrift:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 33, Number 12, pp. 1818-1831
DOI: 10.1109/TCAD.2014.2356463
Jahr:


2014




» Special Issue on Reversible Computation
[Link zur Zeitschriften-Homepage]




Autor:

Robert Wille, Rolf Drechsler, Mehdi . B. Tahoori (editors)
Zeitschrift:
Journal on Emerging Technologies in Computing Systems (JETC)
Details:
Volume 11, Number 2
Jahr:


2014




» Considering Nearest Neighbor Constraints of Quantum Circuits at the Reversible Circuit Level




Autor:

Robert Wille, Aaron Lye, Rolf Drechsler
Zeitschrift:
Quantum Information Processing
Details:
DOI: http://dx.doi.org/10.1007/s11128-013-0642-5
Jahr:


2013




» Trading Off Circuit Lines and Gate Costs in the Synthesis of Reversible Logic
[Link zur Zeitschriften-Homepage]




Autor:

Robert Wille, Mathias Soeken, D. Michael Miller, Rolf Drechsler
Zeitschrift:
INTEGRATION, the VLSI Journal
Details:
Volume 47, Number 2, pp. 284-294, DOI: 10.1016/j.vlsi.2013.08.002
Jahr:


2014




» Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits
[Link zur Zeitschriften-Homepage]




Autor:

Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler
Zeitschrift:
Multiple-Valued Logic and Soft Computing
Details:
Volume 21, Number 5-6, 2013, pp. 627-640
Jahr:


2013




» RevKit: An Open Source Toolkit for the Design of Reversible Circuits
[Link zur Zeitschriften-Homepage]




Autor:

Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Zeitschrift:
Reversible Computation 2011 (Series: Lecture Notes in Computer Science)
Details:
Volume 7165, Third International Workshop, RC 2011, Revised Papers, pp. 64-76
Jahr:


2012




» Special Issue on Reversible Computation
[Link zur Zeitschriften-Homepage]




Autor:

Rolf Drechsler, Irek Ulidowski, Robert Wille (editors)
Zeitschrift:
Multiple-Valued Logic and Soft Computing
Details:
Volume 18, Number 1
Jahr:


2012




» RevKit: A Toolkit for Reversible Circuit Design
[Link zur Zeitschriften-Homepage]




Autor:

Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Zeitschrift:
Multiple-Valued Logic and Soft Computing
Details:
Volume 18, Number 1, pp. 55-65
Jahr:


2012




» Synthesis of Quantum Circuits for Linear Nearest Neighbor Architectures
[Link zur Zeitschriften-Homepage]




Autor:

Mehdi Saeedi, Robert Wille, Rolf Drechsler
Zeitschrift:
Quantum Information Processing
Details:
Volume 10, Number 3, pp. 355-377
DOI: 10.1007/s11128-010-0201-2
Jahr:


2011




» Debugging Reversible Circuits
[Link zur Zeitschriften-Homepage]




Autor:

Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
Zeitschrift:
INTEGRATION, the VLSI Journal
Details:
Volume 44, Number 1, pp. 51-61, January
DOI: 10.1016/j.vlsi.2010.08.002
Jahr:


2011




» BDD-Based Synthesis of Reversible Logic
[Link zur Zeitschriften-Homepage]




Autor:

Robert Wille, Rolf Drechsler
Zeitschrift:
International Journal of Applied Metaheuristic Computing (IJAMC)
Details:
Volume 1, Number 4, pp. 25-41
Jahr:


2010




» Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic
[Link zur Zeitschriften-Homepage]




Autor:

Robert Wille, Rolf Drechsler
Zeitschrift:
Electronic Notes in Theoretical Computer Science
Details:
Volume 253, Number 6, pp. 57-70
DOI: 10.1016/j.entcs.2010.02.006
Jahr:


2010




» Synthese reversibler Logik
[Link zur Zeitschriften-Homepage]




Autor:

Robert Wille, Rolf Drechsler
Zeitschrift:
it-Information Technology
Details:
Volume 52, Number 1, pp. 30-38
PDF Download
Jahr:


2010




» Exact Synthesis of Elementary Quantum Gate Circuits
[Link zur Zeitschriften-Homepage]




Autor:

Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Zeitschrift:
Multiple-Valued Logic and Soft Computing
Details:
Volume 15, Number 4, pp. 283-300
Jahr:


2009




» Exact Multiple Control Toffoli Network Synthesis with SAT Techniques
[Link zur Zeitschriften-Homepage]




Autor:

Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Zeitschrift:
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details:
Volume 28, Number 5, pp. 703-715, May
DOI: 10.1109/TCAD.2009.2017215
Jahr:


2009




» Building Free Binary Decision Diagrams Using SAT Solvers
[Link zur Zeitschriften-Homepage]




Autor:

Robert Wille, Görschwin Fey, Rolf Drechsler
Zeitschrift:
Facta Universitatis, Series: Electronics and Energetics
Details:
Volume 20, Number 3, pp. 381-394,
Jahr:


2007





KONFERENZEN


» Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips




Autor:

Oliver Keszöcze, Mohamed Ibrahim, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
Konferenz:
International Conference on VLSI Design (VLSID)
Referenz:

Pune, Indien, 2018
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» More than true or false: Native Support of Irregular Values in the Automatic Validation & Verification of UML/OCL Models




Autor:

Nils Przigoda, Philipp Niemann, Judith Peters, Frank Hilken, Robert Wille, Rolf Drechsler
Konferenz:
15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Referenz:

Vienna, Austria, 2017
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» BioViz: An Interactive Visualization Engine for Digital Microfluidic Biochips




Autor:

Jannis Stoppe, Oliver Keszöcze, Maximilian Luenert, Robert Wille, Rolf Drechsler
Konferenz:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Referenz:

Bochum, Germany, 2017
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Towards VHDL-based Design of Reversible Circuits




Autor:

Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Konferenz:
Reversible Computation
Referenz:

Kolkata, India, 2017
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Efficient Construction of QMDDs for Irreversible, Reversible and Quantum Functions




Autor:

Philipp Niemann, Alwin Zulehner, Robert Wille, Rolf Drechsler
Konferenz:
Reversible Computation
Referenz:

pp. 214-231, Kolkata, India, 2017
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» OR-Inverter Graphs for the Synthesis of Optical Circuits




Autor:

Arighna Deb, Robert Wille, Rolf Drechsler
Konferenz:
47th International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

Novi Sad, Serbia, 2017
Hyperlink:

[Link zur Konferenz]


» Extensions to the Reversible Hardware Description Language SyReC




Autor:

Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Konferenz:
47th International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

Novi Sad, Serbia, 2017
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Enhancing Robustness of Sequential Circuits Using Application-specific Knowledge and Formal Methods




Autor:

Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler
Konferenz:
22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Referenz:

Chiba/Tokyo, Japan, 2017
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Exact Routing for Micro-Electrode-Dot-Array Digital Microfluidic Biochips




Autor:

Oliver Keszöcze, Zipeng Li, Andreas Grimmer, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
Konferenz:
22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Referenz:

Chiba/Tokyo, Japan, 2017
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Clocks vs. Instants Relations: Verifying CCSL Time Constraints in UML/MARTE Models




Autor:

Judith Peters, Nils Przigoda, Robert Wille, Rolf Drechsler
Konferenz:
14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Referenz:

Indian Institute of Technology, Kanpur, India, 2016
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Frame Conditions in Symbolic Representations of UML/OCL Models




Autor:

Nils Przigoda, Jonas Gomes Filho, Philipp Niemann, Robert Wille, Rolf Drechsler
Konferenz:
14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Referenz:

Indian Institute of Technology, Kanpur, India, 2016
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Generating and Checking Control Logic in the HDL-based Design of Reversible Circuits




Autor:

Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
Konferenz:
International Symposium on Electronic System Design (ISED)
Referenz:

Patna, Indien, 2016
Hyperlink:

[Link zur Konferenz]


» An Improved Gate Library for Logic Synthesis of Optical Circuits




Autor:

Shuchisman Burman, Kamalika Datta, Robert Wille, Indranil Sengupta, Rolf Drechsler
Konferenz:
International Symposium on Electronic System Design (ISED)
Referenz:

Patna, Indien, 2016
Hyperlink:

[Link zur Konferenz]


» Towards a Model-Based Verification Methodology for Complex Swarm Systems




Autor:

Jonas Gomes Filho, Nils Przigoda, Robert Wille, Rolf Drechsler
Konferenz:
International Symposium on Electronic System Design (ISED)
Referenz:

Patna, Indien, 2016
Hyperlink:

[Link zur Konferenz]


» Ground Setting Properties for an Efficient Translation of OCL in SMT-based Model Finding




Autor:

Nils Przigoda, Robert Wille, Rolf Drechsler
Konferenz:
ACM/IEEE 19th International Conference on Model Driven Engineering Languages and Systems (MoDELS)
Referenz:

Saint Malo, Brittany, France, 2016
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs




Autor:

Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
Konferenz:
Reversible Computation
Referenz:

Bologna, Italy, 2016
Hyperlink:

[Link zur Konferenz]


» Towards a Catalog of Structural and Behavioral Verification Tasks for UML/OCL Models




Autor:

Frank Hilken, Philipp Niemann, Martin Gogolla, Robert Wille
Konferenz:
Modellierung
Referenz:

Karlsruhe, Germany, 2016
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Fault Detection in Parity Preserving Reversible Circuits




Autor:

Nils Przigoda, Gerhard Dueck, Robert Wille, Rolf Drechsler
Konferenz:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

Sapporo, Japan, 2016
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Re-writing HDL Descriptions for Line-aware Synthesis of Reversible Circuits




Autor:

Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Konferenz:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

Sapporo, Japan, 2016
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation




Autor:

Laxmidhar Biswal, Chandan Bandyopadhyay, Anupam Chattopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Konferenz:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

Sapporo, Japan, 2016
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Logic Synthesis for Quantum State Generation




Autor:

Philipp Niemann, Rhitam Datta, Robert Wille
Konferenz:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

Sapporo, Japan, 2016
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits




Autor:

Md. Mazder Rahman, Gerhard W. Dueck, Anupam Chattopadhyay, Robert Wille
Konferenz:
46th International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

Sapporo, Japan, 2016
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Synthesis of Approximate Coders for On-chip Interconnects Using Reversible Logic




Autor:

Robert Wille, Oliver Keszöcze, Stefan Hillmich, Marcel Walter, Alberto Garcia-Ortiz
Konferenz:
Design, Automation and Test in Europe (DATE)
Referenz:

Dresden, 2016
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Exploiting Inherent Characteristics of Reversible Circuits for Faster Combinational Equivalence Checking




Autor:

Luca Amaru, Pierre-Emmanuel Gaillardon, Robert Wille, Giovanni De Micheli
Konferenz:
Design, Automation and Test in Europe (DATE)
Referenz:

Dresden, 2016
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Look-ahead Schemes for Nearest Neighbor Optimization of 1D and 2D Quantum Circuits




Autor:

Robert Wille, Oliver Keszöcze, Marcel Walter, Patrick Rohrs, Anupam Chattopadhyay, Rolf Drechsler
Konferenz:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Referenz:

Macao, China, 2016
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library




Autor:

Laxmidhar Biswal, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Konferenz:
International Conference on VLSI Design (VLSI Design)
Referenz:

Kolkata, India, 2016
Hyperlink:

[Link zur Konferenz]


» Reversible Computation: An Alternative Computation Paradigm for Low Power Applications




Autor:

Rolf Drechsler, Robert Wille
Konferenz:
International Green and Sustainable Computing Conference (IGSC)
Referenz:

Las Vegas, USA, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Checking Concurrent Behavior in UML/OCL Models




Autor:

Nils Przigoda, Christoph Hilken, Robert Wille, Jan Peleska, Rolf Drechsler
Konferenz:
ACM/IEEE 18th International Conference on Model Driven Engineering Languages and Systems (MoDELS)
Referenz:

Ottawa, Kanada, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Extracting Frame Conditions from Operation Contracts




Autor:

Philipp Niemann, Frank Hilken, Martin Gogolla, Robert Wille
Konferenz:
ACM/IEEE 18th International Conference on Model Driven Engineering Languages and Systems (MoDELS)
Referenz:

pp. 266-275, Ottawa, Canada, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» A General and Exact Routing Methodology for Digital Microfluidic Biochips




Autor:

Oliver Keszöcze, Robert Wille, Krishnendu Chakrabarty Rolf Drechsler
Konferenz:
International Conference on Computer Aided Design (ICCAD)
Referenz:

Austin, USA, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Formal Methods for Emerging Technologies




Autor:

Robert Wille, Rolf Drechsler
Konferenz:
International Conference on Computer Aided Design (ICCAD)
Referenz:

Austin, USA, 2015
Hyperlink:

[Link zur Konferenz]


» Leveraging the Analysis for Invariant Independence in Formal System Models




Autor:

Nils Przigoda, Robert Wille, Rolf Drechsler
Konferenz:
Euromicro Conference on Digital System Design (DSD)
Referenz:

Funchal, Madeira, Portugal, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Verification-driven Design Across Abstraction Levels - A Case Study




Autor:

Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, Rolf Drechsler
Konferenz:
Euromicro Conference on Digital System Design (DSD)
Referenz:

Funchal, Madeira, Portugal, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Envisioning Self-Verification of Electronic Systems




Autor:

Rolf Drechsler, Martin Fränzle, Robert Wille
Konferenz:
Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
Referenz:

Bremen, Germany, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Towards Line-aware Realizations of Expressions for HDL-based Synthesis of Reversible Circuits




Autor:

Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Konferenz:
Reversible Computation
Referenz:

Grenoble, France, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Synthesis of Quantum Circuits for Dedicated Physical Machine Descriptions




Autor:

Philipp Niemann, Saikat Basu, Amlan Chakrabarti, Niraj K. Jha, Robert Wille
Konferenz:
Reversible Computation
Referenz:

pp. 248-264, Grenoble, France, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Towards a Cost Metric for Nearest Neighbor Constraints in Reversible Circuits




Autor:

Abhoy Kole, Kamalika Datta, Indranil Sengupta, Robert Wille
Konferenz:
Reversible Computation
Referenz:

Grenoble, France, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» From UML/OCL to Base Models: Transformation Concepts for Generic Validation and Verification




Autor:

Frank Hilken, Philipp Niemann, Martin Gogolla, Robert Wille
Konferenz:
International Conference on Model Transformation (ICMT)
Referenz:

pp. 149-165, L’Aquila, Italy, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Contradiction Analysis for Inconsistent Formal Models




Autor:

Nils Przigoda, Robert Wille, Rolf Drechsler
Konferenz:
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15)
Referenz:

Belgrade, Serbia, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» A Generic Representation of CCSL Time Constraints for UML/MARTE Models




Autor:

Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler
Konferenz:
Design Automation Conference (DAC)
Referenz:

San Francisco, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization




Autor:

Arighna Deb, Robert Wille, Rolf Drechsler, Debesh Das
Konferenz:
45th International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

Waterloo, Canada, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» An Examination of the NCV-v1 Quantum Library Based on Minimal Circuits




Autor:

Arman Allahyari-Abhari, Robert Wille, Rolf Drechsler
Konferenz:
45th International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

Waterloo, Canada, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Automated Feature Localization for Dynamically Generated SystemC Designs




Autor:

Jannis Stoppe, Robert Wille, Rolf Drechsler
Konferenz:
Design, Automation and Test in Europe (DATE'15)
Referenz:

Grenoble, France, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Assisted Generation of Frame Conditions for Formal Models




Autor:

Philipp Niemann, Frank Hilken, Martin Gogolla, Robert Wille
Konferenz:
Design, Automation and Test in Europe (DATE'15)
Referenz:

pp. 309-312, Grenoble, France, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» A Unified Formulation of Behavioral Semantics for SysML Models




Autor:

Christoph Hilken, Jan Peleska, Robert Wille
Konferenz:
International Conference on Model-Driven Engineering and Software Development
Referenz:

Angers, France, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» BDD-based Synthesis for All-optical Mach-Zehnder Interferometer Circuits




Autor:

Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Konferenz:
International Conference on VLSI Design (VLSI Design)
Referenz:

Bengaluru, India, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Determining the Minimal Number of SWAP Gates for Multi-dimensional Nearest Neighbor Quantum Circuits




Autor:

Aaron Lye, Robert Wille, Rolf Drechsler
Konferenz:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Referenz:

Chiba/Tokyo, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Reverse BDD-based Synthesis for Splitter-free Optical Circuits




Autor:

Robert Wille, Oliver Keszöcze, Clemens Hopfmuller, Rolf Drechsler
Konferenz:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Referenz:

Chiba/Tokyo, 2015
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Exact Routing for Digital Microfluidic Biochips with Temporary Blockages




Autor:

Oliver Keszöcze, Robert Wille, Rolf Drechsler
Konferenz:
International Conference on Computer Aided Design (ICCAD)
Referenz:

San Jose, 2014
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Automated and Quality-driven Requirements Engineering




Autor:

Rolf Drechsler, Mathias Soeken, Robert Wille,
Konferenz:
International Conference on Computer Aided Design (ICCAD)
Referenz:

San Jose, 2014
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Automatic Refinement Checking for Formal System Models




Autor:

Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
Konferenz:
Forum on specification & Design Languages (FDL)
Referenz:

Munich, Germany, 2014
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Verifying Consistency between Activity Diagrams and Their Corresponding OCL Contracts




Autor:

Christoph Hilken, Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
Konferenz:
Forum on specification & Design Languages (FDL)
Referenz:

Munich, Germany, 2014
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» (Semi-)Automatic Translation of Legal Regulations to Formal Representations: Expanding the Horizon of EDA Applications




Autor:

Oliver Keszöcze, Betina Keiner, Matthias Richter, Gottfried Antpöhler, Robert Wille
Konferenz:
Special Session at the Forum on specification & Design Languages (FDL'14)
Referenz:

Munich, Germany, 2014
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Improving Coverage of Simulation-based Verification by Dedicated Stimuli Generation




Autor:

Shuo Yang, Robert Wille, Rolf Drechsler
Konferenz:
Euromicro Conference on Digital System Design (DSD)
Referenz:

pp. 599-606, Verona, Italy, 2014
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Determining Cases of Scenarios to Improve Coverage in Simulation-based Verication




Autor:

Shuo Yang, Robert Wille, Rolf Drechsler
Konferenz:
Symposium on Integrated Circuits and System Design (SBCCI)
Referenz:

Aracaju, Brazil, 2014
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Validating SystemC Implementations Against Their Formal Specifications




Autor:

Jannis Stoppe, Robert Wille, Rolf Drechsler
Konferenz:
Symposium on Integrated Circuits and System Design (SBCCI)
Referenz:

Aracaju, Brazil, 2014
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Filmstripping and Unrolling: A Comparison of Verification Approaches for UML and OCL Behavioral Models




Autor:

Frank Hilken, Philipp Niemann, Martin Gogolla, Robert Wille
Konferenz:
8th International Conference on Tests & Proofs (TAP)
Referenz:

pp. 99-116, York, 2014
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Generating SystemC Implementations for Clock Constraints specified in UML/MARTE CCSL




Autor:

Judith Peters, Robert Wille, Rolf Drechsler
Konferenz:
International Conference on Engineering of Complex Computer Systems (ICECCS)
Referenz:

pp. 116-125, Tianjin, China, 2014
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Exact One-pass Synthesis of Digital Microfluidic Biochips




Autor:

Oliver Keszöcze, Robert Wille, Tsung-Yi Ho, Rolf Drechsler
Konferenz:
Design Automation Conference (DAC)
Referenz:

San Francisco, 2014
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Equivalence Checking in Multi-level Quantum Systems




Autor:

Philipp Niemann, Robert Wille, Rolf Drechsler
Konferenz:
Reversible Computation
Referenz:

pp. 201-215, Kyoto, Japan, 2014
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» RevVis: Visualization of Structures and Properties in Reversible Circuits




Autor:

Robert Wille, Jannis Stoppe, Eleonora Schönborn, Kamalika Datta, Rolf Drechsler
Konferenz:
Reversible Computation
Referenz:

Kyoto, Japan, 2014
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Optimizing DD-based Synthesis of Reversible Circuits using Negative Control Lines




Autor:

Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Konferenz:
IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Referenz:

pp. 129-134, Warschau, Polen, 2014
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Optimal SWAP Gate Insertion for Nearest Neighbor Quantum Circuits




Autor:

Robert Wille, Aaron Lye, Rolf Drechsler
Konferenz:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Referenz:

pp. 489-494, Singapore, 2014
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Efficient Synthesis of Quantum Circuits Implementing Clifford Group Operations




Autor:

Philipp Niemann, Robert Wille, Rolf Drechsler
Konferenz:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Referenz:

pp. 483-488, Singapore, 2014
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Improved SAT-based ATPG: More Constraints, Better Compaction




Autor:

Stephan Eggersglüß, Robert Wille, Rolf Drechsler
Konferenz:
IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
Referenz:

pp. 85-90, San Jose, USA, 2013
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» A Compact and Efficient SAT Encoding for Quantum Circuits




Autor:

Robert Wille, Nils Przigoda, Rolf Drechsler
Konferenz:
IEEE Africon
Referenz:

Mauritius, 2013
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Exploiting Reversibility in the Complete Simulation of Reversible Circuits




Autor:

Robert Wille, Simon Stelter, Rolf Drechsler
Konferenz:
IEEE Africon
Referenz:

Mauritius, 2013
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Cone of Influence Analysis at the Electronic System Level Using Machine Learning




Autor:

Jannis Stoppe, Robert Wille, Rolf Drechsler
Konferenz:
Euromicro Conference on Digital System Design (DSD)
Referenz:

Santander, Spain, 2013
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Minimal Stimuli Generation in Simulation-based Verification




Autor:

Shuo Yang, Robert Wille, Daniel Große and Rolf Drechsler
Konferenz:
Euromicro Conference on Digital System Design (DSD)
Referenz:

Santander, Spain, 2013
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» The SyReC Hardware Description Language: Enabling Scalable Synthesis of Reversible Circuits




Autor:

Robert Wille, Rolf Drechsler
Konferenz:
International Midwest Symposium on Circuits and Systems (MWSCAS)
Referenz:

Columbus, USA, 2013
Hyperlink:

[Link zur Konferenz]


» Data Extraction from SystemC Designs using Debug Symbols and the SystemC API




Autor:

Jannis Stoppe, Robert Wille, Rolf Drechsler
Konferenz:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Referenz:

Natal, Brazil, 2013
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» On the “Q” in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-structure




Autor:

Philipp Niemann, Robert Wille, Rolf Drechsler
Konferenz:
Reversible Computation
Referenz:

pp. 125-140, Victoria, Canada, 2013
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Exploiting Negative Control Lines in the Optimization of Reversible Circuits




Autor:

Kamalika Datta, Gaurav Rathi, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Konferenz:
Reversible Computation
Referenz:

pp. 209-220, Victoria, Canada, 2013
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure




Autor:

Arighna Deb, Debesh Kumar Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler
Konferenz:
Reversible Computation
Referenz:

pp. 182-195, Victoria, Canada, 2013
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Reducing the Depth of Quantum Circuits Using Additional Lines




Autor:

Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler
Konferenz:
Reversible Computation
Referenz:

pp. 221-233, Victoria, Canada, 2013
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits




Autor:

Robert Wille, Hongyan Zhang, Rolf Drechsler
Konferenz:
43rd International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

pp. 29-34, Toyama, 2013
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Exact Template Matching Using Boolean Satisfiability




Autor:

Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler
Konferenz:
43rd International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

pp. 328-333, Toyama, Japan, 2013
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Determining Relevant Model Elements for the Verification of UML/OCL Specifications




Autor:

Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler
Konferenz:
Design, Automation and Test in Europe (DATE)
Referenz:

pp. 1189-1192, Grenoble, France, 2013
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Towards a Generic Verification Methodology for System Models




Autor:

Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler
Konferenz:
Design, Automation and Test in Europe (DATE)
Referenz:

pp. 1193-1196, Grenoble, France, 2013
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Improving the Mapping of Reversible Circuits to Quantum Circuits Using Multiple Target Lines




Autor:

Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler
Konferenz:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Referenz:

pp. 145-150. Yokohama, Japan, 2013
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Towards Dialog Systems for Assisted Natural Language Processing in the Design of Embedded Systems




Autor:

Rolf Drechsler, Mathias Soeken, Robert Wille
Konferenz:
IEEE Design and Test Symposium 2012 (IDT)
Referenz:

Doha, 2012
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Synthesis of Reversible Circuits Using Decision Diagrams




Autor:

Rolf Drechsler, Robert Wille
Konferenz:
International Symposium on Electronic System Design (ISED)
Referenz:

pp. 1-5, Kolkata, WB, India, 2012
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Completeness-Driven Development




Autor:

Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille
Konferenz:
International Conference on Graph Transformation
Referenz:

pp. 38-50, Bremen, 2012
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Formal Specification Level: Towards Verification-driven Design Based on Natural Language Processing




Autor:

Rolf Drechsler, Mathias Soeken, Robert Wille
Konferenz:
Forum on specification & Design Languages (FDL)
Referenz:

pp. 53-58, Vienna, Austria, 2012
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Circuit Line Minimization in the HDL-based Synthesis of Reversible Logic




Autor:

Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler
Konferenz:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Referenz:

pp. 213-218, Amherst, USA, 2012
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Coverage-driven Stimuli Generation




Autor:

Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler
Konferenz:
15th Euromicro Conference on Digital System Design (DSD)
Referenz:

Izmir, Turkey, 2012
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology




Autor:

Rolf Drechsler, Robert Wille
Konferenz:
International Symposium on VLSI Design and Test (VDAT)
Referenz:

Shibpur, India, 2012
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Assisted Behavior Driven Development Using Natural Language Processing




Autor:

Mathias Soeken, Robert Wille, Rolf Drechsler
Konferenz:
50th International Conference on Objects, Models, Components, Patterns (TOOLS)
Referenz:

pp. 269-287, Prague, Czech Republic, 2012
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Realizing Reversible Circuits Using a New Class of Quantum Gates




Autor:

Zahra Sasanian, Robert Wille, Michael Miller
Konferenz:
Design Automation Conference (DAC)
Referenz:

San Francisco, 2012
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits




Autor:

Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler
Konferenz:
42nd International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

pp. 173-178, Victoria, Canada, 2012
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» A Synthesis Flow for Sequential Reversible Circuits




Autor:

Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler
Konferenz:
42nd International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

pp. 299-304, Victoria, Canada, 2012
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines




Autor:

Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler
Konferenz:
42nd International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

pp. 69-74, Victoria, Canada, 2012
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis




Autor:

Robert Wille, Rolf Drechsler, Christof Oswald, Alberto Garcia-Ortiz
Konferenz:
Design, Automation and Test in Europe (DATE)
Referenz:

Dresden, 2012
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Eliminating Invariants in UML/OCL Models




Autor:

Mathias Soeken, Robert Wille, Rolf Drechsler
Konferenz:
Design, Automation and Test in Europe (DATE)
Referenz:

pp. 1142-1145, Dresden, 2012
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Debugging of Inconsistent UML/OCL Models




Autor:

Robert Wille, Mathias Soeken, Rolf Drechsler
Konferenz:
Design, Automation and Test in Europe (DATE)
Referenz:

pp. 1078-1083, Dresden, 2012
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Synthesis of Reversible Circuits with Minimal Lines for Large Functions




Autor:

Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler
Konferenz:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Referenz:

pp. 85-92, Sydney, 2012
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Improved Fault Diagnosis for Reversible Circuits




Autor:

Hongyan Zhang, Robert Wille, Rolf Drechsler
Konferenz:
Asian Test Symposium (ATS)
Referenz:

New Delhi, 2011
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Efficient Realization of Control Logic in Reversible Circuits




Autor:

Sebastian Offermann, Robert Wille, Rolf Drechsler
Konferenz:
Forum on specification & Design Languages (FDL)
Referenz:

Oldenburg, 2011
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Determining Minimal Testsets for Reversible Circuits Using Boolean Satisfiability




Autor:

Hongyan Zhang, Stefan Frehse, Robert Wille, Rolf Drechsler
Konferenz:
10th IEEE Africon
Referenz:

Livingstone, 2011
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» VisSAT: Visualization of SAT Solver Internals for Computer Aided Hardware Verification




Autor:

Robert Wille, André Sülflow, Rolf Drechsler
Konferenz:
International Conference on Modeling, Simulation and Visualization Methods (MSV)
Referenz:

pp. 36-39, Las Vegas, 2011
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization




Autor:

Robert Wille, Hongyan Zhang, Rolf Drechsler
Konferenz:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Referenz:

pp. 120-125, Chennai, 2011
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» An Introduction to Reversible Circuit Design




Autor:

Robert Wille
Konferenz:
Saudi International Electronics, Communications and Photonics Conference (SIECPC)
Referenz:

Riyadh, 2011
Hyperlink:

[Link zur Konferenz]


» Encoding OCL Data Types for SAT-based Verification of UML/OCL Models




Autor:

Mathias Soeken, Robert Wille, Rolf Drechsler
Konferenz:
5th International Conference on Tests & Proofs (TAP)
Referenz:

pp. 152-170, Zurich, 2011
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Designing a RISC CPU in Reversible Logic




Autor:

Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
Konferenz:
41st International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

pp. 170-175, Tuusula, 2011
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits




Autor:

Rolf Drechsler, Robert Wille
Konferenz:
41st International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

pp. 78-85, Tuusula, 2011
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Elementary Quantum Gate Realizations for Multiple-Control Toffoli Gates




Autor:

D. Michael Miller, Robert Wille, Z. Sasanian
Konferenz:
41st International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

pp. 288-293, Tuusula, 2011
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Verifying Dynamic Aspects of UML Models




Autor:

Mathias Soeken, Robert Wille, Rolf Drechsler
Konferenz:
Design, Automation and Test in Europe (DATE)
Referenz:

pp. 1077-1082, Grenoble, 2011
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Determining the Minimal Number of Lines for Large Reversible Circuits




Autor:

Robert Wille, Oliver Keszöcze, Rolf Drechsler
Konferenz:
Design, Automation and Test in Europe (DATE)
Referenz:

pp. 1204—1207, Grenoble, 2011
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» SyReC: A Programming Language for Synthesis of Reversible Circuits




Autor:

Robert Wille, Sebastian Offermann, Rolf Drechsler
Konferenz:
Forum on specification & Design Languages (FDL)
Referenz:

pp. 184-189, Southampton, 2010
Received Best Paper Award
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Reducing the Number of Lines in Reversible Circuits




Autor:

Robert Wille, Mathias Soeken, Rolf Drechsler
Konferenz:
Design Automation Conference (DAC)
Referenz:

pp. 647-652, Anaheim, 2010
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Graph Transformation Units Guided by a SAT Solver




Autor:

Hans-Jörg Kreowski, Susanne Kuske, Robert Wille
Konferenz:
International Conference on Graph Transformations (ICGT)
Referenz:

pp. 27-42, Enschede, 2010
Hyperlink:

[Link zur Konferenz]


» Synthesizing Multiplier in Reversible Logic




Autor:

Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Konferenz:
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Referenz:

pp. 335-340, Vienna, 2010
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Window Optimization of Reversible and Quantum Circuits




Autor:

Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Konferenz:
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Referenz:

pp. 431-435, Vienna, 2010
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Enhancing Debugging of Multiple Missing Control Errors in Reversible Logic




Autor:

Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler
Konferenz:
Great Lakes Symposium on VLSI (GLSVLSI)
Referenz:

pp. 465-470, Rhode Island, 2010
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Efficient Simulation-based Debugging of Reversible Logic




Autor:

Stefan Frehse, Robert Wille, Rolf Drechsler
Konferenz:
40th International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

pp. 156-161, Barcelona, 2010
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Reducing Reversible Circuit Cost by Adding Lines




Autor:

D. Michael Miller, Robert Wille, Rolf Drechsler
Konferenz:
40th International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

pp. 217-222, Barcelona, 2010
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Verifying UML/OCL Models Using Boolean Satisfiability




Autor:

Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler
Konferenz:
Design, Automation and Test in Europe (DATE)
Referenz:

pp. 1341-1344, Dresden, 2010
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» SMT-based Stimuli Generation in the SystemC Verification Library




Autor:

Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler
Konferenz:
Forum on specification & Design Languages (FDL)
Referenz:

pp. 1-6, Sophia Antipolis, 2009
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Synthesizing Reversible Circuits for Irreversible Functions




Autor:

D. Michael Miller, Robert Wille, Gerhard W. Dueck
Konferenz:
Euromicro Conference on Digital System Design (DSD)
Referenz:

pp. 749-756, Patras, 2009
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» BDD-based Synthesis of Reversible Logic for Large Functions




Autor:

Robert Wille, Rolf Drechsler
Konferenz:
Design Automation Conference (DAC)
Referenz:

pp. 270-275, San Francisco, 2009
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Contradictory Antecedent Debugging in Bounded Model Checking




Autor:

Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
Konferenz:
Great Lakes Symposium on VLSI (GLSVLSI)
Referenz:

pp. 173-176, Boston, 2009
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Evaluation of Cardinality Constraints on SMT-based Debugging




Autor:

Andre Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler
Konferenz:
39th International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

pp. 298-303, Naha, Okinawa, 2009
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Equivalence Checking of Reversible Circuits




Autor:

Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
Konferenz:
39th International Symposium on Multiple-Valued Logic (ISMVL)
Referenz:

pp. 324-330, Naha, Okinawa, 2009
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Debugging of Toffoli Networks




Autor:

Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
Konferenz:
Design, Automation and Test in Europe (DATE)
Referenz:

pp. 1284-1289, Nice, 2009
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Reversible Logic Synthesis with Output Permutation




Autor:

Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler
Konferenz:
22nd International Conference on VLSI Design
Referenz:

pp. 189-194, New Delhi, 2009
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking




Autor:

Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler
Konferenz:
Euromicro Conference on Digital System Design (DSD)
Referenz:

pp. 542-549, Parma, 2008
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Contradiction Analysis for Constraint-based Random Simulation




Autor:

Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
Konferenz:
Forum on specification & Design Languages (FDL)
Referenz:

pp. 130-135, Stuttgart, 2008
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability




Autor:

Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler
Konferenz:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Referenz:

pp. 411-416, Montpellier, 2008
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» RevLib: An Online Resource for Reversible Functions and Reversible Circuits




Autor:

Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler
Konferenz:
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Referenz:

pp. 220-225, Dallas, 2008
RevLib is available at www.revlib.org
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don’t Cares




Autor:

Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Konferenz:
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Referenz:

pp. 214-219, Dallas, 2008
Received IEEE Young Researcher Award
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Quantified Synthesis of Reversible Logic




Autor:

Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große
Konferenz:
Design, Automation, and Test in Europe (DATE)
Referenz:

pp. 1015-1020, Munich, 2008
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Fast Exact Toffoli Network Synthesis of Reversible Logic




Autor:

Robert Wille, Daniel Große
Konferenz:
IEEE International Conference on Computer Aided Design (ICCAD)
Referenz:

pp. 60-64, San Jose, 2007
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» SWORD: A SAT like Prover Using Word Level Information




Autor:

Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
Konferenz:
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC)
Referenz:

pp. 88-93, Atlanta, 2007
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


WORKSHOPS


» Integrating an SMT-based Model Finder into USE




Autor:

Nils Przigoda, Frank Hilken, Judith Peters, Robert Wille, Martin Gogolla, Rolf Drechsler
Workshop:
Workshop on Model-Driven Engineering, Verification, and Validation (MoDeVVa)
Referenz:

Saint-Malo, France, 2016
Hyperlink:

[Link zum Workshop]


» Extraktion von Frame Conditions aus Operation Contracts




Autor:

Philipp Niemann, Frank Hilken, Martin Gogolla, Robert Wille
Workshop:
Software Engineering (SE)
Referenz:

Vienna, Austria, 2016
Hyperlink:

[Link zum Workshop]


» Synthesis of Optical Circuits with Contradictory Optimization Objectives




Autor:

Arighna Deb, Robert Wille, Oliver Keszöcze, Stefan Hillmich, Rolf Drechsler
Workshop:
The 2nd International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS Workshop)
Referenz:

Dresden, Germany, 2016
Hyperlink:

[Link zum Workshop]


» Visualizing Microfluidic Biochips Interactively




Autor:

Jannis Stoppe, Oliver Keszöcze, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Design Automation for Understanding Hardware Designs (DUHDE)
Referenz:

Dresden, Germany, 2016
Hyperlink:

[Link zum Workshop]


» Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses




Autor:

Nils Przigoda, Judith Peters, Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Model-Driven Engineering, Verification, and Validation (MoDeVVa)
Referenz:

Ottawa, Canada, 2015
Hyperlink:

[Link zum Workshop]


» Quo Vadis, Reversible Circuit Design? Towards Scaling Design and Synthesis of Reversible Circuits




Autor:

Eleonora Schönborn, Robert Wille, Rolf Drechsler
Workshop:
Reed-Muller Workshop
Referenz:

Waterloo, Canada, 2015
Hyperlink:

[Link zum Workshop]


» Verbesserung der Fehlersuche in inkonsistenten formalen Modellen




Autor:

Nils Przigoda, Robert Wille, Rolf Drechsler
Workshop:
18. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'15)
Referenz:

Chemnitz, Germany, 2015
Hyperlink:

[Link zum Workshop]


» Towards a Base Model for UML and OCL Verification




Autor:

Frank Hilken, Philipp Niemann, Robert Wille, Martin Gogolla
Workshop:
Model-Driven Engineering, Verification, and Validation (MoDeVVa)
Referenz:

Valencia, Spain, 2014
Hyperlink:

[Link zum Workshop]


» Towards a Multi-dimensional and Dynamic Visualization for ESL Designs




Autor:

Jannis Stoppe, Marc Michael, Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
DATE Friday Workshop: Design Automation for Understanding Hardware Designs
Referenz:

Dresden, Germany, 2014
Hyperlink:

[Link zum Workshop]


» Law-based Verification for Complex Swarm Systems




Autor:

Rolf Drechsler, Hoang M. Le, Mathias Soeken, Robert Wille
Workshop:
International Workshop on the Swarm at the Edge of the Cloud
Referenz:

Montreal, Canada
Hyperlink:

[Link zum Workshop]


» Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen




Autor:

Mathias Soeken, Robert Wille, Eugen Kuksa, Rolf Drechsler
Workshop:
16. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Referenz:

Rostock, 2013
Hyperlink:

[Link zum Workshop]


» Verification of Embedded Systems Using Modeling and Implementation Languages




Autor:

Mathias Soeken, Heinz Riener, Robert Wille, Görschwin Fey, Rolf Drechsler
Workshop:
International Workshop on Metamodelling and Code Generation for Embedded Systems (MeCoEs'12)
Referenz:

pp. 67-72, Tampere, Finland, 2012
PDF:

[hier ansehen]
Hyperlink:

[Link zum Workshop]


» Towards Increasing Test Compaction Abilities of SAT-based ATPG through Fault Detection Constraints




Autor:

Stephan Eggersglüß, Melanie Diepenbeck, Robert Wille, Rolf Drechsler
Workshop:
IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12)
Referenz:

Niigata, Japan, 2012
PDF:

[hier ansehen]
Hyperlink:

[Link zum Workshop]


» Towards Embedding of Large Functions for Reversible Logic




Autor:

Mathias Soeken, Robert Wille, Laura Tague, D. Michael Miller, Rolf Drechsler
Workshop:
International Workshop on Boolean Problems
Referenz:

Freiberg, 2012
Hyperlink:

[Link zum Workshop]


» Using πDDs in the Design for Reversible Circuits




Autor:

Mathias Soeken, Robert Wille, Shin-Ichi Minato, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Referenz:

Kopenhagen, 2012
Hyperlink:

[Link zum Workshop]


» Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams




Autor:

Julia Seiter, Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Referenz:

Kopenhagen, 2012
Hyperlink:

[Link zum Workshop]


» Towards Automatic Determination of Problem Bounds for Object Instantiation in Static Model Verification




Autor:

Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
Model-Driven Engineering, Verification, And Validation (MoDeVVa)
Referenz:

Wellington, 2011
Hyperlink:

[Link zum Workshop]


» Synthesis of Reversible Circuits with Minimal Lines for Large Functions




Autor:

Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Referenz:

pp. 59-70, Gent, 2011
Hyperlink:

[Link zum Workshop]


» Customized Design Flows for Reversible Circuits Using RevKit




Autor:

Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Referenz:

pp. 91-96, Gent, 2011
Hyperlink:

[Link zum Workshop]


» Improving ESOP-based Synthesis of Reversible Logic Using Evolutionary Algorithms




Autor:

Rolf Drechsler, Alexander Finder, Robert Wille
Workshop:
6th European Workshop on Hardware Optimization Techniques (EvoHOT)
Referenz:

Applications of Evolutionary Computation, LNCS 6625, pp. 151-161, Turin, 2011
PDF:

[hier ansehen]
Hyperlink:

[Link zum Workshop]


» Designing a RISC CPU in Reversible Logic




Autor:

Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
Workshop:
14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Referenz:

pp. 249-258, Oldenburg, 2011
Hyperlink:

[Link zum Workshop]


» SAT-based ATPG for Reversible Circuits




Autor:

Hongyan Zhang, Robert Wille, Rolf Drechsler
Workshop:
5th International Design & Test Workshop (IDT)
Referenz:

pp. 149-154, Abu Dhabi, 2010
Hyperlink:

[Link zum Workshop]


» Hierarchical Synthesis of Reversible Circuits Using Positive and Negative Davio Decomposition




Autor:

Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
5th International Design & Test Workshop (IDT)
Referenz:

pp. 143-148, Abu Dhabi, 2010
PDF:

[hier ansehen]
Hyperlink:

[Link zum Workshop]


» RevKit: A Toolkit for Reversible Circuit Design




Autor:

Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Referenz:

pp. 69-72, Bremen, 2010
PDF:

[hier ansehen]
Hyperlink:

[Link zum Workshop]


» Hierarchical Synthesis of Reversible Circuits Using Positive and Negative Davio Decomposition




Autor:

Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Referenz:

pp. 55-58, Bremen, 2010
Hyperlink:

[Link zum Workshop]


» SyReC: A Programming Language for Synthesis of Reversible Circuits




Autor:

Robert Wille, Sebastian Offermann, Rolf Drechsler
Workshop:
International Workshop on Logic Synthesis (IWLS)
Referenz:

Irvine, 2010
Hyperlink:

[Link zum Workshop]


» VisSAT: Visualization of SAT Solver Internals




Autor:

Robert Wille, Andre Sülflow, Christian Genz, Rolf Drechsler
Workshop:
University Booth at Design, Automation and Test in Europe (DATE10)
Referenz:

Dresden, 2010
PDF:

[hier ansehen]
Hyperlink:

[Link zum Workshop]


» SyReC: A Programming Language for Synthesis of Reversible Circuits




Autor:

Robert Wille, Sebastian Offermann, Rolf Drechsler
Workshop:
13. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Referenz:

Dresden, 2010
Hyperlink:

[Link zum Workshop]


» Verifying UML/OCL Models Using Boolean Satisfiability




Autor:

Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler
Workshop:
13. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Referenz:

pp 57-66, Dresden, 2010
Hyperlink:

[Link zum Workshop]


» Reducing Reversible Circuit Cost by Adding Lines




Autor:

D. Michael Miller, Robert Wille, Rolf Drechsler
Workshop:
International Workshop on Logic Synthesis (IWLS)
Referenz:

Berkeley, 2009
Hyperlink:

[Link zum Workshop]


» Synthesis of Reversible Functions Beyond Gate Count and Quantum Cost




Autor:

Robert Wille, Mehdi Saeedi, Rolf Drechsler
Workshop:
International Workshop on Logic Synthesis (IWLS)
Referenz:

Berkeley, 2009
PDF:

[hier ansehen]
Hyperlink:

[Link zum Workshop]


» Synthesizing Reversible Logic: An Overview




Autor:

Robert Wille, Rolf Drechsler
Workshop:
Reed-Muller Workshop
Referenz:

Naha, Okinawa, 2009
Hyperlink:

[Link zum Workshop]


» Synthesising Reversible Circuits from Irreversible Specifications using Reed-Muller Spectral Techniques




Autor:

D. Michael Miller, Gerhard W. Dueck, Robert Wille
Workshop:
Reed-Muller Workshop
Referenz:

Naha, Okinawa, 2009
Hyperlink:

[Link zum Workshop]


» FormED: A Formal Environment for Debugging




Autor:

Andre Sülflow, Robert Wille, Christian Genz, Görschwin Fey, Rolf Drechsler
Workshop:
University Booth at Design, Automation and Test in Europe (DATE09)
Referenz:

Nizza, 2009
PDF:

[hier ansehen]
Hyperlink:

[Link zum Workshop]


» Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic




Autor:

Robert Wille, Rolf Drechsler
Workshop:
Reversible Computation
Referenz:

York, 2009
Hyperlink:

[Link zum Workshop]


» Equivalence Checking of Reversible Circuits




Autor:

Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
Workshop:
12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Referenz:

2009
Hyperlink:

[Link zum Workshop]


» Reversible Logic Synthesis with Output Permutation




Autor:

Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler
Workshop:
International Workshop on Boolean Problems
Referenz:

Freiberg, 2008
Hyperlink:

[Link zum Workshop]


» Contradiction Analysis for Constraint-based Random Simulation




Autor:

Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
Workshop:
Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS)
Referenz:

pp. 25-30, Dresden, 2008
Hyperlink:

[Link zum Workshop]


» Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking




Autor:

Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
Workshop:
11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Referenz:

pp. 169-178, Freiburg, 2008
Hyperlink:

[Link zum Workshop]


» Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits




Autor:

Andre Sülflow, Ulrich Kühne, Robert Wille, Daniel Große, Rolf Drechsler
Workshop:
IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07)
Referenz:

pp. 31-36, Beijing, P.R.China, 2007
PDF:

[hier ansehen]
Hyperlink:

[Link zum Workshop]


» Parallelisierung von SAT-basierter Testmustergenerierung




Autor:

Daniel Tille, Robert Wille, Rolf Drechsler
Workshop:
21. Workshop der GI/ITG-Fachgruppe Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS 2007)
Referenz:

pp. 213-217, Hamburg, 2007
Hyperlink:

[Link zum Workshop]


» Building Free Binary Decision Diagrams Using SAT Solvers




Autor:

Robert Wille, Görschwin Fey, Rolf Drechsler
Workshop:
8th Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM2007)
Referenz:

Oslo, 2007
Hyperlink:

[Link zum Workshop]


» Formal Verification on the Word Level using SAT-like Proof Techniques




Autor:

Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler
Workshop:
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Referenz:

pp. 165-173, Erlangen, 2007
Hyperlink:

[Link zum Workshop]

















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