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Home « Team « Publikationen
» Publikationen von
Robert Wille
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BÜCHER |
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» Auf dem Weg zum Quantencomputer - Entwurf reversibler Logik
[Lesen Sie hier mehr!]
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Verlag: |
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Shaker Verlag |
Autor:
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Rolf Drechsler, Mathias Soeken, Robert Wille (Hrsg.) |
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gebunden |
Erscheinungsjahr:
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2012
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» Towards a Design Flow for Reversible Logic
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Robert Wille, Rolf Drechsler |
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Gebunden |
Erscheinungsjahr:
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2010
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BUCHBEITRÄGE |
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| » SyReC: A Programming Language for Synthesis of Reversible Circuits |
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Autor:
| Robert Wille, Sebastian Offermann, Rolf Drechsler
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| Herausgeber: | Tom J. Kazmierski, Adam Morawiec |
| Buchtitel: | System Specification and Design Languages: Selected Contributions from FDL 2010 |
| Verlag: | Springer |
| Seiten: | 207-222 |
| Erscheinungsjahr: | 2012 |
| Format: | Hardcover |
| » SMT-based Stimuli Generation in the SystemC Verification Library |
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Autor:
| Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler
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| Herausgeber: | Dominique Borrione |
| Buchtitel: | Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s: Selected Contributions on Specification, Design, and Verification from FDL 2009 |
| Verlag: | Springer |
| Seiten: | 227-244 |
| Erscheinungsjahr: | 2010 |
| Format: | Hardcover |
| » Ein Entwurfsablauf für Reversible Schaltkreise |
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Autor:
| Robert Wille
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| Herausgeber: | S. Hölldobler et al. |
| Buchtitel: | Ausgezeichnete Informatikdissertationen 2009 |
| Verlag: | GI |
| Seiten: | 291-300 |
| Erscheinungsjahr: | 2010 |
| Format: | Paperback |
| » Synthesis of Boolean Functions in Reversible Logic |
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Autor:
| Robert Wille, Rolf Drechsler
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| Herausgeber: | Tsutomu Sasao, Jon T. Butler, Mitchell Thornton |
| Buchtitel: | Progress in Applications of Boolean Functions (Synthesis Lectures on Digital Circuits and Systems) |
| Verlag: | Morgan and Claypool Publishers |
| Seiten: | 75-92 |
| Erscheinungsjahr: | 2010 |
| Format: | Paperback |
| » Debugging Contradictory Constraints in Constraint-based Random Simulation |
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Autor:
| Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
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| Herausgeber: | Martin Radetzki |
| Buchtitel: | Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL'08 |
| Verlag: | Springer |
| Seiten: | 273-290 |
| Erscheinungsjahr: | 2009 |
| Format: | gebunden |
| » SWORD: A SAT like Prover Using Word Level Information |
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Autor:
| Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
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| Herausgeber: | Ricardo Reis, Vincent Mooney, Paul Hasler |
| Buchtitel: | VLSI-SoC: Advanced Topics on Systems on a Chip:
A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip |
| Verlag: | Springer |
| Seiten: | 175-192 |
| Erscheinungsjahr: | 2009 |
| Format: | Hardcover |
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ZEITSCHRIFTEN |
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» RevKit: An Open Source Toolkit for the Design of Reversible Circuits
[Link zur Zeitschriften-Homepage]
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Autor:
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Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler |
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Reversible Computation 2011 (Series: Lecture Notes in Computer Science) |
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Volume 7165, Third International Workshop, RC 2011, Revised Papers |
Jahr:
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2012
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» Special Issue on Reversible Computation
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler, Irek Ulidowski, Robert Wille (editors) |
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Multiple-Valued Logic and Soft Computing |
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Volume 18, Number 1 |
Jahr:
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2012
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» RevKit: A Toolkit for Reversible Circuit Design
[Link zur Zeitschriften-Homepage]
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Autor:
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Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler |
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Multiple-Valued Logic and Soft Computing |
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Volume 18, Number 1, pp. 55-65 |
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2012
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» Synthesis of Quantum Circuits for Linear Nearest Neighbor Architectures
[Link zur Zeitschriften-Homepage]
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Autor:
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Mehdi Saeedi, Robert Wille, Rolf Drechsler |
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Quantum Information Processing |
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Volume 10, Number 3, pp. 355-377DOI: 10.1007/s11128-010-0201-2 |
Jahr:
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2011
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» Debugging Reversible Circuits
[Link zur Zeitschriften-Homepage]
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Autor:
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Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler |
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INTEGRATION, the VLSI Journal |
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Volume 44, Number 1, pp. 51-61, JanuaryDOI: 10.1016/j.vlsi.2010.08.002 |
Jahr:
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2011
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» BDD-Based Synthesis of Reversible Logic
[Link zur Zeitschriften-Homepage]
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Autor:
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Robert Wille, Rolf Drechsler |
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International Journal of Applied Metaheuristic Computing (IJAMC) |
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Volume 1, Number 4, pp. 25-41 |
Jahr:
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2010
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» Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic
[Link zur Zeitschriften-Homepage]
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Autor:
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Robert Wille, Rolf Drechsler |
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Electronic Notes in Theoretical Computer Science |
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Volume 253, Number 6, pp. 57-70DOI: 10.1016/j.entcs.2010.02.006 |
Jahr:
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2010
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» Synthese reversibler Logik
[Link zur Zeitschriften-Homepage]
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Autor:
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Robert Wille, Rolf Drechsler |
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it-Information Technology |
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Volume 52, Number 1, pp. 30-38
PDF Download |
Jahr:
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2010
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» Exact Synthesis of Elementary Quantum Gate Circuits
[Link zur Zeitschriften-Homepage]
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Autor:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
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Multiple-Valued Logic and Soft Computing |
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Volume 15, Number 4, pp. 283-300 |
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2009
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» Exact Multiple Control Toffoli Network Synthesis with SAT Techniques
[Link zur Zeitschriften-Homepage]
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Autor:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 28, Number 5, pp. 703-715, MayDOI: 10.1109/TCAD.2009.2017215 |
Jahr:
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2009
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» Building Free Binary Decision Diagrams Using SAT Solvers
[Link zur Zeitschriften-Homepage]
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Autor:
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Robert Wille, Görschwin Fey, Rolf Drechsler |
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Facta Universitatis, Series: Electronics and Energetics |
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Volume 20, Number 3, pp. 381-394, |
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2007
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KONFERENZEN |
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» Improved SAT-based ATPG: More Constraints, Better Compaction
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Autor:
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Stephan Eggersglüß, Robert Wille, Rolf Drechsler |
| Konferenz: |
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IEEE/ACM International Conference on Computer-Aided Design (ICCAD) |
Referenz:
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| San Jose, USA, 2013
| Hyperlink:
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| [Link zur Konferenz]
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» A Compact and Efficient SAT Encoding for Quantum Circuits
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Autor:
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Robert Wille, Nils Przigoda, Rolf Drechsler |
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IEEE Africon |
Referenz:
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| Mauritius, 2013
| Hyperlink:
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| [Link zur Konferenz]
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» Exploiting Reversibility in the Complete Simulation of Reversible Circuits
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Autor:
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Robert Wille, Simon Stelter, Rolf Drechsler |
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IEEE Africon |
Referenz:
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| Mauritius, 2013
| Hyperlink:
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| [Link zur Konferenz]
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» Cone of Influence Analysis at the Electronic System Level Using Machine Learning
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Autor:
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Jannis Stoppe, Robert Wille, Rolf Drechsler |
| Konferenz: |
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Euromicro Conference on Digital System Design (DSD) |
Referenz:
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| Santander, Spain, 2013
| Hyperlink:
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| [Link zur Konferenz]
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» Minimal Stimuli Generation in Simulation-based Verification
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Autor:
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Shuo Yang, Robert Wille, Daniel Große and Rolf Drechsler |
| Konferenz: |
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Euromicro Conference on Digital System Design (DSD) |
Referenz:
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| Santander, Spain, 2013
| Hyperlink:
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| [Link zur Konferenz]
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» The SyReC Hardware Description Language:
Enabling Scalable Synthesis of Reversible Circuits
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Autor:
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Robert Wille, Rolf Drechsler |
| Konferenz: |
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International Midwest Symposium on Circuits and Systems (MWSCAS) |
Referenz:
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| Columbus, USA, 2013
| Hyperlink:
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| [Link zur Konferenz]
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» Data Extraction from SystemC Designs using Debug Symbols and the SystemC API
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Autor:
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Jannis Stoppe, Robert Wille, Rolf Drechsler |
| Konferenz: |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
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| Natal, Brazil, 2013
| Hyperlink:
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| [Link zur Konferenz]
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» On the “Q” in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-structure
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Autor:
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Philipp Niemann, Robert Wille, Rolf Drechsler |
| Konferenz: |
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Reversible Computation |
Referenz:
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| Victoria, Canada, 2013
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Exploiting Negative Control Lines in the Optimization of Reversible Circuits
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Autor:
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Kamalika Datta, Gaurav Rathi, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler |
| Konferenz: |
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Reversible Computation |
Referenz:
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| Victoria, Canada, 2013
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure
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Autor:
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Arighna Deb, Debesh Kumar Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler |
| Konferenz: |
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Reversible Computation |
Referenz:
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| Victoria, Canada, 2013
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Reducing the Depth of Quantum Circuits Using Additional Lines
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Autor:
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Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
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Reversible Computation |
Referenz:
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| Victoria, Canada, 2013
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits
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Autor:
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Robert Wille, Hongyan Zhang, Rolf Drechsler |
| Konferenz: |
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43rd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| Toyama, 2013
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Exact Template Matching Using Boolean Satisfiability
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Autor:
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Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
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43rd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| Toyama, 2013
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Determining Relevant Model Elements for the Verification of UML/OCL Specifications
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Autor:
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Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| Grenoble, France, 2013
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Towards a Generic Verification Methodology for System Models
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Autor:
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Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler |
| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| Grenoble, France, 2013
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Improving the Mapping of Reversible Circuits to Quantum Circuits Using Multiple Target Lines
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Autor:
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Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler |
| Konferenz: |
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Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
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| Yokohama, Japan, 2013
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Towards Dialog Systems for Assisted Natural Language Processing in the Design of Embedded Systems
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Autor:
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Rolf Drechsler, Mathias Soeken, Robert Wille |
| Konferenz: |
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IEEE Design and Test Symposium 2012 (IDT) |
Referenz:
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| Doha, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Synthesis of Reversible Circuits Using Decision Diagrams
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Autor:
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Rolf Drechsler, Robert Wille |
| Konferenz: |
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International Symposium on Electronic System Design (ISED) |
Referenz:
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| Kolkata, WB, India, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Completeness-Driven Development
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Autor:
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Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille |
| Konferenz: |
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International Conference on Graph Transformation |
Referenz:
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| pp. 38-50, Bremen, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Formal Specification Level: Towards Verification-driven Design Based on Natural Language Processing
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Autor:
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Rolf Drechsler, Mathias Soeken, Robert Wille |
| Konferenz: |
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Forum on specification & Design Languages (FDL) |
Referenz:
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| pp. 53-58, Vienna, Austria, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Circuit Line Minimization in the HDL-based Synthesis of Reversible Logic
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Autor:
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Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler |
| Konferenz: |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
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| pp. 213-218, Amherst, USA, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Coverage-driven Stimuli Generation
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Autor:
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Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler |
| Konferenz: |
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15th Euromicro Conference on Digital System Design (DSD) |
Referenz:
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| Izmir, Turkey, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology
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Autor:
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Rolf Drechsler, Robert Wille |
| Konferenz: |
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International Symposium on VLSI Design and Test (VDAT) |
Referenz:
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| Shibpur, India, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Assisted Behavior Driven Development Using Natural Language Processing
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Autor:
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Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
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50th International Conference on Objects, Models, Components, Patterns (TOOLS) |
Referenz:
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| pp. 269-287, Prague, Czech Republic, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Realizing Reversible Circuits Using a New Class of Quantum Gates
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Autor:
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Zahra Sasanian, Robert Wille, Michael Miller |
| Konferenz: |
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Design Automation Conference (DAC) |
Referenz:
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| San Francisco, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits
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Autor:
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Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler |
| Konferenz: |
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42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| 2012, Victoria
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» A Synthesis Flow for Sequential Reversible Circuits
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Autor:
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Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler |
| Konferenz: |
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42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| 2012, Victoria
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines
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Autor:
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Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler |
| Konferenz: |
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42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
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| Victoria, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis
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Autor:
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Robert Wille, Rolf Drechsler, Christof Oswald, Alberto Garcia-Ortiz |
| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| Dresden, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Eliminating Invariants in UML/OCL Models
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Autor:
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Mathias Soeken, Robert Wille, Rolf Drechsler
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| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| pp. 1142-1145, Dresden, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Debugging of Inconsistent UML/OCL Models
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Autor:
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Robert Wille, Mathias Soeken, Rolf Drechsler
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| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| pp. 1078-1083, Dresden, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Synthesis of Reversible Circuits with Minimal Lines for Large Functions
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Autor:
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Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler |
| Konferenz: |
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Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
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| pp. 85-92, Sydney, 2012
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Improved Fault Diagnosis for Reversible Circuits
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Autor:
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Hongyan Zhang, Robert Wille, Rolf Drechsler |
| Konferenz: |
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Asian Test Symposium (ATS) |
Referenz:
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| New Delhi, 2011
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Efficient Realization of Control Logic in Reversible Circuits
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Autor:
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Sebastian Offermann, Robert Wille, Rolf Drechsler |
| Konferenz: |
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Forum on specification & Design Languages (FDL) |
Referenz:
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| Oldenburg, 2011
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Determining Minimal Testsets for Reversible Circuits Using Boolean Satisfiability
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Autor:
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Hongyan Zhang, Stefan Frehse, Robert Wille, Rolf Drechsler |
| Konferenz: |
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10th IEEE Africon |
Referenz:
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| Livingstone, 2011
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» VisSAT: Visualization of SAT Solver Internals for Computer Aided Hardware Verification
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Autor:
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Robert Wille, André Sülflow, Rolf Drechsler |
| Konferenz: |
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International Conference on Modeling, Simulation and Visualization Methods (MSV) |
Referenz:
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| pp. 36-39, Las Vegas, 2011
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» ATPG for Reversible Circuits Using Simulation,
Boolean Satisfiability, and Pseudo Boolean
Optimization
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Autor:
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Robert Wille, Hongyan Zhang, Rolf Drechsler |
| Konferenz: |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
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| pp. 120-125, Chennai, 2011
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» An Introduction to Reversible Circuit Design
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Autor:
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Robert Wille |
| Konferenz: |
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Saudi International Electronics, Communications and Photonics Conference (SIECPC) |
Referenz:
|
| Riyadh, 2011
| Hyperlink:
|
| [Link zur Konferenz]
|
» Encoding OCL Data Types for SAT-based Verification of UML/OCL Models
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
5th International Conference on Tests & Proofs (TAP) |
Referenz:
|
| pp. 152-170, Zurich, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Designing a RISC CPU in Reversible Logic
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler |
| Konferenz: |
|
41st International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 170-175, Tuusula, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits
|
|
|
|
Autor:
|
|
Rolf Drechsler, Robert Wille |
| Konferenz: |
|
41st International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 78-85, Tuusula, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Elementary Quantum Gate Realizations for Multiple-Control Toffoli Gates
|
|
|
|
Autor:
|
|
D. Michael Miller, Robert Wille, Z. Sasanian |
| Konferenz: |
|
41st International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 288-293, Tuusula, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Verifying Dynamic Aspects of UML Models
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1077-1082, Grenoble, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Determining the Minimal Number of Lines for Large Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Oliver Keszöcze, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1204-1207, Grenoble, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» SyReC: A Programming Language for Synthesis of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Sebastian Offermann, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 184-189, Southampton, 2010
Received Best Paper Award
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reducing the Number of Lines in Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| pp. 647-652, Anaheim, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Graph Transformation Units Guided by a SAT Solver
|
|
|
|
Autor:
|
|
Hans-Jörg Kreowski, Susanne Kuske, Robert Wille |
| Konferenz: |
|
International Conference on Graph Transformations (ICGT) |
Referenz:
|
| pp. 27-42, Enschede, 2010
| Hyperlink:
|
| [Link zur Konferenz]
|
» Synthesizing Multiplier in Reversible Logic
|
|
|
|
Autor:
|
|
Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 335-340, Vienna, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Window Optimization of Reversible and Quantum Circuits
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 431-435, Vienna, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Enhancing Debugging of Multiple Missing Control Errors in Reversible Logic
|
|
|
|
Autor:
|
|
Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler
|
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 465-470, Rhode Island, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Efficient Simulation-based Debugging of Reversible Logic
|
|
|
|
Autor:
|
|
Stefan Frehse, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
40th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 156-161, Barcelona, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reducing Reversible Circuit Cost by Adding Lines
|
|
|
|
Autor:
|
|
D. Michael Miller, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
40th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 217-222, Barcelona, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Verifying UML/OCL Models Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1341-1344, Dresden, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» SMT-based Stimuli Generation in the SystemC Verification Library
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 1-6, Sophia Antipolis, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Synthesizing Reversible Circuits for Irreversible Functions
|
|
|
|
Autor:
|
|
D. Michael Miller, Robert Wille, Gerhard W. Dueck |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 749-756, Patras, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» BDD-based Synthesis of Reversible Logic for Large Functions
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| pp. 270-275, San Francisco, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Contradictory Antecedent Debugging in Bounded Model Checking
|
|
|
|
Autor:
|
|
Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 173-176, Boston, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Evaluation of Cardinality Constraints on SMT-based Debugging
|
|
|
|
Autor:
|
|
Andre Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
39th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 298-303, Naha, Okinawa, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Equivalence Checking of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler |
| Konferenz: |
|
39th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 324-330, Naha, Okinawa, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Debugging of Toffoli Networks
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1284-1289, Nice, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reversible Logic Synthesis with Output Permutation
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
22nd International Conference on VLSI Design |
Referenz:
|
| pp. 189-194, New Delhi, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking
|
|
|
|
Autor:
|
|
Robert Wille, Görschwin Fey, Marc Messing, Gerhard
Angst, Lothar Linhard, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 542-549, Parma, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Contradiction Analysis for Constraint-based Random Simulation
|
|
|
|
Autor:
|
|
Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 130-135, Stuttgart, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| pp. 411-416, Montpellier, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» RevLib: An Online Resource for
Reversible Functions and Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Referenz:
|
| pp. 220-225, Dallas, 2008
RevLib is available at www.revlib.org
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Exact Synthesis of Elementary Quantum Gate
Circuits for Reversible Functions with Don’t Cares
|
|
|
|
Autor:
|
|
Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Referenz:
|
| pp. 214-219, Dallas, 2008
Received IEEE Young Researcher Award
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Quantified Synthesis of Reversible Logic
|
|
|
|
Autor:
|
|
Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große |
| Konferenz: |
|
Design, Automation, and Test in Europe (DATE) |
Referenz:
|
| pp. 1015-1020, Munich, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Fast Exact Toffoli Network Synthesis of Reversible Logic
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große |
| Konferenz: |
|
IEEE International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| pp. 60-64, San Jose, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» SWORD: A SAT like Prover Using Word Level Information
|
|
|
|
Autor:
|
|
Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC) |
Referenz:
|
| pp. 88-93, Atlanta, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
|
WORKSHOPS |
|
» Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Eugen Kuksa, Rolf Drechsler |
| Workshop: |
|
16. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
|
| Rostock, 2013
| Hyperlink:
|
| [Link zum Workshop]
|
» Verification of Embedded Systems Using Modeling and Implementation Languages
|
|
|
|
Autor:
|
|
Mathias Soeken, Heinz Riener, Robert Wille, Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
International Workshop on Metamodelling and Code Generation for Embedded Systems (MeCoEs'12) |
Referenz:
|
| pp. 67-72, Tampere, Finland, 2012
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Towards Increasing Test Compaction Abilities of SAT-based ATPG through Fault Detection Constraints
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Melanie Diepenbeck, Robert Wille, Rolf Drechsler |
| Workshop: |
|
IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12) |
Referenz:
|
| Niigata, Japan, 2012
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Towards Embedding of Large Functions for Reversible Logic
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Laura Tague, D. Michael Miller, Rolf Drechsler |
| Workshop: |
|
International Workshop on Boolean Problems |
Referenz:
|
| Freiberg, 2012
| Hyperlink:
|
| [Link zum Workshop]
|
» Using πDDs in the Design for Reversible Circuits
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Shin-Ichi Minato, Rolf Drechsler |
| Workshop: |
|
Workshop on Reversible Computation |
Referenz:
|
| Kopenhagen, 2012
| Hyperlink:
|
| [Link zum Workshop]
|
» Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams
|
|
|
|
Autor:
|
|
Julia Seiter, Mathias Soeken, Robert Wille, Rolf Drechsler |
| Workshop: |
|
Workshop on Reversible Computation |
Referenz:
|
| Kopenhagen, 2012
| Hyperlink:
|
| [Link zum Workshop]
|
» Towards Automatic Determination of Problem Bounds for Object Instantiation in Static Model Verification
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler |
| Workshop: |
|
Model-Driven Engineering, Verification, And Validation (MoDeVVa) |
Referenz:
|
| Wellington, 2011
| Hyperlink:
|
| [Link zum Workshop]
|
» Synthesis of Reversible Circuits with Minimal Lines for Large Functions
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler |
| Workshop: |
|
Workshop on Reversible Computation |
Referenz:
|
| pp. 59-70, Gent, 2011
| Hyperlink:
|
| [Link zum Workshop]
|
» Customized Design Flows for Reversible Circuits Using RevKit
|
|
|
|
Autor:
|
|
Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler |
| Workshop: |
|
Workshop on Reversible Computation |
Referenz:
|
| pp. 91-96, Gent, 2011
| Hyperlink:
|
| [Link zum Workshop]
|
» Improving ESOP-based Synthesis of Reversible Logic Using Evolutionary Algorithms
|
|
|
|
Autor:
|
|
Rolf Drechsler, Alexander Finder, Robert Wille |
| Workshop: |
|
6th European Workshop on Hardware Optimization Techniques (EvoHOT) |
Referenz:
|
| Applications of Evolutionary Computation, LNCS 6625, pp. 151-161, Turin, 2011
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Designing a RISC CPU in Reversible Logic
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler |
| Workshop: |
|
14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
|
| pp. 249-258, Oldenburg, 2011
| Hyperlink:
|
| [Link zum Workshop]
|
» SAT-based ATPG for Reversible Circuits
|
|
|
|
Autor:
|
|
Hongyan Zhang, Robert Wille, Rolf Drechsler |
| Workshop: |
|
5th International Design & Test Workshop (IDT) |
Referenz:
|
| pp. 149-154, Abu Dhabi, 2010
| Hyperlink:
|
| [Link zum Workshop]
|
» Hierarchical Synthesis of Reversible Circuits Using Positive and Negative Davio Decomposition
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler |
| Workshop: |
|
5th International Design & Test Workshop (IDT) |
Referenz:
|
| pp. 143-148, Abu Dhabi, 2010
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» RevKit: A Toolkit for Reversible Circuit Design
|
|
|
|
Autor:
|
|
Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler |
| Workshop: |
|
Workshop on Reversible Computation |
Referenz:
|
| pp. 69-72, Bremen, 2010
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Hierarchical Synthesis of Reversible Circuits Using Positive and Negative Davio Decomposition
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler |
| Workshop: |
|
Workshop on Reversible Computation |
Referenz:
|
| pp. 55-58, Bremen, 2010
| Hyperlink:
|
| [Link zum Workshop]
|
» SyReC: A Programming Language for Synthesis of
Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Sebastian Offermann, Rolf Drechsler |
| Workshop: |
|
International Workshop on Logic Synthesis (IWLS) |
Referenz:
|
| Irvine, 2010
| Hyperlink:
|
| [Link zum Workshop]
|
» VisSAT: Visualization of SAT Solver Internals
|
|
|
|
Autor:
|
|
Robert Wille, Andre Sülflow, Christian Genz, Rolf Drechsler |
| Workshop: |
|
University Booth at Design, Automation and Test in Europe (DATE10) |
Referenz:
|
| Dresden, 2010
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» SyReC: A Programming Language for Synthesis of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Sebastian Offermann, Rolf Drechsler |
| Workshop: |
|
13. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
|
| Dresden, 2010
| Hyperlink:
|
| [Link zum Workshop]
|
» Verifying UML/OCL Models Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler |
| Workshop: |
|
13. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
|
| pp 57-66, Dresden, 2010
| Hyperlink:
|
| [Link zum Workshop]
|
» Reducing Reversible Circuit Cost by Adding Lines
|
|
|
|
Autor:
|
|
D. Michael Miller, Robert Wille, Rolf Drechsler |
| Workshop: |
|
International Workshop on Logic Synthesis (IWLS) |
Referenz:
|
| Berkeley, 2009
| Hyperlink:
|
| [Link zum Workshop]
|
» Synthesis of Reversible Functions Beyond Gate Count and Quantum Cost
|
|
|
|
Autor:
|
|
Robert Wille, Mehdi Saeedi, Rolf Drechsler |
| Workshop: |
|
International Workshop on Logic Synthesis (IWLS) |
Referenz:
|
| Berkeley, 2009
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Synthesizing Reversible Logic: An Overview
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler |
| Workshop: |
|
Reed-Muller Workshop |
Referenz:
|
| Naha, Okinawa, 2009
| Hyperlink:
|
| [Link zum Workshop]
|
» Synthesising Reversible Circuits from Irreversible Specifications using Reed-Muller Spectral Techniques
|
|
|
|
Autor:
|
|
D. Michael Miller, Gerhard W. Dueck, Robert Wille |
| Workshop: |
|
Reed-Muller Workshop |
Referenz:
|
| Naha, Okinawa, 2009
| Hyperlink:
|
| [Link zum Workshop]
|
» FormED: A Formal Environment for Debugging
|
|
|
|
Autor:
|
|
Andre Sülflow, Robert Wille, Christian Genz, Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
University Booth at Design, Automation and Test in Europe (DATE09) |
Referenz:
|
| Nizza, 2009
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler |
| Workshop: |
|
Reversible Computation |
Referenz:
|
| York, 2009
| Hyperlink:
|
| [Link zum Workshop]
|
» Equivalence Checking of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler |
| Workshop: |
|
12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
|
| 2009
| Hyperlink:
|
| [Link zum Workshop]
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» Reversible Logic Synthesis with Output Permutation
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Autor:
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Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
| Workshop: |
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International Workshop on Boolean Problems |
Referenz:
|
| Freiberg, 2008
| Hyperlink:
|
| [Link zum Workshop]
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» Contradiction Analysis for Constraint-based Random Simulation
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Autor:
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Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler |
| Workshop: |
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Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS)
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Referenz:
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| pp. 25-30, Dresden, 2008
| Hyperlink:
|
| [Link zum Workshop]
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» Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking
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Autor:
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Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
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11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen
zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
|
| pp. 169-178, Freiburg, 2008
| Hyperlink:
|
| [Link zum Workshop]
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» Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits
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Autor:
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Andre Sülflow, Ulrich Kühne, Robert Wille, Daniel Große, Rolf Drechsler |
| Workshop: |
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IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07) |
Referenz:
|
| pp. 31-36, Beijing, P.R.China, 2007
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
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» Parallelisierung von SAT-basierter Testmustergenerierung
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Autor:
|
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Daniel Tille, Robert Wille, Rolf Drechsler |
| Workshop: |
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21. Workshop der GI/ITG-Fachgruppe Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS 2007) |
Referenz:
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| pp. 213-217, Hamburg, 2007
| Hyperlink:
|
| [Link zum Workshop]
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» Building Free Binary Decision Diagrams Using SAT Solvers
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Autor:
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Robert Wille, Görschwin Fey, Rolf Drechsler |
| Workshop: |
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8th Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM2007) |
Referenz:
|
| Oslo, 2007
| Hyperlink:
|
| [Link zum Workshop]
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» Formal Verification on the Word Level using SAT-like Proof
Techniques
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Autor:
|
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Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Referenz:
|
| pp. 165-173, Erlangen, 2007
| Hyperlink:
|
| [Link zum Workshop]
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