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Home « Team « Publikationen
» Publikationen von
Rolf Drechsler
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BÜCHER |
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» Auf dem Weg zum Quantencomputer - Entwurf reversibler Logik
[Lesen Sie hier mehr!]
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Verlag: |
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Shaker Verlag |
Autor:
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Rolf Drechsler, Mathias Soeken, Robert Wille (Hrsg.) |
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gebunden |
Erscheinungsjahr:
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2012
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» High Quality Test Pattern Generation and Boolean Satisfiability
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Stephan Eggersglüß, Rolf Drechsler |
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Hardcover |
Erscheinungsjahr:
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2012
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» Applications of Evolutionary Computation
Applications of Evolutionary Computation
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Cecilia Di Chio, Anthony Brabazon, Gianni A. Di Caro, Rolf Drechsler, Muddassar Farooq, Jörn Grahl, Gary Greenfield, Christian Prins, Juan Romero und Giovanni Squillero, et al. |
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Gebunden |
Erscheinungsjahr:
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2011
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» Towards a Design Flow for Reversible Logic
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Robert Wille, Rolf Drechsler |
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Gebunden |
Erscheinungsjahr:
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2010
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» Debugging at the Electronic System Level
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Frank Rogin, Rolf Drechsler |
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Gebunden |
Erscheinungsjahr:
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2010
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» Quality-Driven SystemC Design
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Daniel Große, Rolf Drechsler |
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Hardcover |
Erscheinungsjahr:
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2010
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» Test Pattern Generation using Boolean Proof Engines
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille |
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Hardcover |
Erscheinungsjahr:
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2009
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» Robustness and Usability in Modern Design Flows
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Görschwin Fey, Rolf Drechsler |
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Hardcover |
Erscheinungsjahr:
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2008
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» Applications of Evolutionary Computing
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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M. Giacobini, A. Brabazon, S. Cagnoni, G. A. DiCaro, Rolf Drechsler, A. Ekart, A. I. Esparcia-Alcazar, M. Farooq, A. Fink, J. McCormack, M. O'Neill, J. Romero, F. Rothlauf, G. Squillero, S. Uyar, S. Yang
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Gebunden |
Erscheinungsjahr:
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2008
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» Applications of Evolutionary Computing
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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M. Giacobini, A. Brabazon, S. Cagoni, G.A. Di Caro, Rolf Drechsler, M. Farooq, A. Fink, E. Lutton, P. Machado, S. Minner, M. O'Neill, J. Romero, F. Rothlauf, G. Squillero, H. Takagi, A.S. Uyar, S. Yang |
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Gebunden |
Erscheinungsjahr:
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2007
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» SATRIX - Algorithmen für Boolesche Erfüllbarkeit
[Lesen Sie hier mehr!]
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Verlag: |
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Shaker Verlag |
Autor:
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Daniel Große, Görschwin Fey, Rolf Drechsler (Hrsg.) |
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Gebunden |
Erscheinungsjahr:
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2007
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» Applications of Evolutionary Computing
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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F. Rothlauf, J. Branke, S. Cagnoni, E. Costa, C. Cotta, Rolf Drechsler, E. Lutton, P. Machado, J.H. Moore, J. Romero, G.D. Smith, G. Squillero, H. Takagi (Eds.) |
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Gebunden |
Erscheinungsjahr:
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2006
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» Advanced BDD Optimization
[Lesen Sie hier mehr!]
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Verlag: |
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Springer Verlag |
Autor:
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Rüdiger Ebendt, Görschwin Fey, Rolf Drechsler |
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Hardcover |
Erscheinungsjahr:
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2005
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» Technische Informatik - Eine Einführung
[Lesen Sie hier mehr!]
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Verlag: |
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Pearson Studium |
Autor:
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Bernd Becker, Rolf Drechsler, Paul Molitor |
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Gebunden |
Erscheinungsjahr:
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2005
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» Applications of Evolutionary Computing
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Franz Rothlauf, Jürgen Branke, Stefano Cagnoni, David W. Corne, Rolf Drechsler, Yaochu Jin, Penousal Machado, Elena Marchiori, Juan Romero, George D. Smith, Giovanni Squillero |
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Gebunden |
Erscheinungsjahr:
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2005
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» FunTaskIC - Eine integrierte Entwurfsumgebung für SystemC
[Lesen Sie hier mehr!]
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Verlag: |
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Shaker Verlag |
Autor:
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Görschwin Fey, Rolf Drechsler (Hrsg.) |
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Gebunden |
Erscheinungsjahr:
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2005
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» Applications of Evolutionary Computing
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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G.R. Raidl, S. Cagnoni, J. Branke, D.W. Corne, Rolf Drechsler, Y. Jin, C.G. Johnson, P. Machado, E. Marchiori,F. Rothlauf, G.D. Smith, G. Squillero
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Gebunden |
Erscheinungsjahr:
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2004
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» Advanced Formal Verification
[Lesen Sie hier mehr!]
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Verlag: |
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Kluwer Academic Publishers |
Autor:
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Rolf Drechsler |
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Gebunden |
Erscheinungsjahr:
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2004
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» Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
[Lesen Sie hier mehr!]
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Verlag: |
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Shaker Verlag |
Autor:
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Rolf Drechsler |
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Gebunden |
Erscheinungsjahr:
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2003
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» Evolutionary Algorithms for Embedded System Design
[Lesen Sie hier mehr!]
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Verlag: |
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Kluwer Academic Publishers |
Autor:
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Rolf Drechsler, Nicole Drechsler |
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Gebunden |
Erscheinungsjahr:
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2002
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» Software-Engineering und Hardware-Design
[Lesen Sie hier mehr!]
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Verlag: |
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Carl Hanser Verlag |
Autor:
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Axel Sikora, Rolf Drechsler
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Gebunden |
Erscheinungsjahr:
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2002
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» Towards One-Pass Synthesis
[Lesen Sie hier mehr!]
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Verlag: |
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Kluwer Academic Publishers |
Autor:
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Rolf Drechsler, Wolfgang Günther
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Hardcover |
Erscheinungsjahr:
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2002
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» Spectral Techniques in VLSI CAD
[Lesen Sie hier mehr!]
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Verlag: |
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Kluwer Academic Publishers |
Autor:
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Mitchell A. Thornton, Rolf Drechsler, D. Michel Miller |
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Hardcover |
Erscheinungsjahr:
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2001
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» Formal Verification of Circuits
[Lesen Sie hier mehr!]
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Verlag: |
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Kluwer Academic Publishers |
Autor:
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Rolf Drechsler |
| Format: |
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Hardcover |
Erscheinungsjahr:
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2000
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» Evolutionary Algorithms for VLSI CAD
[Lesen Sie hier mehr!]
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Verlag: |
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Kluwer Academic Publishers |
Autor:
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Rolf Drechsler |
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Hardcover |
Erscheinungsjahr:
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1998
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» Binary Decision Diagrams: Theory and Implementations
[Lesen Sie hier mehr!]
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Verlag: |
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Kluwer Academic Publisher |
Autor:
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Rolf Drechsler, Bernd Becker |
| Format: |
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Hardcover |
Erscheinungsjahr:
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1998
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» Graphenbasierte Funktionsdarstellung
[Lesen Sie hier mehr!]
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Verlag: |
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B.G. Teubner |
Autor:
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Rolf Drechsler, Bernd Becker |
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Gebunden |
Erscheinungsjahr:
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1998
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» Functional Decision Diagrams und ihre Anwendung
[Lesen Sie hier mehr!]
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Verlag: |
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Modell Verlag |
Autor:
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Rolf Drechsler |
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Gebunden |
Erscheinungsjahr:
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1996
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BUCHBEITRÄGE |
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| » SyReC: A Programming Language for Synthesis of Reversible Circuits |
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Autor:
| Robert Wille, Sebastian Offermann, Rolf Drechsler
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| Herausgeber: | Tom J. Kazmierski, Adam Morawiec |
| Buchtitel: | System Specification and Design Languages: Selected Contributions from FDL 2010 |
| Verlag: | Springer |
| Seiten: | 207-222 |
| Erscheinungsjahr: | 2012 |
| Format: | Hardcover |
| » Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis |
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Autor:
| Daniel Große, Görschwin Fey, Rolf Drechsler
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| Herausgeber: | Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus |
| Buchtitel: | Design and Test Technology for Dependable Systems-on-Chip |
| Verlag: | Information Science Reference |
| Seiten: | 119-129 |
| Erscheinungsjahr: | 2011 |
| Format: | Hardcover |
| » SMT-based Stimuli Generation in the SystemC Verification Library |
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Autor:
| Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler
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| Herausgeber: | Dominique Borrione |
| Buchtitel: | Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s: Selected Contributions on Specification, Design, and Verification from FDL 2009 |
| Verlag: | Springer |
| Seiten: | 227-244 |
| Erscheinungsjahr: | 2010 |
| Format: | Hardcover |
| » Synthesis of Boolean Functions in Reversible Logic |
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Autor:
| Robert Wille, Rolf Drechsler
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| Herausgeber: | Tsutomu Sasao, Jon T. Butler, Mitchell Thornton |
| Buchtitel: | Progress in Applications of Boolean Functions (Synthesis Lectures on Digital Circuits and Systems) |
| Verlag: | Morgan and Claypool Publishers |
| Seiten: | 75-92 |
| Erscheinungsjahr: | 2010 |
| Format: | Paperback |
| » Non-Clausal SAT and ATPG |
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Autor:
| Rolf Drechsler, Tommi Junttila and Ilkka Niemelä
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| Herausgeber: | A. Biere, M. Heule, H. van Maaren, T. Walsh |
| Buchtitel: | Handbook of Satisfiability |
| Verlag: | IOS Press |
| Seiten: | 655-693 |
| Erscheinungsjahr: | 2009 |
| Format: | gebunden |
| » Debugging Contradictory Constraints in Constraint-based Random Simulation |
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Autor:
| Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
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| Herausgeber: | Martin Radetzki |
| Buchtitel: | Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL'08 |
| Verlag: | Springer |
| Seiten: | 273-290 |
| Erscheinungsjahr: | 2009 |
| Format: | gebunden |
| » SWORD: A SAT like Prover Using Word Level Information |
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Autor:
| Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
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| Herausgeber: | Ricardo Reis, Vincent Mooney, Paul Hasler |
| Buchtitel: | VLSI-SoC: Advanced Topics on Systems on a Chip:
A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip |
| Verlag: | Springer |
| Seiten: | 175-192 |
| Erscheinungsjahr: | 2009 |
| Format: | Hardcover |
| » An Integrated SystemC Debugging Environment |
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Autor:
| Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke
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| Herausgeber: | Eugenio Villar |
| Buchtitel: | Embedded Systems Specification and Design Languages: Selected contributions from FDL'07 |
| Verlag: | Springer |
| Seiten: | 59-71 |
| Erscheinungsjahr: | 2008 |
| Format: | gebunden |
| » Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques |
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Autor:
| Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler
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| Herausgeber: | Eugenio Villar |
| Buchtitel: | Embedded Systems Specification and Design Languages: Selected contributions from FDL'07 |
| Verlag: | Springer |
| Seiten: | 73-86 |
| Erscheinungsjahr: | 2008 |
| Format: | gebunden |
| » Exact BDD Minimization for Path-Related Objective Functions |
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Autor:
| Rüdiger Ebendt, Rolf Drechsler
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| Herausgeber: | Ricardo Reis, Ada Osseiran, Hans-Jörg Pleiderer |
| Buchtitel: | VLSI-SoC: From Systems to Silicon |
| Verlag: | Springer |
| Seiten: | 299-315 |
| Erscheinungsjahr: | 2007 |
| Format: | gebunden |
| » Stuck-At-Fault Testability of SPP Three-Level Logic Forms |
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Autor:
| V. Ciriani, A. Bernasconi, Rolf Drechsler
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| Herausgeber: | M. Glesner, R. Reis, L. Indrusiak, V. Mooney, H. Eveking |
| Buchtitel: | VLSI-SOC: From Systems to Chips |
| Verlag: | Springer |
| Seiten: | 299-313 |
| Erscheinungsjahr: | 2006 |
| Format: | gebunden |
| » Exploration of Sequential Depth by Evolutionary Algorithms |
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Autor:
| Nicole Drechsler, Rolf Drechsler
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| Herausgeber: | M. Glesner, R. Reis, L. Indrusiak, V. Mooney, H. Eveking |
| Buchtitel: | VLSI-SOC: From Systems to Chips |
| Verlag: | Springer Boston |
| Seiten: | 73-83 |
| Erscheinungsjahr: | 2006 |
| Format: | gebunden |
| » Processor Verification |
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Autor:
| Daniel Große, Robert Siegmund, Rolf Drechsler
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| Herausgeber: | Paolo Ienne, Rainer Leupers |
| Buchtitel: | Customizable Embedded Processors |
| Verlag: | Elsevier |
| Seiten: | 281-302 |
| Erscheinungsjahr: | 2006 |
| Format: | gebunden |
| » Automatic Test Pattern Generation |
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Autor:
| Rolf Drechsler, Görschwin Fey
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| Herausgeber: | Marco Bernardo, Alessandro Cimatti |
| Buchtitel: | Formal Methods for Hardware Verification, LNCS 3965 |
| Verlag: | Springer |
| Seiten: | 30-55 |
| Erscheinungsjahr: | 2006 |
| Format: | gebunden |
| » System-level validation using formal techniques |
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Autor:
| Rolf Drechsler, Daniel Große
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| Herausgeber: | Bashir M. Al-Hashimi |
| Buchtitel: | System-on-Chip: Next Generation Electronics |
| Verlag: | The IEE |
| Seiten: | 715-745 |
| Erscheinungsjahr: | 2006 |
| Format: | gebunden |
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ZEITSCHRIFTEN |
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» RevKit: An Open Source Toolkit for the Design of Reversible Circuits
[Link zur Zeitschriften-Homepage]
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Autor:
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Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler |
| Zeitschrift: |
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Reversible Computation 2011 (Series: Lecture Notes in Computer Science) |
| Details: |
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Volume 7165, Third International Workshop, RC 2011, Revised Papers |
Jahr:
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2012
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» Automatic TLM Fault Localization for SystemC
[Link zur Zeitschriften-Homepage]
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Autor:
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Hoang M. Le, Daniel Große, Rolf Drechsler |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 31, Number 8, pp. 1249-1262,
DOI: 10.1109/TCAD.2012.2188800
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Jahr:
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2012
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» Special Issue on Reversible Computation
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler, Irek Ulidowski, Robert Wille (editors) |
| Zeitschrift: |
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Multiple-Valued Logic and Soft Computing |
| Details: |
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Volume 18, Number 1 |
Jahr:
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2012
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» RevKit: A Toolkit for Reversible Circuit Design
[Link zur Zeitschriften-Homepage]
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Autor:
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Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler |
| Zeitschrift: |
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Multiple-Valued Logic and Soft Computing |
| Details: |
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Volume 18, Number 1, pp. 55-65 |
Jahr:
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2012
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» A Highly Fault-Efficient SAT-Based ATPG Flow
[Link zur Zeitschriften-Homepage]
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Autor:
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Stephan Eggersglüß, Rolf Drechsler |
| Zeitschrift: |
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IEEE Design & Test of Computers |
| Details: |
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Volume 29, Issue 4 (July/August), pp. 63-70
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Jahr:
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2012
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» Efficient Data Structures and Methodologies for SAT-based ATPG providing High Fault Coverage in Industrial Application
[Link zur Zeitschriften-Homepage]
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Autor:
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Stephan Eggersglüß, Rolf Drechsler |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 30, Number 9, pp. 1411-1415,
DOI: 10.1109/TCAD.2011.2152450 |
Jahr:
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2011
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» Effective Robustness Analysis using Bounded Model Checking Techniques
[Link zur Zeitschriften-Homepage]
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Autor:
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Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 30, Number 8, pp. 1239-1252
DOI: 10.1109/TCAD.2011.2120950 |
Jahr:
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2011
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» Synthesis of Quantum Circuits for Linear Nearest Neighbor Architectures
[Link zur Zeitschriften-Homepage]
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Autor:
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Mehdi Saeedi, Robert Wille, Rolf Drechsler |
| Zeitschrift: |
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Quantum Information Processing |
| Details: |
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Volume 10, Number 3, pp. 355-377DOI: 10.1007/s11128-010-0201-2 |
Jahr:
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2011
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» Debugging Reversible Circuits
[Link zur Zeitschriften-Homepage]
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Autor:
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Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler |
| Zeitschrift: |
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INTEGRATION, the VLSI Journal |
| Details: |
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Volume 44, Number 1, pp. 51-61, JanuaryDOI: 10.1016/j.vlsi.2010.08.002 |
Jahr:
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2011
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» BDD-Based Synthesis of Reversible Logic
[Link zur Zeitschriften-Homepage]
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Autor:
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Robert Wille, Rolf Drechsler |
| Zeitschrift: |
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International Journal of Applied Metaheuristic Computing (IJAMC) |
| Details: |
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Volume 1, Number 4, pp. 25-41 |
Jahr:
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2010
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» Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen
[Link zur Zeitschriften-Homepage]
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Autor:
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Görschwin Fey, Andre Sülflow, Stefan Frehse, Rolf Drechsler |
| Zeitschrift: |
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it-Information Technology |
| Details: |
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Volume 52, Number 4, pp. 216-223
PDF Download |
Jahr:
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2010
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» Towards Fully Automatic Synthesis of Embedded Software
[Link zur Zeitschriften-Homepage]
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Autor:
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Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Zeitschrift: |
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IEEE Embedded Systems Letters |
| Details: |
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Volume 2, Number 3, pp. 53-57, September |
Jahr:
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2010
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» Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic
[Link zur Zeitschriften-Homepage]
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Autor:
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Robert Wille, Rolf Drechsler |
| Zeitschrift: |
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Electronic Notes in Theoretical Computer Science |
| Details: |
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Volume 253, Number 6, pp. 57-70DOI: 10.1016/j.entcs.2010.02.006 |
Jahr:
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2010
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» Incremental Solving Techniques for SAT-based ATPG
[Link zur Zeitschriften-Homepage]
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Autor:
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Daniel Tille, Stephan Eggersglüß, Rolf Drechsler |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 29, Number 7, pp. 1125-1130, July |
Jahr:
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2010
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» Synthese reversibler Logik
[Link zur Zeitschriften-Homepage]
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Autor:
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Robert Wille, Rolf Drechsler |
| Zeitschrift: |
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it-Information Technology |
| Details: |
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Volume 52, Number 1, pp. 30-38
PDF Download |
Jahr:
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2010
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» MONSOON: SAT-based ATPG for Path Delay Faults Using Multiple-Valued Logics
[Link zur Zeitschriften-Homepage]
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Autor:
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Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Rolf Drechsler |
| Zeitschrift: |
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Journal of Electronic Testing: Theory and Applications |
| Details: |
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Volume 26, Number 3 / June, pp. 307-322
Pdf download (Preliminary Version)
The final publication is available at www.springerlink.com |
Jahr:
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2010
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» Overcoming the limitations of data introspection for SystemC
[Link zur Zeitschriften-Homepage]
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Autor:
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Christian Genz, Rolf Drechsler |
| Zeitschrift: |
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EDA Tech Forum |
| Details: |
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Volume 6, Issue 5, Pages 30-34 (December 2009) |
Jahr:
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2009
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» Weighted A* search - unifying view and application
[Link zur Zeitschriften-Homepage]
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Autor:
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Rüdiger Ebendt, Rolf Drechsler |
| Zeitschrift: |
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Artificial Intelligence |
| Details: |
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Volume 173, Issue 15, Pages 1367-1456 (September 2009) |
Jahr:
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2009
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» Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille |
| Zeitschrift: |
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it - information technology |
| Details: |
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Volume 51, Number 2, pp. 102-111
Pdf download |
Jahr:
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2009
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» Exact Synthesis of Elementary Quantum Gate Circuits
[Link zur Zeitschriften-Homepage]
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Autor:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Zeitschrift: |
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Multiple-Valued Logic and Soft Computing |
| Details: |
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Volume 15, Number 4, pp. 283-300 |
Jahr:
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2009
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» Advanced Verification by Automatic Property Generation
[Link zur Zeitschriften-Homepage]
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Autor:
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Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke |
| Zeitschrift: |
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IET Computers & Digital Techniques |
| Details: |
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Volume 3, Issue 4, pp. 338-353, July |
Jahr:
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2009
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» Exact Multiple Control Toffoli Network Synthesis with SAT Techniques
[Link zur Zeitschriften-Homepage]
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Autor:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 28, Number 5, pp. 703-715, MayDOI: 10.1109/TCAD.2009.2017215 |
Jahr:
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2009
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» Modeling and Proving Completeness in Formal Verification of Counting Heads
[Link zur Zeitschriften-Homepage]
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Autor:
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Sebastian Kinder, Rolf Drechsler |
| Zeitschrift: |
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Software Tools for Technology Transfer (STTT)
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| Details: |
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Springer, Volume 10, Number 6, pp. 521 - 534 |
Jahr:
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2008
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» On Acceleration of SAT-based ATPG for Industrial Designs
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Daniel Tille |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 27, Number 7, pp. 1329-1333, July |
Jahr:
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2008
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» Improved SAT-based Reachability Analysis with Observability Don’t Cares
[Link zur Zeitschriften-Homepage]
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Autor:
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Sean Safarpour, Andreas Veneris and Rolf Drechsler |
| Zeitschrift: |
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Journal on Satisfiability, Boolean Modeling and Computation (JSAT) |
| Details: |
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Volume 5, pp. 1-25, Special Volume on Application of Constraints to Formal Verification |
Jahr:
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2008
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» On the Construction of Small Fully Testable Circuits with Low Depth
[Link zur Zeitschriften-Homepage]
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Autor:
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Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler |
| Zeitschrift: |
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Embedded Hardware Design - Microprocessors and Microsystems (MICPRO) |
| Details: |
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Special Issue, Volume 32, Issues 5-6, pp. 263-269 |
Jahr:
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2008
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» Logic Minimization and Testability of 2-SPP Networks
[Link zur Zeitschriften-Homepage]
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Autor:
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Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 27, Number 7, pp. 1190-1202, July |
Jahr:
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2008
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» Analyzing Functional Coverage in Bounded Model Checking
[Link zur Zeitschriften-Homepage]
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Autor:
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Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 27, Number 7, pp. 1305-1314, July |
Jahr:
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2008
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» Automatic Fault Localization for Property Checking
[Link zur Zeitschriften-Homepage]
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Autor:
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Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 27, Number 6, pp. 1138-1149, June |
Jahr:
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2008
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» BDD-based Verification of Scalable Designs
[Link zur Zeitschriften-Homepage]
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Autor:
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Daniel Große, Rolf Drechsler |
| Zeitschrift: |
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Facta Universitatis, Series: Electronics and Energetics |
| Details: |
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Volume 20, Number 3, pp. 367-379 |
Jahr:
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2007
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» Building Free Binary Decision Diagrams Using SAT Solvers
[Link zur Zeitschriften-Homepage]
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Autor:
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Robert Wille, Görschwin Fey, Rolf Drechsler |
| Zeitschrift: |
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Facta Universitatis, Series: Electronics and Energetics |
| Details: |
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Volume 20, Number 3, pp. 381-394, |
Jahr:
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2007
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» An Integrated Approach for Combining BDDs and SAT Provers
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler, Görschwin Fey, Sebastian Kinder |
| Zeitschrift: |
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Facta Universitatis, Series: Electronics and Energetics
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| Details: |
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Volume 20, Number 3, pp. 415-436 |
Jahr:
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2007
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» Technische Dokumentation von Soft- und Hardware in
eingebetteten Systemen
[Link zur Zeitschriften-Homepage]
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Autor:
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Beate Muranko, Rolf Drechsler |
| Zeitschrift: |
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it - information technology |
| Details: |
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Number 2, pp. 110-117
Pdf download |
Jahr:
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2007
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» Exact minimisation of path-related objective functions for binary decision diagrams
[Link zur Zeitschriften-Homepage]
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Autor:
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Rüdiger Ebendt, Rolf Drechsler |
| Zeitschrift: |
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IEE Proceedings Computer & Digital Techniques |
| Details: |
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Volume 153, Number 4, pp. 231-242, July |
Jahr:
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2006
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» Testability of SPP Three-Level Logic Networks in Static Fault Models
[Link zur Zeitschriften-Homepage]
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Autor:
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Valentina Ciriani, Anna Bernasconi, Rolf Drechsler |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 25, Number 10, pp. 2241-2248, October |
Jahr:
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2006
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» The Effect of Improved Lower Bounds in Dynamic BDD Reordering
[Link zur Zeitschriften-Homepage]
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Autor:
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Rüdiger Ebendt, Rolf Drechsler |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 25, Number 5, pp. 902-909, May |
Jahr:
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2006
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» Minimizing the Number of Paths in BDDs
- Theory and Algorithm
[Link zur Zeitschriften-Homepage]
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Autor:
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Görschwin Fey, Rolf Drechsler |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 25, Number 1, pp. 4-11, January |
Jahr:
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2006
|
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» Combining Ordered Best-First Search with Branch and Bound for Exact BDD Minimization
[Link zur Zeitschriften-Homepage]
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Autor:
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Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 24, Number 10, pp. 1515-1529, October |
Jahr:
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2005
|
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» System Level Validation Using Formal Techniques
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler, Daniel Große |
| Zeitschrift: |
|
IEE Proceedings Computer & Digital Techniques, Special Issue on Embedded Microelectronic Systems: Status and Trends |
| Details: |
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Volume 152, Number 3, pp. 393-406, May |
Jahr:
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2005
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» Generic Implementation of Multi-Valued Decision Diagram Packages
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Autor:
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Rolf Drechsler, Dragan Jankovic, Radomir Stankovic |
| Zeitschrift: |
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Multiple-Valued Logic and Soft Computing |
| Details: |
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Volume 11, Numbers 1-2, pp. 1-18 |
Jahr:
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2005
|
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» Project-Based Learning in Student Teams in Computer Science Education
[Link zur Zeitschriften-Homepage]
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Autor:
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Andreas Breiter, Görschwin Fey, Rolf Drechsler |
| Zeitschrift: |
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Facta Universitatis, Series: Electronics and Energetics
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| Details: |
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Volume 18, Number 2, August, pp. 165-180. |
Jahr:
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2005
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» Synthesis of Fully Testable Circuits from BDDs
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler, Junhao Shi, Görschwin Fey |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 23, Number 3, March |
Jahr:
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2004
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» Methods for Construction of Recursive Algorithms for Reed-Mulle-Fourier Polarity Matrices Calculation
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Autor:
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Dragan Jankovic, Rolf Drechsler |
| Zeitschrift: |
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Multiple-Valued Logic and Soft Computing |
| Details: |
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Volume 10, Numbers 1, pp. 29-50 |
Jahr:
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2004
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» Using Word-Level Information in Formal Hardware Verification
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler |
| Zeitschrift: |
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Automation and Remote Control |
| Details: |
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Jahr:
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Volume 65, Issue 6, pp. 963-977, June 2004
|
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» An Improved Branch and Bound Algorithm for Exact BDD Minimization
[Link zur Zeitschriften-Homepage]
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Autor:
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Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 22, Number 12, pp. 1657-1663, December |
Jahr:
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2003
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» Recursive Bi-Partitioning of Netlists for Large Number of Partitions
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst |
| Zeitschrift: |
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Journal of Systems Architecture - the Euromicro Journal |
| Details: |
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Volume 49, pp. 521-528 |
Jahr:
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2003
|
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» Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC
[Link zur Zeitschriften-Homepage]
|
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Autor:
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Daniel Große, Rolf Drechsler |
| Zeitschrift: |
|
it - information technology |
| Details: |
|
Number 4, pp. 219-226, August |
Jahr:
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2003
|
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» Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams
[Link zur Zeitschriften-Homepage]
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Autor:
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Wolfgang Günther, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computers |
| Details: |
|
Volume 52, Number 9, pp. 1196-1209, September |
Jahr:
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2003
|
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» Exact Routing with Search Space Reduction
[Link zur Zeitschriften-Homepage]
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Autor:
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Frank Schmiedle, Rolf Drechsler, Bernd Becker |
| Zeitschrift: |
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IEEE Transactions on Computers |
| Details: |
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Volume 52, Number 6, pp. 815-825, June |
Jahr:
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2003
|
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» Computer Architecture Core of Knowledge for Computer Science Studies
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Autor:
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M. Stojcev, I. Milentijevic, D. Kehagias, Rolf Drechsler, M. Gusev |
| Zeitschrift: |
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Cyprus Computer Society Journal |
| Details: |
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Volume I, Edition 4, April |
Jahr:
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2003
|
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» Polynomial Formal Verification of Multipliers
[Link zur Zeitschriften-Homepage]
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Autor:
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Martin Keim, Rolf Drechsler, Bernd Becker, Michael Martin, Paul Molitor |
| Zeitschrift: |
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Formal Methods in System Design: An International Journal |
| Details: |
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Volume 22, Issue 1, pp. 39-58 |
Jahr:
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2003
|
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» Low Power Optimization Techniques for BDD Mapped Circuits Using Temporal Correlation
[Link zur Zeitschriften-Homepage]
|
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Autor:
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Rolf Drechsler, Mikael Kerttu, Per Lindgren, Mitch Thornton |
| Zeitschrift: |
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Canadian Journal of Electrical and Computer Engineering |
| Details: |
|
Volume 27, Number 4, pp. 159-164, October |
Jahr:
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2002
|
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» Minimization of Word-level Decision Diagrams
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler, Wolfgang Günther, Stefan Höreth. |
| Zeitschrift: |
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INTEGRATION, the VLSI Journal |
| Details: |
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Volume 33, Issue 1-2, pp. 39-70 |
Jahr:
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2002
|
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» Minimization of Free BDDs
[Link zur Zeitschriften-Homepage]
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Autor:
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Wolfgang Günther, Rolf Drechsler |
| Zeitschrift: |
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INTEGRATION, the VLSI Journal |
| Details: |
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Volume 32, Issue 1-2, pp. 41-59 |
Jahr:
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2002
|
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» Verifying Integrity of Decision Diagrams
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler |
| Zeitschrift: |
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INTEGRATION, the VLSI Journal |
| Details: |
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Volume 32, Issue 1-2, pp. 61-75 |
Jahr:
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2002
|
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» Heuristic Learning based on Genetic Programming
[Link zur Zeitschriften-Homepage]
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Autor:
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Frank Schmiedle, Nicole Drechsler, Daniel Große and Rolf Drechsler |
| Zeitschrift: |
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Genetic Programming and Evolvable Machines |
| Details: |
|
Volume 3, pp. 363-388, December |
Jahr:
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2002
|
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» Dynamic Re-Encoding During MDD Minimization
[Link zur Zeitschriften-Homepage]
|
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Autor:
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Frank Schmiedle, Wolfgang Günther, Rolf Drechsler |
| Zeitschrift: |
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Multiple-Valued Logic - An International Journal |
| Details: |
|
Volume 8, Numbers 5-6, pp. 625-643 |
Jahr:
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2002
|
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» History-based Dynamic BDD Minimization
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler, Wolfgang Günther |
| Zeitschrift: |
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INTEGRATION, the VLSI Journal |
| Details: |
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Volume 31, Issue 1, pp. 51-63 |
Jahr:
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2001
|
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» Äquivalenzvergleich digitaler Schaltungen im industriellen Umfeld
|
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Autor:
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Rolf Drechsler |
| Zeitschrift: |
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it+ti - Informationstechnik und Technische Informatik |
| Details: |
|
Oldenbourg Wissenschaftsverlag, Number 4, pp. 200-205 |
Jahr:
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2001
|
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» Fault Simulation in Multi-Valued Logic Networks
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler, Martin Keim, Bernd Becker |
| Zeitschrift: |
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Multiple-Valued Logic - An International Journal |
| Details: |
|
Volume 7, Numbers 1-2, pp. 25-47 |
Jahr:
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2001
|
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» Binary Decision Diagrams in Theory and Practice
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler, Detlef Sieling |
| Zeitschrift: |
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Software Tools for Technology Transfer (STTT) |
| Details: |
|
Springer, Number 3, pp. 112-136 |
Jahr:
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2001
|
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» Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
[Link zur Zeitschriften-Homepage]
|
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Autor:
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Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker |
| Zeitschrift: |
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Journal of Electronic Testing, Theory and Application (JETTA) |
| Details: |
|
No. 17, pp. 37-51, February |
Jahr:
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2001
|
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» Decision Diagram Method for Calculation of Pruned Walsh Transform
[Link zur Zeitschriften-Homepage]
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Autor:
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|
Dragan Jankovic, Radomir Stankovic, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computers |
| Details: |
|
Volume 50, Number 2, pp. 147-157, February |
Jahr:
|
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2001
|
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» Using Lower Bounds during Dynamic BDD Minimization
[Link zur Zeitschriften-Homepage]
|
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Autor:
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|
Rolf Drechsler, Wolfgang Günther, Fabio Somenzi |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 20, Number 1, pp. 51-57, January |
Jahr:
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2001
|
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» ACTion: Combining Logic Synthesis and Technology Mapping for MUX based FPGAs
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Wolfgang Günther and Rolf Drechsler. |
| Zeitschrift: |
|
Journal of Systems Architecture - the Euromicro Journal |
| Details: |
|
Volume 46, Issue 14, pp. 1321-1334, December |
Jahr:
|
|
2000
|
|
» Boolean Function Representation and Spectral Characterization Using AND/OR Graphs
[Link zur Zeitschriften-Homepage]
|
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Autor:
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Alenka Zuzek, Rolf Drechsler, Mitch Thornton |
| Zeitschrift: |
|
INTEGRATION, the VLSI Journal |
| Details: |
|
Volume 29, Issue 2, pp. 101-116, September |
Jahr:
|
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2000
|
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» Genetic Algorithm for Minimization of fixed polarity Reed-Muller expressions
|
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Autor:
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Rolf Drechsler, Bernd Becker and Nicole Drechsler |
| Zeitschrift: |
|
IEE Proceedings Computers and Digital Techniques |
| Details: |
|
Volume 147, Number 5, September |
Jahr:
|
|
2000
|
|
» On the Computational Power of Linearly Transformed BDDs
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Wolfgang Günther, Rolf Drechsler |
| Zeitschrift: |
|
Information Processing Letters |
| Details: |
|
Volume 75, Nummer 3, pp. 119-125, August |
Jahr:
|
|
2000
|
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» Fast Exact Minimization of BDDs
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Rolf Drechsler, Nicole Drechsler, Wolfgang Günther |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 19, Number 3, pp. 384-389, March |
Jahr:
|
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2000
|
|
» Pseudo Kronecker Expressions for Symmetric Functions
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computers |
| Details: |
|
Volume 48, Number 9, pp. 987-990, September |
Jahr:
|
|
1999
|
|
» Testability of 2-Level AND/EXOR Circuits
[Link zur Zeitschriften-Homepage]
|
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Autor:
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Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker |
| Zeitschrift: |
|
Journal of Electronic Testing, Theory and Application (JETTA) |
| Details: |
|
Volume 14, Number 3, pp. 173-192, June |
Jahr:
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1999
|
|
» BDD Minimization Using Symmetries
[Link zur Zeitschriften-Homepage]
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Autor:
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Christoph Scholl, Dirk Möller, Paul Molitor, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 18, Number 2, pp. 81-100, February |
Jahr:
|
|
1999
|
|
» On Variable Ordering and Decomposition Type Choice in OKFDDs
[Link zur Zeitschriften-Homepage]
|
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|
|
Autor:
|
|
Rolf Drechsler, Bernd Becker, Andrea Jahnke |
| Zeitschrift: |
|
IEEE Transactions on Computers |
| Details: |
|
Volume 47, Number 12, December |
Jahr:
|
|
1998
|
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|
KONFERENZEN |
|
» Improved SAT-based ATPG: More Constraints, Better Compaction
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
IEEE/ACM International Conference on Computer-Aided Design (ICCAD) |
Referenz:
|
| San Jose, USA, 2013
| Hyperlink:
|
| [Link zur Konferenz]
|
» A Compact and Efficient SAT Encoding for Quantum Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Nils Przigoda, Rolf Drechsler |
| Konferenz: |
|
IEEE Africon |
Referenz:
|
| Mauritius, 2013
| Hyperlink:
|
| [Link zur Konferenz]
|
» Exploiting Reversibility in the Complete Simulation of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Simon Stelter, Rolf Drechsler |
| Konferenz: |
|
IEEE Africon |
Referenz:
|
| Mauritius, 2013
| Hyperlink:
|
| [Link zur Konferenz]
|
» Cone of Influence Analysis at the Electronic System Level Using Machine Learning
|
|
|
|
Autor:
|
|
Jannis Stoppe, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| Santander, Spain, 2013
| Hyperlink:
|
| [Link zur Konferenz]
|
» Minimal Stimuli Generation in Simulation-based Verification
|
|
|
|
Autor:
|
|
Shuo Yang, Robert Wille, Daniel Große and Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| Santander, Spain, 2013
| Hyperlink:
|
| [Link zur Konferenz]
|
» The SyReC Hardware Description Language:
Enabling Scalable Synthesis of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler |
| Konferenz: |
|
International Midwest Symposium on Circuits and Systems (MWSCAS) |
Referenz:
|
| Columbus, USA, 2013
| Hyperlink:
|
| [Link zur Konferenz]
|
» Incorporating User Preferences in Many-Objective Optimization using Relation Epsilon-Preferred
|
|
|
|
Autor:
|
|
Nicole Drechsler, André Sülflow, Rolf Drechsler |
| Konferenz: |
|
International Conference on Evolutionary Computation Theory and Applications (ECTA) |
Referenz:
|
| Vilamoura, Portugal, 2013
| Hyperlink:
|
| [Link zur Konferenz]
|
» Data Extraction from SystemC Designs using Debug Symbols and the SystemC API
|
|
|
|
Autor:
|
|
Jannis Stoppe, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| Natal, Brazil, 2013
| Hyperlink:
|
| [Link zur Konferenz]
|
» On the “Q” in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-structure
|
|
|
|
Autor:
|
|
Philipp Niemann, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Victoria, Canada, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Exploiting Negative Control Lines in the Optimization of Reversible Circuits
|
|
|
|
Autor:
|
|
Kamalika Datta, Gaurav Rathi, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Victoria, Canada, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure
|
|
|
|
Autor:
|
|
Arighna Deb, Debesh Kumar Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Victoria, Canada, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reducing the Depth of Quantum Circuits Using Additional Lines
|
|
|
|
Autor:
|
|
Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Victoria, Canada, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Hardware-Software Co-Visualization: Developing Systems in the Holodeck
|
|
|
|
Autor:
|
|
Rolf Drechsler, Mathias Soeken |
| Konferenz: |
|
16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| Karlovy Vary, Czech Republic, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Verifying SystemC using an Intermediate Verification Language and Symbolic Simulation
|
|
|
|
Autor:
|
|
Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| Austin, Texas, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Hongyan Zhang, Rolf Drechsler |
| Konferenz: |
|
43rd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Toyama, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Debugging of Reversible Circuits using πDDs
|
|
|
|
Autor:
|
|
Laura Tague, Mathias Soeken, Shin-ichi Minato, Rolf Drechsler |
| Konferenz: |
|
43rd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Toyama, 2013
| Hyperlink:
|
| [Link zur Konferenz]
|
» Exact Template Matching Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
43rd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Toyama, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Synchronized Debugging across Different Abstraction Levels in System Design
|
|
|
|
Autor:
|
|
Rolf Drechsler, Daniel Große, Hoang M. Le, André Sülflow |
| Konferenz: |
|
embedded world Conference 2013 |
Referenz:
|
| Nürnberg, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Scalable Fault Localization for SystemC TLM Designs
|
|
|
|
Autor:
|
|
Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE'13) |
Referenz:
|
| pp. 35-38, Grenoble, France, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Determining Relevant Model Elements for the Verification of UML/OCL Specifications
|
|
|
|
Autor:
|
|
Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Grenoble, France, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Towards a Generic Verification Methodology for System Models
|
|
|
|
Autor:
|
|
Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Grenoble, France, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Improving the Mapping of Reversible Circuits to Quantum Circuits Using Multiple Target Lines
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| Yokohama, Japan, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» An Evolutionary Approach to Reversible Logic Synthesis using Output Permutation
|
|
|
|
Autor:
|
|
Kamalika Datta, Indranil Sen Gupta, Hafizur Rahaman, Rolf Drechsler |
| Konferenz: |
|
IEEE Design and Test Symposium 2012 (IDT) |
Referenz:
|
| Doha, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Towards Dialog Systems for Assisted Natural Language Processing in the Design of Embedded Systems
|
|
|
|
Autor:
|
|
Rolf Drechsler, Mathias Soeken, Robert Wille |
| Konferenz: |
|
IEEE Design and Test Symposium 2012 (IDT) |
Referenz:
|
| Doha, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Synthesis of Reversible Circuits Using Decision Diagrams
|
|
|
|
Autor:
|
|
Rolf Drechsler, Robert Wille |
| Konferenz: |
|
International Symposium on Electronic System Design (ISED) |
Referenz:
|
| Kolkata, WB, India, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» SyDe - a New Graduate School for
System Design in an Excellent Setting
|
|
|
|
Autor:
|
|
Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Informatics Europe (ECSS) |
Referenz:
|
| Barcelona, 2012
| Hyperlink:
|
| [Link zur Konferenz]
|
» From Requirements and Scenarios to ESL Design in SystemC
|
|
|
|
Autor:
|
|
Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
International Symposium on Electronic System Design (ISED) |
Referenz:
|
| Kolkata, WB, India, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» FoREnSiC - An Automatic Debugging Environment for C Programs
|
|
|
|
Autor:
|
|
Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow
|
| Konferenz: |
|
Haifa Verification Conference (HVC) |
Referenz:
|
| Haifa, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» The System Verification Methodology for
Advanced TLM Verification
|
|
|
|
Autor:
|
|
Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler, Wolfgang Ecker, Volkan Esen |
| Konferenz: |
|
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) |
Referenz:
|
| pp. 313-322, Tampere, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Complete and Effective Robustness Checking by Means of Interpolation
|
|
|
|
Autor:
|
|
Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav and Rolf Drechsler |
| Konferenz: |
|
Formal Methods in Computer-Aided Design (FMCAD'12) |
Referenz:
|
| Cambridge, UK, 2012, page 82-90
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Completeness-Driven Development
|
|
|
|
Autor:
|
|
Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille |
| Konferenz: |
|
International Conference on Graph Transformation |
Referenz:
|
| pp. 38-50, Bremen, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC
|
|
|
|
Autor:
|
|
Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
International Symposium on System-on-Chip (SoC) |
Referenz:
|
| pp. 1-7, Tampere, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Localizing Features of ESL Models for Design Understanding
|
|
|
|
Autor:
|
|
Marc Michael, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Vienna, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Formal Specification Level: Towards Verification-driven Design Based on Natural Language Processing
|
|
|
|
Autor:
|
|
Rolf Drechsler, Mathias Soeken, Robert Wille |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 53-58, Vienna, Austria, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Circuit Line Minimization in the HDL-based Synthesis of Reversible Logic
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| pp. 213-218, Amherst, USA, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Coverage-driven Stimuli Generation
|
|
|
|
Autor:
|
|
Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
15th Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| Izmir, Turkey, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology
|
|
|
|
Autor:
|
|
Rolf Drechsler, Robert Wille |
| Konferenz: |
|
International Symposium on VLSI Design and Test (VDAT) |
Referenz:
|
| Shibpur, India, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Assisted Behavior Driven Development Using Natural Language Processing
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
50th International Conference on Objects, Models, Components, Patterns (TOOLS) |
Referenz:
|
| pp. 269-287, Prague, Czech Republic, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» A New SAT-based ATPG for Generating Highly Compacted Test Sets
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler |
| Konferenz: |
|
15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 230-235, Tallinn, Estonia, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits
|
|
|
|
Autor:
|
|
Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler |
| Konferenz: |
|
42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| 2012, Victoria
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» A Synthesis Flow for Sequential Reversible Circuits
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler |
| Konferenz: |
|
42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| 2012, Victoria
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler |
| Konferenz: |
|
42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Victoria, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler, Christof Oswald, Alberto Garcia-Ortiz |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Dresden, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» A Guiding Coverage Metric for Formal Verification
|
|
|
|
Autor:
|
|
Finn Haedicke, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Dresden, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Eliminating Invariants in UML/OCL Models
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1142-1145, Dresden, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Debugging of Inconsistent UML/OCL Models
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1078-1083, Dresden, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Synthesis of Reversible Circuits with Minimal Lines for Large Functions
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| pp. 85-92, Sydney, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Improved Fault Diagnosis for Reversible Circuits
|
|
|
|
Autor:
|
|
Hongyan Zhang, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Asian Test Symposium (ATS) |
Referenz:
|
| New Delhi, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Hochoptimierter Ablauf zur Robustheitsprüfung
|
|
|
|
Autor:
|
|
Stefan Frehse, Finn Haedicke, Melanie Diepenbeck, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) |
Referenz:
|
| Hamburg-Harburg, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Analyzing Dependability Measures at the Electronic System Level
|
|
|
|
Autor:
|
|
Marc Michael, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 1-8, Oldenburg, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Efficient Realization of Control Logic in Reversible Circuits
|
|
|
|
Autor:
|
|
Sebastian Offermann, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Oldenburg, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Determining Minimal Testsets for Reversible Circuits Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Hongyan Zhang, Stefan Frehse, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
10th IEEE Africon |
Referenz:
|
| Livingstone, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» VisSAT: Visualization of SAT Solver Internals for Computer Aided Hardware Verification
|
|
|
|
Autor:
|
|
Robert Wille, André Sülflow, Rolf Drechsler |
| Konferenz: |
|
International Conference on Modeling, Simulation and Visualization Methods (MSV) |
Referenz:
|
| pp. 36-39, Las Vegas, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» ATPG for Reversible Circuits Using Simulation,
Boolean Satisfiability, and Pseudo Boolean
Optimization
|
|
|
|
Autor:
|
|
Robert Wille, Hongyan Zhang, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| pp. 120-125, Chennai, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Encoding OCL Data Types for SAT-based Verification of UML/OCL Models
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
5th International Conference on Tests & Proofs (TAP) |
Referenz:
|
| pp. 152-170, Zurich, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Automatic Property Generation for the Formal Verification of Bus Bridges
|
|
|
|
Autor:
|
|
Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 417-422, Cottbus, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» TLM Protocol Compliance Checking at the Electronic System Level
|
|
|
|
Autor:
|
|
Mohamed Bawadekji, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 435-440, Cottbus, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Designing a RISC CPU in Reversible Logic
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler |
| Konferenz: |
|
41st International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 170-175, Tuusula, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits
|
|
|
|
Autor:
|
|
Rolf Drechsler, Robert Wille |
| Konferenz: |
|
41st International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 78-85, Tuusula, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Simulation-based Equivalence Checking between SystemC Models at different Levels of Abstraction
|
|
|
|
Autor:
|
|
Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 223-228, Lausanne, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Verifying Dynamic Aspects of UML Models
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1077-1082, Grenoble, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Determining the Minimal Number of Lines for Large Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Oliver Keszöcze, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1204-1207, Grenoble, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1291-1296, Grenoble, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Automatic Fault Localization for Programmable Logic Controllers
|
|
|
|
Autor:
|
|
Andre Sülflow, Rolf Drechsler |
| Konferenz: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT) |
Referenz:
|
| pp. 247-256, Braunschweig, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Robust Algorithms for High Quality Test Pattern Generation Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
International Test Conference (ITC) |
Referenz:
|
| pp. 1-10, Austin, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Polynomial Datapath Optimization using Constraint Solving and Formal Modelling
|
|
|
|
Autor:
|
|
Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler |
| Konferenz: |
|
IEEE/ACM International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| San Jose, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» SyReC: A Programming Language for Synthesis of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Sebastian Offermann, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 184-189, Southampton, 2010
Received Best Paper Award
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Proving Transaction and System-level Properties of Untimed SystemC TLM Designs
|
|
|
|
Autor:
|
|
Daniel Große, Hoang M. Le, Rolf Drechsler |
| Konferenz: |
|
International Conference on
Formal Methods and Models for Codesign (MEMOCODE) |
Referenz:
|
| pp. 113-122, Grenoble, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» RobuCheck: A Robustness Checker for Digital Circuits
|
|
|
|
Autor:
|
|
Stefan Frehse, Görschwin Fey, Andre Sülflow and Rolf Drechsler
|
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 226-231, Lille, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reducing the Number of Lines in Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| pp. 647-652, Anaheim, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Synthesizing Multiplier in Reversible Logic
|
|
|
|
Autor:
|
|
Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 335-340, Vienna, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Window Optimization of Reversible and Quantum Circuits
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 431-435, Vienna, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» A Better-Than-Worst-Case Robustness Measure
|
|
|
|
Autor:
|
|
Stefan Frehse, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 78-83, Vienna, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Enhancing Debugging of Multiple Missing Control Errors in Reversible Logic
|
|
|
|
Autor:
|
|
Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler
|
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 465-470, Rhode Island, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Improving CNF Representations in SAT-based ATPG for Industrial Circuits using BDDs
|
|
|
|
Autor:
|
|
Daniel Tille, Stephan Eggersglüß, René Krenz-Bååth, Juergen Schloeffel, Rolf Drechsler |
| Konferenz: |
|
15th IEEE European Test Symposium (ETS) |
Referenz:
|
| pp. 176-181, Prag, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions
|
|
|
|
Autor:
|
|
Alexander Finder, Rolf Drechsler |
| Konferenz: |
|
40th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 150-155, Barcelona, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Efficient Simulation-based Debugging of Reversible Logic
|
|
|
|
Autor:
|
|
Stefan Frehse, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
40th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 156-161, Barcelona, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reducing Reversible Circuit Cost by Adding Lines
|
|
|
|
Autor:
|
|
D. Michael Miller, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
40th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 217-222, Barcelona, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Efficient Test Generation with Maximal Crosstalk-Induced Noise using Unconstrained Aggressor Excitation
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS) |
Referenz:
|
| pp. 649-652, Paris, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Using QBF to Increase Accuracy of SAT-Based Debugging
|
|
|
|
Autor:
|
|
Andre Sülflow, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS) |
Referenz:
|
| pp.641-644, Paris, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Verifying UML/OCL Models Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1341-1344, Dresden, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Timing Arc Based Logic Analysis for False Noise Reduction
|
|
|
|
Autor:
|
|
Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler |
| Konferenz: |
|
IEEE/ACM International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| pp. 225-230, San Jose, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Anwendungsbezogene Analyse der Robustheit von Digitalen Schaltungen
|
|
|
|
Autor:
|
|
Andre Sülflow, Stefan Frehse, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) |
Referenz:
|
| pp. 45-52, Stuttgart, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Structural Heuristics for SAT-based ATPG
|
|
|
|
Autor:
|
|
Daniel Tille, Stephan Eggersglüß, Hoang M. Le, Rolf Drechsler |
| Konferenz: |
|
17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2009) |
Referenz:
|
| pp. 77-82, Florianópolis, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Speeding up SAT-based ATPG using Dynamic Clause Activation
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
| Konferenz: |
|
18th Asian Test Symposium (ATS'09) |
Referenz:
|
| pp. 177-182, Taichung, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Automatic Debugging of System-on-a-Chip Designs
|
|
|
|
Autor:
|
|
Frank Rogin, Rolf Drechsler, Steffen Rülke |
| Konferenz: |
|
IEEE International SOC Conference (SOCC) |
Referenz:
|
| Belfast, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» SMT-based Stimuli Generation in the SystemC Verification Library
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 1-6, Sophia Antipolis, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Robustness Check for Multiple Faults using Formal Techniques
|
|
|
|
Autor:
|
|
Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 85-90, Patras, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» BDD-based Synthesis of Reversible Logic for Large Functions
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| pp. 270-275, San Francisco, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Computing Bounds for Fault Tolerance using Formal Techniques
|
|
|
|
Autor:
|
|
Görschwin Fey, Andre Sülflow, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| pp. 190-195, San Francisco, USA, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» WoLFram - A Word Level Framework for Formal Verification
|
|
|
|
Autor:
|
|
Andre Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
IEEE/IFIP International Symposium on Rapid System Prototyping (RSP) |
Referenz:
|
| pp. 11-17, Paris, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» A Fast Untestability Proof for SAT-based ATPG
|
|
|
|
Autor:
|
|
Daniel Tille, Rolf Drechsler |
| Konferenz: |
|
12th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems |
Referenz:
|
| pp. 38-43, Liberec, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Increasing Robustness of SAT-based Delay Test Generation using Efficient Dynamic Learning Techniques
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
14th IEEE European Test Symposium (ETS) |
Referenz:
|
| pp. 81-86, Sevilla, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Contradictory Antecedent Debugging in Bounded Model Checking
|
|
|
|
Autor:
|
|
Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 173-176, Boston, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Evaluation of Cardinality Constraints on SMT-based Debugging
|
|
|
|
Autor:
|
|
Andre Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
39th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 298-303, Naha, Okinawa, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Equivalence Checking of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler |
| Konferenz: |
|
39th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 324-330, Naha, Okinawa, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Approximate BDD Minimization by Weighted A*
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'09) |
Referenz:
|
| Taipei, 2009
| Hyperlink:
|
| [Link zur Konferenz]
|
» Overcoming Limitations of the SystemC Data Introspection
|
|
|
|
Autor:
|
|
Christian Genz, Rolf Drechsler |
| Konferenz: |
|
Design Automation and Test in Europe (DATE)
|
Referenz:
|
| pp. 590-593, Nice, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Property Analysis and Design Understanding
|
|
|
|
Autor:
|
|
Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE)
|
Referenz:
|
| pp. 1246-1249, Nice, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Debugging of Toffoli Networks
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1284-1289, Nice, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Increasing the Accuracy of SAT-based Debugging
|
|
|
|
Autor:
|
|
Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1326-1332, Nice, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reversible Logic Synthesis with Output Permutation
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
22nd International Conference on VLSI Design |
Referenz:
|
| pp. 189-194, New Delhi, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Formaler Nachweis der Fehlertoleranz von Schaltkreisen
|
|
|
|
Autor:
|
|
Görschwin Fey, Andre Sülflow, Stefan Frehse, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
GMM/GI/ITG-Fachtagung: Zuverlässigkeit und Entwurf (ZuE 2008) |
Referenz:
|
| pp. 75-82, Ingolstadt, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Verification of PLC Programs using Formal Proof Techniques
|
|
|
|
Autor:
|
|
Andre Sülflow, Rolf Drechsler |
| Konferenz: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008) |
Referenz:
|
| pp. 43-50, Budapest, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Efficient Formal Verification of Track Vacancy Detection Sections
|
|
|
|
Autor:
|
|
Sebastian Kinder und Rolf Drechsler |
| Konferenz: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008)
|
Referenz:
|
| pp. 233-240, Budapest, 2008
| Hyperlink:
|
| [Link zur Konferenz]
|
» Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking
|
|
|
|
Autor:
|
|
Robert Wille, Görschwin Fey, Marc Messing, Gerhard
Angst, Lothar Linhard, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 542-549, Parma, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Contradiction Analysis for Constraint-based Random Simulation
|
|
|
|
Autor:
|
|
Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 130-135, Stuttgart, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| pp. 411-416, Montpellier, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» RevLib: An Online Resource for
Reversible Functions and Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Referenz:
|
| pp. 220-225, Dallas, 2008
RevLib is available at www.revlib.org
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Exact Synthesis of Elementary Quantum Gate
Circuits for Reversible Functions with Don’t Cares
|
|
|
|
Autor:
|
|
Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Referenz:
|
| pp. 214-219, Dallas, 2008
Received IEEE Young Researcher Award
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» On the Influence of Boolean Encodings in SAT-based ATPG for Path Delay Faults
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Referenz:
|
| pp. 94-99, Dallas, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Using Unsatisfiable Cores to Debug Multiple Design Errors
|
|
|
|
Autor:
|
|
Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
| Konferenz: |
|
IEEE Great Lakes Symposium on VLSI (GLSVLSI'08) |
Referenz:
|
| pp. 77-82, Orlando, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Process Variations Aware Robust on-Chip Bus Architecture Synthesis for MPSoCs
|
|
|
|
Autor:
|
|
Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'08) |
Referenz:
|
| Seattle, 2008
| Hyperlink:
|
| [Link zur Konferenz]
|
» A Basis for Formal Robustness Checking
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler
|
| Konferenz: |
|
International Symposium on Quality of Electronic Design (ISQED) |
Referenz:
|
| San Jose, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Adaptive Branch and Bound using SAT to Estimate False Crosstalk
|
|
|
|
Autor:
|
|
Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler
|
| Konferenz: |
|
International Symposium on Quality of Electronic Design (ISQED) |
Referenz:
|
| San Jose, 2008
| Hyperlink:
|
| [Link zur Konferenz]
|
» Automatic Generation of Complex Properties for Hardware Designs
|
|
|
|
Autor:
|
|
Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler Steffen Rülke |
| Konferenz: |
|
Design, Automation, and Test in Europe (DATE) |
Referenz:
|
| Munich, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs
|
|
|
|
Autor:
|
|
Sujan Pandey, Rolf Drechsler |
| Konferenz: |
|
Design, Automation, and Test in Europe (DATE) |
Referenz:
|
| Munich, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Robust On-Chip Bus architecture Synthesis for MPSoCs Under Random Tasks Arrival
|
|
|
|
Autor:
|
|
Sujan Pandey, Rolf Drechsler |
| Konferenz: |
|
13th Asia and South Pacific Design Automation Conference, (ASP-DAC 2008) |
Referenz:
|
| Seoul, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» SWORD: A SAT like Prover Using Word Level Information
|
|
|
|
Autor:
|
|
Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC) |
Referenz:
|
| pp. 88-93, Atlanta, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Co-Synthesis of Custom On-Chip Bus and Memory for
MPSoC Architectures
|
|
|
|
Autor:
|
|
Sujan Pandey, Christian Genz, Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration Systems and Systems on Chip (VLSI-SoC) |
Referenz:
|
| pp. 304-307, Atlanta, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Improving Test Pattern Compactness in SAT-based ATPG
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
16th Asian Test Symposium (ATS’07) |
Referenz:
|
| pp. 445-450, Beijing, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» An Integrated SystemC Debugging Environment
|
|
|
|
Autor:
|
|
Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke |
| Konferenz: |
|
Forum on Specification & Design Languages (FDL) |
Referenz:
|
| pp. 140-145, Barcelona, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Measuring the Quality of a SystemC Testbench by using Code Coverage Technqiues
|
|
|
|
Autor:
|
|
Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 146-151, Barcelona, 2007
Received Best Paper Award
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Proving Completeness of Properties in Formal Verification of Counting Heads for Railways
|
|
|
|
Autor:
|
|
Sebastian Kinder and Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD)
Architectures, Methods and Tools |
Referenz:
|
| Lübeck, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» On the Construction of Small Fully Testable Circuits with Low Depth
|
|
|
|
Autor:
|
|
Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD)
Architectures, Methods and Tools |
Referenz:
|
| Lübeck, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Hardware Project Management - What we Can Learn from the Software Development Process for Hardware Design?
|
|
|
|
Autor:
|
|
Rolf Drechsler, Andreas Breiter |
| Konferenz: |
|
2nd International Conference on Software and Data Technologies |
Referenz:
|
| Barcelona, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel |
| Konferenz: |
|
Fifth ACM-IEEE International Conference on
Formal Methods and Models for Codesign (MEMOCODE'2007) |
Referenz:
|
| pp. 181-187, Nice, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
|
|
|
|
Autor:
|
|
Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07) |
Referenz:
|
| pp. 165-170, Porto Alegre, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^m) in SystemC
|
|
|
|
Autor:
|
|
Andre Sülflow, Rolf Drechsler |
| Konferenz: |
|
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07) |
Referenz:
|
| pp. 42, Oslo, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL
|
|
|
|
Autor:
|
|
Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler |
| Konferenz: |
|
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07) |
Referenz:
|
| Oslo, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Experimental Studies on SAT-based ATPG for Gate Delay Faults
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
| Konferenz: |
|
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07) |
Referenz:
|
| Oslo, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Visualization of SystemC Designs
|
|
|
|
Autor:
|
|
Christian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS) |
Referenz:
|
| pp. 413-416,
New Orleans, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
| PS:
|
| [hier ansehen]
|
» SAT-based ATPG for Path Delay Faults in Sequential Circuits
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'07) |
Referenz:
|
| pp. 3671-3674, New Orleans, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Improvements for Constraint Solving in the SystemC Verification Library
|
|
|
|
Autor:
|
|
Daniel Große, Rüdiger Ebendt, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 493-496, Stresa, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Exact SAT-based Toffoli Network Synthesis
|
|
|
|
Autor:
|
|
Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 96-101, Stresa, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Ein formaler Ansatz zum Robustheitsnachweis
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
Zuverlässigkeit und Entwurf |
Referenz:
|
| München, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Robust Multi-Objective Optimization in High Dimensional Spaces
|
|
|
|
Autor:
|
|
André Sülflow, Nicole Drechsler, Rolf Drechsler |
| Konferenz: |
|
Fourth International Conference on Evolutionary Multi-Criterion Optimization |
Referenz:
|
| pp. 715-726, Matsushima, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Estimating Functional Coverage in Bounded Model Checking
|
|
|
|
Autor:
|
|
Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1176-1181, Nice, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Modeling and Formal Verification of Counting Heads for Railways
|
|
|
|
Autor:
|
|
Sebastian Kinder, Rolf Drechsler |
| Konferenz: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2007) |
Referenz:
|
| Braunschweig, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reusing Learned Information in SAT-based ATPG
|
|
|
|
Autor:
|
|
Görschwin Fey, Tim Warode, Rolf Drechsler |
| Konferenz: |
|
20th International Conference on VLSI Design |
Referenz:
|
| Bangalore, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Automatic Fault Localization for Property Checking
|
|
|
|
Autor:
|
|
Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
| Konferenz: |
|
Haifa Verification Conference |
Referenz:
|
| Haifa, 2006
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Technical Documentation of Software and Hardware
in Embedded Systems
|
|
|
|
Autor:
|
|
Beate Muranko, Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC 2006) |
Referenz:
|
| Nice, France 2006
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» A Framework for Quasi-Exact Optimization using Relaxed Best-First Search
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Rolf Drechsler |
| Konferenz: |
|
29th Annual German Conference on Artificial Intelligence (KI'06) |
Referenz:
|
| Bremen, 2006
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» HW/SW Co-Verification of Embedded Systems using Bounded Model Checking
|
|
|
|
Autor:
|
|
Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 43-48, Philadelphia, 2006
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Efficiency of Multiple-Valued Encoding in SAT-based ATPG
|
|
|
|
Autor:
|
|
Görschwin Fey, Junhao Shi, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multiple-Valued Logic (ISMVL '06) |
Referenz:
|
| Singapore, 2006
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Integrating Observability Don't Cares in All-Solution SAT Solvers
|
|
|
|
Autor:
|
|
Sean Safarpour, Andreas Veneris, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'06) |
Referenz:
|
| Kos, 2006
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» On the Sensitivity of BDDs with Respect to Path-Related Objective Functions
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'06) |
Referenz:
|
| Kos, 2006
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» System Exploration of SystemC Designs
|
|
|
|
Autor:
|
|
Christian Genz, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| pp. 335-340, Karlsruhe, 2006
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
| PS:
|
| [hier ansehen]
|
» On the Relation Between Simulation-based and SAT-based Diagnosis
|
|
|
|
Autor:
|
|
Görschwin Fey, Sean Safarpour, Andreas Veneris, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1139-1144, Munich, 2006
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Efficient Minimization of Fully Testable 2-SPP Networks
|
|
|
|
Autor:
|
|
Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1300-1305, Munich, 2006
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks
|
|
|
|
Autor:
|
|
Görschwin Fey, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1225-1226, Munich, 2006
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» An Integrated Approach for Combining BDD and SAT Provers
|
|
|
|
Autor:
|
|
Rolf Drechsler, Görschwin Fey, Sebastian Kinder |
| Konferenz: |
|
International Conference on VLSI Design |
Referenz:
|
| Hyderabad, 2006
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Experimental Studies on SAT-based Test Pattern Generation for Industrial Circuits
|
|
|
|
Autor:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke |
| Konferenz: |
|
International Conference on ASIC (ASICON 2005)
|
Referenz:
|
| pp. 967-970, Shanghai, 2005
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Post-Verification Debugging of Hierarchical Designs
|
|
|
|
Autor:
|
|
Moayad Ali, Sean Safarpour, Andreas Veneris, Magdy Abadir, Rolf Drechsler |
| Konferenz: |
|
IEEE International Conference on Computer Aided Design (ICCAD'05) |
Referenz:
|
| pp. 871-876, San Jose, 2005
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Exact BDD Minimization for Path-Related Objective Functions
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC 2005) |
Referenz:
|
| pp. 525-530, Perth, 2005
| Hyperlink:
|
| [Link zur Konferenz]
| PS:
|
| [hier ansehen]
|
» Acceleration of SAT-based Iterative Property Checking
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Correct Hardware Design and Verification Methods (CHARME) |
Referenz:
|
| pp. 349-353, Saarbrücken, 2005
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Quasi-Exact BDD Minimization using Relaxed Best-First Search
|
|
|
|
Autor:
|
|
Rüdiger Ebendt and Rolf Drechsler |
| Konferenz: |
|
IEEE Annual Symposium on VLSI (ISVLSI '05) |
Referenz:
|
| pp. 59-64, Tampa, Florida, 2005
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» PASSAT: Efficient SAT-based Test Pattern Generation
|
|
|
|
Autor:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
| Konferenz: |
|
IEEE Annual Symposium on VLSI (ISVLSI '05) |
Referenz:
|
| pp.212-217, Tampa, Florida, 2005
| Hyperlink:
|
| [Link zur Konferenz]
| PS:
|
| [hier ansehen]
|
» Controlling the Memory During Manipulation of Word-Level Decision Diagrams
|
|
|
|
Autor:
|
|
Sebastian Kinder, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL 2005) |
Referenz:
|
| pp. 250-255, Calgary, 2005
| Hyperlink:
|
| [Link zur Konferenz]
| PS:
|
| [hier ansehen]
|
» Utilizing Don't Care States in SAT-based Bounded Sequential Problems
|
|
|
|
Autor:
|
|
Sean Safarpour, Görschwin Fey, Andreas Veneris, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI'05) |
Referenz:
|
| Chicago, 2005
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» CheckSyC: An Efficient Property Checker for RTL SystemC Designs
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'05) |
Referenz:
|
| pp. 4167-4170, Kobe, 2005
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Bridging Fault Testability of BDD Circuits
|
|
|
|
Autor:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005) |
Referenz:
|
| pp. 188-191 Shanghai, 2005
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Lower Bounds for Dynamic BDD Reordering
|
|
|
|
Autor:
|
|
Rüdiger Ebendt and Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005) |
Referenz:
|
| pp. 579-582, Shanghai, 2005
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Automated Verification For Train Control Systems
|
|
|
|
Autor:
|
|
Jan Peleska, Daniel Große, Anne E. Haxthausen, Rolf Drechsler |
| Konferenz: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2004) |
Referenz:
|
| pp. 252-265, Braunschweig, 2004
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Debugging Sequential Circuits Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Moayad Ali, Andreas Veneris, Sean Safarpour, Magdy Abadir, Rolf Drechsler, Alexander Smith |
| Konferenz: |
|
IEEE International Conference on Computer Aided Design (ICCAD'04) |
Referenz:
|
| pp. 204-209, San Jose, 2004
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» BDD Circuit Optimization for Path Delay Fault Testability
|
|
|
|
Autor:
|
|
Görschwin Fey, Junhao Shi, Rolf Drechsler |
| Konferenz: |
|
Euromicro Symposium on Digital System Design (DSD'2004) |
Referenz:
|
| pp. 168-172, Rennes, 2004
| Hyperlink:
|
| [Link zur Konferenz]
| PS:
|
| [hier ansehen]
|
» Checkers for SystemC Designs
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Second ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2004) |
Referenz:
|
| pp. 171-178, San Diego, 2004
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reduction of Sizes of Multiple-Valued Decision Diagrams by Copy Properties
|
|
|
|
Autor:
|
|
Dragan Jankovic, Radomir Stankovic, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2004) |
Referenz:
|
| pp. 229-234, Toronto, 2004
| Hyperlink:
|
| [Link zur Konferenz]
|
» Algorithms for Taylor Expansion Diagrams
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler, Maciej Ciesielski |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2004) |
Referenz:
|
| pp. 235-240, Toronto, 2004
| Hyperlink:
|
| [Link zur Konferenz]
| PS:
|
| [hier ansehen]
|
» Placement and Routing Optimization for Circuits Derived from BDDs
|
|
|
|
Autor:
|
|
Thomas Eschbach, Rolf Drechsler, Bernd Becker |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'04) |
Referenz:
|
| Vancouver, 2004
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Managing Don't Cares in Boolean
Satisfiability
|
|
|
|
Autor:
|
|
Sean Safarpour, Andreas Veneris, Rolf Drechsler, Joanne Hang |
| Konferenz: |
|
IEEE Design, Automation and Test in Europe
|
Referenz:
|
| Vol. I, pp. 260-265, Paris, 2004
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Improving Simulation-Based Verification by Means of Formal Methods
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
|
Referenz:
|
| pp. 640-643, Yokohama, 2004
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Minimization of the Expected Path Length in BDDs Based on Local Changes
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
|
Referenz:
|
| pp. 866-871, Yokohama, 2004
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Combining Ordered Best-First Search with Branch and Bound for Exact BDD Minimization
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
|
Referenz:
|
| pp. 876-879, Yokohama, 2004
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Hardware Project Management – What we Can Learn from the Software Development Process for Hardware Design?
|
|
|
|
Autor:
|
|
Rolf Drechsler, Andreas Breiter |
| Konferenz: |
|
4th Conference of Informatics and Information Technologies |
Referenz:
|
| Bitola, 2003
| Hyperlink:
|
| [Link zur Konferenz]
|
» Minimizing the Number of One-Paths in BDDs by an Evolutionary Algorithm
|
|
|
|
Autor:
|
|
Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler |
| Konferenz: |
|
Congress on Evolutionary Computation 2003 (CEC2003) |
Referenz:
|
| Vol.3, pp.1724-1731, Canberra, 2003
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
| PS:
|
| [hier ansehen]
|
» Testability of SPP Three-Level Logic Networks
|
|
|
|
Autor:
|
|
Valentina Ciriani, Anna Bernasconi, Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (VLSI'03) |
Referenz:
|
| pp. 331-336, Darmstadt, 2003
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Exploration of Sequential Depth by Evolutionary Algorithms
|
|
|
|
Autor:
|
|
Nicole Drechsler, Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (VLSI'03) |
Referenz:
|
| pp. 81-85, Darmstadt, 2003
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
|
|
|
|
Autor:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
Twelfth Asian Test Symposium (ATS03)
|
Referenz:
|
| p.290-293,
Xi'an, 2003
| Hyperlink:
|
| [Link zur Konferenz]
| PS:
|
| [hier ansehen]
|
» Efficient Automatic Visualization of SystemC Designs
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst |
| Konferenz: |
|
Forum on Specification & Design Languages (FDL'03) |
Referenz:
|
| pp. 646-657, Frankfurt, 2003
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Finding Good Counter-Examples to Aid Design Verification
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
First ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2003) |
Referenz:
|
| pp. 51-52, Mont Saint-Michel, 2003
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
| PS:
|
| [hier ansehen]
|
» Fast Heuristics for the Edge Coloring of Large Graphs
|
|
|
|
Autor:
|
|
Mario Hilgemeier, Nicole Drechsler and Rolf Drechsler |
| Konferenz: |
|
Euromicro Symposium on Digital System Design (DSD'2003) |
Referenz:
|
| pp. 230-237, Antalya, 2003
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
| PS:
|
| [hier ansehen]
|
» MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits
|
|
|
|
Autor:
|
|
Rolf Drechsler, Junhao Shi and Görschwin Fey |
| Konferenz: |
|
IEEE Great Lakes Symposium on VLSI (GLSV'03) |
Referenz:
|
| p. 80-83, Washington, 2003
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
| PS:
|
| [hier ansehen]
|
» Efficient Minimization of Multi-Valued Decision Diagrams for Incompletely Specified Functions
|
|
|
|
Autor:
|
|
Denis Popel and Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003) |
Referenz:
|
| pp. 241-246, Tokyo, 2003
| Hyperlink:
|
| [Link zur Konferenz]
| PS:
|
| [hier ansehen]
|
» Augmented Sifting for Multiple-Valued Decision Diagrams
|
|
|
|
Autor:
|
|
Michael Miller and Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003) |
Referenz:
|
| pp. 375-382, Tokyo, 2003
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Modeling Multi-Valued Circuits in SystemC
|
|
|
|
Autor:
|
|
Daniel Große, Görschwin Fey and Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003) |
Referenz:
|
| pp. 281-286, Tokyo, 2003
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
| PS:
|
| [hier ansehen]
|
» Using Games for Benchmarking and Representing the Complete Solution Space Using Symbolic Techniques
|
|
|
|
Autor:
|
|
Görschwin Fey, Sebastian Kinder and Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2003) |
Referenz:
|
| pp. 361-366, Tokyo, 2003
| PS:
|
| [hier ansehen]
|
» Formal Verification of LTL Formulas for SystemC Designs
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'03) |
Referenz:
|
| pp. V:245-V:248, Bangkok, 2003
| PDF:
|
| [hier ansehen]
|
» Synthesizing Checkers for On-line Verification of System-on-Chip Designs
|
|
|
|
Autor:
|
|
Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'03) |
Referenz:
|
| pp. IV:748-IV:751, Bangkok, 2003
| PDF:
|
| [hier ansehen]
|
» Minimization of Transitions by Complementation and Resequencing using Evolutionary Algorithms
|
|
|
|
Autor:
|
|
Rolf Drechsler and Nicole Drechsler |
| Konferenz: |
|
21st IASTED International Multi-Conference Applied Informatics (AI 2003) |
Referenz:
|
| Innsbruck, 2003
| Hyperlink:
|
| [Link zur Konferenz]
| PS:
|
| [hier ansehen]
|
» Combination of Lower Bounds in Exact BDD Minimization
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Wolfgang Günther and Rolf Drechsler |
| Konferenz: |
|
IEEE Design, Automation and Test in Europe (DATE'03) |
Referenz:
|
| pp. 758-763, Munich, 2003
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Utilizing BDDs for disjoint SOP minimization
|
|
|
|
Autor:
|
|
Görschwin Fey and Rolf Drechsler |
| Konferenz: |
|
IEEE The 45rd Midwest Symposium on Circuits and Systems (MWSCAS'2002) |
Referenz:
|
| volume II, pages 306-309, Tulsa, 2002
| PS:
|
| [hier ansehen]
|
» Minimizing the Number of Paths in BDDs
|
|
|
|
Autor:
|
|
Görschwin Fey and Rolf Drechsler |
| Konferenz: |
|
15th Symposium on Integrated Circuits and System Design |
Referenz:
|
| pages 359-364, Porto Alegre, 2002
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
| PS:
|
| [hier ansehen]
|
» Crossing Reduction by Windows Optimization
|
|
|
|
Autor:
|
|
Thomas Eschbach, Wolfgang Günther, Rolf Drechsler and Bernd Becker |
| Konferenz: |
|
10th International Symposium on Graph Drawing (GD'2002) |
Referenz:
|
| LNCS 2528, pp. 285-294, Irvine, 2002
| PDF:
|
| [hier ansehen]
| PS:
|
| [hier ansehen]
|
» Reachability Analysis for Formal Verification of SystemC
|
|
|
|
Autor:
|
|
Rolf Drechsler and Daniel Große |
| Konferenz: |
|
Euromicro Symposium on Digital System Design (DSD'2002) |
Referenz:
|
| pages 337-340, Dortmund, 2002
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Decision Diagrams Optimization Using Copy Properties
|
|
|
|
Autor:
|
|
Dragan Jankovic, Radomir Stankovic and Rolf Drechsler |
| Konferenz: |
|
Euromicro Symposium on Digital System Design (DSD'2002) |
Referenz:
|
| pages 236-243, Dortmund, 2002
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Recursive Bi-Partitioning of Netlists for Large Number of Partitions
|
|
|
|
Autor:
|
|
Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard and Gerhard Angst |
| Konferenz: |
|
Euromicro Symposium on Digital System Design (DSD'2002) |
Referenz:
|
| pages 38-44, Dortmund, 2002
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» JADE: Implementation and Visualization of a BDD Package in JAVA
|
|
|
|
Autor:
|
|
Rolf Drechsler |
| Konferenz: |
|
IEEE Design, Automation and Test in Europe (DATE'02) - User Forum |
Referenz:
|
| page 259, Paris, 2002
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Computing Walsh, Arithmetic and Reed-Muller Spectral Decision Diagrams Using Graph Transformations
|
|
|
|
Autor:
|
|
Whitney Townsend, Mitch Thornton, Rolf Drechsler and Michael Miller |
| Konferenz: |
|
IEEE Great Lakes Symposium on VLSI (GLSV'02) |
Referenz:
|
| pp. 178-183, New York, 2002
| PDF:
|
| [hier ansehen]
|
» Switching Activity Estimation for Finite State Machines for Low Power Synthesis (Poster)
|
|
|
|
Autor:
|
|
Mikael Kerttu, Per Lindgren, Mitch Thornton and Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'02) |
Referenz:
|
| Scottsdale, 2002
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
| PS:
|
| [hier ansehen]
|
» Multi-Output Timed Shannon Circuits
|
|
|
|
Autor:
|
|
Mitch Thorton, Rolf Drechsler and Michael Miller |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002) |
Referenz:
|
| pages 47-52, Pittsburgh, 2002
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
| PS:
|
| [hier ansehen]
|
» Evaluation of Static Variable Ordering Heuristics for MDD Construction
|
|
|
|
Autor:
|
|
Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2002) |
Referenz:
|
| pages 254-260, Boston, 2002
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
| PS:
|
| [hier ansehen]
|
» On the Construction of Multi-Valued Decision Diagrams
|
|
|
|
Autor:
|
|
Michael Miller and Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2002) |
Referenz:
|
| pages 245-253, Boston, 2002
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Efficient Calculation of Fixed-Polarity Polynomial Expressions for Multi-Valued Logic Functions
|
|
|
|
Autor:
|
|
Dragan Jankovic, Radomir Stankovic and Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multi-Valued Logic (ISMVL'2002) |
Referenz:
|
| pages 76-82, Boston, 2002
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
| PS:
|
| [hier ansehen]
|
» On the Relation Between SAT and BDDs for Equivalence Checking
|
|
|
|
Autor:
|
|
Sherif Reda, Rolf Drechsler and Alex Orailoglu |
| Konferenz: |
|
International Symposium on Quality of Electronic Design (ISQED 2002) |
Referenz:
|
| pages 394-399, San Jose, 2002
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» RTL-Datapath Verification using Integer Linear Programming
|
|
|
|
Autor:
|
|
Raik Brinkmann and Rolf Drechsler |
| Konferenz: |
|
IEEE VLSI Design'02 & Asia and South Pacific Design Automation Conference |
Referenz:
|
| pages 741-746, Bangalore, 2002
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
| PS:
|
| [hier ansehen]
|
» Fast and Efficient Equivalence Checking based on NAND-BDDs
|
|
|
|
Autor:
|
|
Rolf Drechsler and Mitch Thornton |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (VLSI'01) |
Referenz:
|
| pages 401-405, Montpellier, 2001
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
| PS:
|
| [hier ansehen]
|
» Formal Verification on Register Transfer Level - Utilizing High-Level Information for Hardware Verification
|
|
|
|
Autor:
|
|
Peer Johannsen and Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (VLSI'01) |
Referenz:
|
| pages 127-132, Montpellier, 2001
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
| PS:
|
| [hier ansehen]
|
|
WORKSHOPS |
|
» lips: An IDE for Model Driven Engineering Based on Natural Language Processing
|
|
|
|
Autor:
|
|
Oliver Keszöcze, Mathias Soeken, Eugen Kuksa, Rolf Drechsler |
| Workshop: |
|
Workshop on Natural Language Analysis in Software Engineering (NaturaLiSE) |
Referenz:
|
| pp. 31-38, San Francisco, 2013
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Towards Automatic Scenario Generation from Coverage Information
|
|
|
|
Autor:
|
|
Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler |
| Workshop: |
|
8th International Workshop on Automation of Software Test (AST) |
Referenz:
|
| pp. 82-88, San Francisco, 2013
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» SystemC Verifikation mittels symbolischer Simulation einer Zwischensprache
|
|
|
|
Autor:
|
|
Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler |
| Workshop: |
|
edaWorkshop |
Referenz:
|
| pp. 53-58, Dresden, 2013
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Eugen Kuksa, Rolf Drechsler |
| Workshop: |
|
16. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
|
| Rostock, 2013
| Hyperlink:
|
| [Link zum Workshop]
|
» Verification of Embedded Systems Using Modeling and Implementation Languages
|
|
|
|
Autor:
|
|
Mathias Soeken, Heinz Riener, Robert Wille, Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
International Workshop on Metamodelling and Code Generation for Embedded Systems (MeCoEs'12) |
Referenz:
|
| pp. 67-72, Tampere, Finland, 2012
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Towards Increasing Test Compaction Abilities of SAT-based ATPG through Fault Detection Constraints
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Melanie Diepenbeck, Robert Wille, Rolf Drechsler |
| Workshop: |
|
IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12) |
Referenz:
|
| Niigata, Japan, 2012
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Behavior Driven Development for Circuit Design and Verification
|
|
|
|
Autor:
|
|
Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler |
| Workshop: |
|
IEEE International Workshop on High-Level Design Validation and Test (HLDVT) |
Referenz:
|
| Huntington Beach, USA, 2012
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Towards Embedding of Large Functions for Reversible Logic
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Laura Tague, D. Michael Miller, Rolf Drechsler |
| Workshop: |
|
International Workshop on Boolean Problems |
Referenz:
|
| Freiberg, 2012
| Hyperlink:
|
| [Link zum Workshop]
|
» Using πDDs in the Design for Reversible Circuits
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Shin-Ichi Minato, Rolf Drechsler |
| Workshop: |
|
Workshop on Reversible Computation |
Referenz:
|
| Kopenhagen, 2012
| Hyperlink:
|
| [Link zum Workshop]
|
» Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams
|
|
|
|
Autor:
|
|
Julia Seiter, Mathias Soeken, Robert Wille, Rolf Drechsler |
| Workshop: |
|
Workshop on Reversible Computation |
Referenz:
|
| Kopenhagen, 2012
| Hyperlink:
|
| [Link zum Workshop]
|
» Design Understanding by Feature Localization on ESL
|
|
|
|
Autor:
|
|
Marc Michael, Daniel Große, Rolf Drechsler |
| Workshop: |
|
9. GMM/ITG/GI-Workshop Cyber-Physical Systems – Enabling Multi-Nature Systems (CPMNS) |
Referenz:
|
| pp. 19-24, Dresden, 2012
| Hyperlink:
|
| [Link zum Workshop]
|
» Compilation of Methodologies to Speed up the Verification Process
at System Level
|
|
|
|
Autor:
|
|
Stephan Radke, Steffen Rülke, Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Müller, Wolfgang Ecker, Volkan Esen, Simon Hufnagel, Nico Bannow, Helmut Brazdrum, Peter Janssen, Hoang M. Le, Daniel Große, Rolf Drechsler, Erhard Fehlauer, Gernot Koch, Andreas Burger, Oliver Bringmann, Wolfgang Rosenstiel, Finn Haedicke, Ralph Görgen, Jan-Hendrik Oetjens |
| Workshop: |
|
edaWorkshop |
Referenz:
|
| pp. 57-62, Hannover, 2012
| Hyperlink:
|
| [Link zum Workshop]
|
» SystemC-based ESL Verification Flow
Integrating Property Checking and Automatic
Debugging
|
|
|
|
Autor:
|
|
Hoang M. Le, Daniel Große, Rolf Drechsler |
| Workshop: |
|
DATE Friday Workshop: OSCI and Accellera Core Technologies for the Next Generation of System-Level Design |
Referenz:
|
| Dresden, 2012
| Hyperlink:
|
| [Link zum Workshop]
|
» CRAVE: An Advanced Constrained Random Verification Environment for SystemC
|
|
|
|
Autor:
|
|
Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler |
| Workshop: |
|
15. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) |
Referenz:
|
| Kaiserslautern, 2012
Software and benchmarks available at www.systemc-verification.org
| Hyperlink:
|
| [Link zum Workshop]
|
» Towards Proving TLM Properties with Local Variables
|
|
|
|
Autor:
|
|
Hoang M. Le, Daniel Große, Rolf Drechsler |
| Workshop: |
|
7th International Workshop on Constraints in Formal Verification (CFV) |
Referenz:
|
| San Jose, 2011
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Towards Automatic Determination of Problem Bounds for Object Instantiation in Static Model Verification
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler |
| Workshop: |
|
Model-Driven Engineering, Verification, And Validation (MoDeVVa) |
Referenz:
|
| Wellington, 2011
| Hyperlink:
|
| [Link zum Workshop]
|
» metaSMT: Focus on Your Application not on Solver Integration
|
|
|
|
Autor:
|
|
Finn Haedicke, Stefan Frehse, Görschwin Fey, Daniel Große, Rolf Drechsler |
| Workshop: |
|
DIFTS'11: 1st International workshop on design and implementation of formal tools and systems |
Referenz:
|
| pp. 22-29, Austin, USA, 2011
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Synthesis of Reversible Circuits with Minimal Lines for Large Functions
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler |
| Workshop: |
|
Workshop on Reversible Computation |
Referenz:
|
| pp. 59-70, Gent, 2011
| Hyperlink:
|
| [Link zum Workshop]
|
» Customized Design Flows for Reversible Circuits Using RevKit
|
|
|
|
Autor:
|
|
Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler |
| Workshop: |
|
Workshop on Reversible Computation |
Referenz:
|
| pp. 91-96, Gent, 2011
| Hyperlink:
|
| [Link zum Workshop]
|
» Formal Analysis Techniques: A Basis for High-Quality Designs
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Workshop: |
|
IEEE International Workshop on Processor Verification, Test and Debug |
Referenz:
|
| Invited Talk, Trondheim, 2011
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» On Timing-Aware ATPG using Pseudo-Boolean Optimization
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Workshop: |
|
IEEE European Test Symposium (ETS), Informal Digest of Papers |
Referenz:
|
| Trondheim, 2011
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines
|
|
|
|
Autor:
|
|
Kim Grüttner, Andreas Herrholz, Ulrich Kühne, Daniel Große, Achim Rettberg, Wolfgang Nebel, Rolf Drechsler |
| Workshop: |
|
SORT 2011: 2nd IEEE Workshop on Self-Organizing Real-Time Systems |
Referenz:
|
| pp. 181-188, Newport Beach, 2011
| Hyperlink:
|
| [Link zum Workshop]
|
» Improving ESOP-based Synthesis of Reversible Logic Using Evolutionary Algorithms
|
|
|
|
Autor:
|
|
Rolf Drechsler, Alexander Finder, Robert Wille |
| Workshop: |
|
6th European Workshop on Hardware Optimization Techniques (EvoHOT) |
Referenz:
|
| Applications of Evolutionary Computation, LNCS 6625, pp. 151-161, Turin, 2011
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Protocol Compliance Checking of SystemC TLM Models
|
|
|
|
Autor:
|
|
Mohamed Bawadekji, Daniel Große, Rolf Drechsler |
| Workshop: |
|
8. GMM/ITG/GI-Workshop Cyber-Physical Systems – Enabling Multi-Nature Systems (CPMNS) |
Referenz:
|
| pp. 27-32, Bremen, 2011
| Hyperlink:
|
| [Link zum Workshop]
|
» Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction
|
|
|
|
Autor:
|
|
Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
|
14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
|
| pp. 269-278, Oldenburg, 2011
| Hyperlink:
|
| [Link zum Workshop]
|
» Designing a RISC CPU in Reversible Logic
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler |
| Workshop: |
|
14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
|
| pp. 249-258, Oldenburg, 2011
| Hyperlink:
|
| [Link zum Workshop]
|
» Towards Automatic Property Generation for the Formal Verification of Bus Bridges
|
|
|
|
Autor:
|
|
Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
|
| Oldenburg, 2011
| Hyperlink:
|
| [Link zum Workshop]
|
» As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Workshop: |
|
23. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2011 |
Referenz:
|
| Passau, 2011
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» SAT-based ATPG for Reversible Circuits
|
|
|
|
Autor:
|
|
Hongyan Zhang, Robert Wille, Rolf Drechsler |
| Workshop: |
|
5th International Design & Test Workshop (IDT) |
Referenz:
|
| pp. 149-154, Abu Dhabi, 2010
| Hyperlink:
|
| [Link zum Workshop]
|
» Hierarchical Synthesis of Reversible Circuits Using Positive and Negative Davio Decomposition
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler |
| Workshop: |
|
5th International Design & Test Workshop (IDT) |
Referenz:
|
| pp. 143-148, Abu Dhabi, 2010
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Automatic Fault Localization for SystemC TLM Designs
|
|
|
|
Autor:
|
|
Hoang M. Le, Daniel Große, Rolf Drechsler |
| Workshop: |
|
11th International Workshop on Microprocessor Test and Verification (MTV) |
Referenz:
|
| pp. 35-40, Austin, Texas, 2010
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Towards Unifying Localization and Explanation for Automated Debugging
|
|
|
|
Autor:
|
|
Görschwin Fey, André Sülflow, Rolf Drechsler |
| Workshop: |
|
11th International Workshop on Microprocessor Test and Verification (MTV) |
Referenz:
|
| pp. 3-8, Austin, Texas, 2010
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» RevKit: A Toolkit for Reversible Circuit Design
|
|
|
|
Autor:
|
|
Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler |
| Workshop: |
|
Workshop on Reversible Computation |
Referenz:
|
| pp. 69-72, Bremen, 2010
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Hierarchical Synthesis of Reversible Circuits Using Positive and Negative Davio Decomposition
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler |
| Workshop: |
|
Workshop on Reversible Computation |
Referenz:
|
| pp. 55-58, Bremen, 2010
| Hyperlink:
|
| [Link zum Workshop]
|
» Towards Analyzing Functional Coverage in SystemC TLM Property Checking
|
|
|
|
Autor:
|
|
Hoang M. Le, Daniel Große, Rolf Drechsler |
| Workshop: |
|
IEEE International Workshop on High-Level Design Validation and Test (HLDVT) |
Referenz:
|
| pp. 67-74, Anaheim, 2010
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» SyReC: A Programming Language for Synthesis of
Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Sebastian Offermann, Rolf Drechsler |
| Workshop: |
|
International Workshop on Logic Synthesis (IWLS) |
Referenz:
|
| Irvine, 2010
| Hyperlink:
|
| [Link zum Workshop]
|
» Technische Dokumentation im V-Modell XT
|
|
|
|
Autor:
|
|
Beate Kapturek, Rolf Drechsler
|
| Workshop: |
|
17. Workshop der Fachgruppe WI-VM der Gesellschaft für Informatik e.V. |
Referenz:
|
| Stuttgart, 2010
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» RobuCheck: A Robustness Checker for Digital Circuits
|
|
|
|
Autor:
|
|
Stefan Frehse, Görschwin Fey, Andre Sülflow and Rolf Drechsler
|
| Workshop: |
|
The First International Workshop on Dynamic Aspects
in Dependability Models for Fault-Tolerant Systems (DYADEM-FTS) |
Referenz:
|
| Valencia, 2010
| Hyperlink:
|
| [Link zum Workshop]
|
» VisSAT: Visualization of SAT Solver Internals
|
|
|
|
Autor:
|
|
Robert Wille, Andre Sülflow, Christian Genz, Rolf Drechsler |
| Workshop: |
|
University Booth at Design, Automation and Test in Europe (DATE10) |
Referenz:
|
| Dresden, 2010
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» A Better-Than-Worst-Case Robustness Measure
|
|
|
|
Autor:
|
|
Stefan Frehse,
Görschwin Fey,
Rolf Drechsler |
| Workshop: |
|
22. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2010 |
Referenz:
|
| Paderborn, 2010
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» SyReC: A Programming Language for Synthesis of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Sebastian Offermann, Rolf Drechsler |
| Workshop: |
|
13. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
|
| Dresden, 2010
| Hyperlink:
|
| [Link zum Workshop]
|
» Verifying UML/OCL Models Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler |
| Workshop: |
|
13. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
|
| pp 57-66, Dresden, 2010
| Hyperlink:
|
| [Link zum Workshop]
|
» Induction-based Formal Verification of SystemC TLM Designs
|
|
|
|
Autor:
|
|
Daniel Große, Hoang M. Le, Rolf Drechsler |
| Workshop: |
|
10th International Workshop on Microprocessor Test and Verification (MTV) |
Referenz:
|
| pp. 101-106, Austin, Texas, 2009
| Hyperlink:
|
| [Link zum Workshop]
|
» Using QBF to Increase the Accuracy of SAT-Based Debugging
|
|
|
|
Autor:
|
|
Andre Sülflow, Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
International Workshop on Constraints in Formal Verification (CFV) |
Referenz:
|
| Grenoble, France, 2009
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Reducing Reversible Circuit Cost by Adding Lines
|
|
|
|
Autor:
|
|
D. Michael Miller, Robert Wille, Rolf Drechsler |
| Workshop: |
|
International Workshop on Logic Synthesis (IWLS) |
Referenz:
|
| Berkeley, 2009
| Hyperlink:
|
| [Link zum Workshop]
|
» Synthesis of Reversible Functions Beyond Gate Count and Quantum Cost
|
|
|
|
Autor:
|
|
Robert Wille, Mehdi Saeedi, Rolf Drechsler |
| Workshop: |
|
International Workshop on Logic Synthesis (IWLS) |
Referenz:
|
| Berkeley, 2009
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Model-Based Diagnosis for Programmable Logic Controllers
|
|
|
|
Autor:
|
|
Andre Sülflow, Rolf Drechsler |
| Workshop: |
|
Gemeinsamer Workshop der Informatik-Graduiertenkollegs und Forschungskollegs |
Referenz:
|
| Dagstuhl, 2009
|
» A Two-Stage SAT-based ATPG Approach with Reduced Switching Activity
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
| Workshop: |
|
Second International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR) 2009 |
Referenz:
|
| Sevilla, Spain, 2009
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Robustness Check for Multiple Faults using Formal Techniques
|
|
|
|
Autor:
|
|
Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler |
| Workshop: |
|
Constraints in Formal Verification (CFV) |
Referenz:
|
| Grenoble, France, 2009
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Synthesizing Reversible Logic: An Overview
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler |
| Workshop: |
|
Reed-Muller Workshop |
Referenz:
|
| Naha, Okinawa, 2009
| Hyperlink:
|
| [Link zum Workshop]
|
» FormED: A Formal Environment for Debugging
|
|
|
|
Autor:
|
|
Andre Sülflow, Robert Wille, Christian Genz, Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
University Booth at Design, Automation and Test in Europe (DATE09) |
Referenz:
|
| Nizza, 2009
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler |
| Workshop: |
|
Reversible Computation |
Referenz:
|
| York, 2009
| Hyperlink:
|
| [Link zum Workshop]
|
» A Fast Untestability Proof for SAT-based ATPG
|
|
|
|
Autor:
|
|
Daniel Tille, Rolf Drechsler |
| Workshop: |
|
21. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2009 |
Referenz:
|
| Bremen, 2009
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Using a Two-Dimensional Fault List for Compact Automatic Test Pattern Generation
|
|
|
|
Autor:
|
|
Marc Messing, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler |
| Workshop: |
|
10th IEEE Latin-American TestWorkshop (LATW) |
Referenz:
|
| Búzios, Rio de Janeiro, 2009
| Hyperlink:
|
| [Link zum Workshop]
|
» Increasing the Accuracy of SAT-based Debugging
|
|
|
|
Autor:
|
|
Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
|
12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
|
| pp. 47-56, Berlin, 2009
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Equivalence Checking of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler |
| Workshop: |
|
12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
|
| 2009
| Hyperlink:
|
| [Link zum Workshop]
|
» Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow
|
|
|
|
Autor:
|
|
Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Workshop: |
|
9th International Workshop on Microprocessor Test and Verification (MTV) |
Referenz:
|
| pp. 88-93, Austin, Texas, 2008
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Computing Bounds for Fault Tolerance using Formal Techniques
|
|
|
|
Autor:
|
|
Andre Sülflow, Görschwin Fey, Stefan Frehse, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
|
IEEE Workshop on Design for Reliability and Variability (DRV) |
Referenz:
|
| Santa Clara, USA, 2008
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Experimental Studies on SMT-based Debugging
|
|
|
|
Autor:
|
|
Andre Sülflow, Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
IEEE 9th Workshop on RTL and High Level Testing (WRTLT'08) |
Referenz:
|
| pp. 93-98, Japan, 2008
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Reversible Logic Synthesis with Output Permutation
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
| Workshop: |
|
International Workshop on Boolean Problems |
Referenz:
|
| Freiberg, 2008
| Hyperlink:
|
| [Link zum Workshop]
|
» Effiziente automatische Generierung von Assertions für industrielle Hardware-Designs
|
|
|
|
Autor:
|
|
Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke |
| Workshop: |
|
Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS) |
Referenz:
|
| Dresden, 2008
| Hyperlink:
|
| [Link zum Workshop]
|
» Contradiction Analysis for Constraint-based Random Simulation
|
|
|
|
Autor:
|
|
Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler |
| Workshop: |
|
Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS)
|
Referenz:
|
| pp. 25-30, Dresden, 2008
| Hyperlink:
|
| [Link zum Workshop]
|
» Robust Tests for Transition Faults with Long Propagation Paths Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
|
| Workshop: |
|
IEEE European Test Symposium (ETS), Informal Digest of Papers |
Referenz:
|
| Lago Maggiore, 2008
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Formale Modellextraktion von SystemC Entwürfen
|
|
|
|
Autor:
|
|
Christian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard
|
| Workshop: |
|
edaWorkshop |
Referenz:
|
| pp. 7-12, Hannover 2008
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Incremental SAT Instance Generation for SAT-based ATPG
|
|
|
|
Autor:
|
|
Daniel Tille, Rolf Drechsler |
| Workshop: |
|
11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems |
Referenz:
|
| pp. 68-73, Bratislava, 2008
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking
|
|
|
|
Autor:
|
|
Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
|
11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen
zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
|
| pp. 169-178, Freiburg, 2008
| Hyperlink:
|
| [Link zum Workshop]
|
» Debugging Design Errors by Using Unsatisfiable Cores
|
|
|
|
Autor:
|
|
Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
| Workshop: |
|
11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen
zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
|
| pp. 159-168, Freiburg, 2008
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» False Noise Analysis Using Branch & Bound and SAT
|
|
|
|
Autor:
|
|
Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler |
| Workshop: |
|
ACM/IEEE International Workshop on Timing
Issues in the Specification and Synthesis of Digital Systems
(TAU 2008) |
Referenz:
|
| Monterey, 2008
| Hyperlink:
|
| [Link zum Workshop]
|
» Improved Circuit-to-CNF Transformation for SAT-based ATPG
|
|
|
|
Autor:
|
|
Daniel Tille, René Krenz-Bååth, Jürgen Schlöffel, Rolf Drechsler |
| Workshop: |
|
20. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
|
Referenz:
|
| Wien, 2008
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits
|
|
|
|
Autor:
|
|
Andre Sülflow, Ulrich Kühne, Robert Wille, Daniel Große, Rolf Drechsler |
| Workshop: |
|
IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07) |
Referenz:
|
| pp. 31-36, Beijing, P.R.China, 2007
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Formal Robustness Checking
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
Workshop on Constraints in Formal Verification, 2007 |
Referenz:
|
| Bremen, 2007
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
|
|
|
|
Autor:
|
|
Rolf Drechsler, Görschwin Fey, Jürgen Schlöffel |
| Workshop: |
|
edaWorkshop 2007 |
Referenz:
|
| Hannover, 2007
| Hyperlink:
|
| [Link zum Workshop]
|
» Parallelisierung von SAT-basierter Testmustergenerierung
|
|
|
|
Autor:
|
|
Daniel Tille, Robert Wille, Rolf Drechsler |
| Workshop: |
|
21. Workshop der GI/ITG-Fachgruppe Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS 2007) |
Referenz:
|
| pp. 213-217, Hamburg, 2007
| Hyperlink:
|
| [Link zum Workshop]
|
» Building Free Binary Decision Diagrams Using SAT Solvers
|
|
|
|
Autor:
|
|
Robert Wille, Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
8th Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM2007) |
Referenz:
|
| Oslo, 2007
| Hyperlink:
|
| [Link zum Workshop]
|
» SAT-based ATPG for Path Delay Fault in Industrial Circuits
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel |
| Workshop: |
|
IEEE European Test Symposium (ETS), Informal Digest of Papers |
Referenz:
|
| Freiburg, 2007
| Hyperlink:
|
| [Link zum Workshop]
|
» Estimating the Quality of AND-EXOR Optimization Results
|
|
|
|
Autor:
|
|
Sebastian Kinder, Görschwin Fey and Rolf Drechsler |
| Workshop: |
|
8th Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM2007) |
Referenz:
|
| Oslo, 2007
| Hyperlink:
|
| [Link zum Workshop]
|
» Documentation Driven Software Development for
Embedded Systems
|
|
|
|
Autor:
|
|
Beate Muranko, Rolf Drechsler |
| Workshop: |
|
14. Workshop der Fachgruppe WI-VM der Gesellschaft für Informatik e.V. Vorgehensmodelle und Projektmanagement
- Assessment, Zertifizierung, Akkreditierung - |
Referenz:
|
| München, 2007
| PDF:
|
| [hier ansehen]
|
» Studies on Integrating SAT-based ATPG in an Industrial Environment
|
|
|
|
Autor:
|
|
Daniel Tille, Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
| Workshop: |
|
19. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
|
Referenz:
|
| Erlangen, 2007
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Instance Generation for SAT-based ATPG
|
|
|
|
Autor:
|
|
Daniel Tille, Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems |
Referenz:
|
| Krakau, 2007
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Visualized SystemC Debugging
|
|
|
|
Autor:
|
|
Christian Genz, Frank Rogin, Rolf Drechsler, Steffen Rülke |
| Workshop: |
|
University Booth at Design, Automation and Test in Europe (DATE07) |
Referenz:
|
| Nizza, 2007
| PDF:
|
| [hier ansehen]
|
» Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
|
|
|
|
Autor:
|
|
Rolf Drechsler |
| Workshop: |
|
Treffen der ASIM/GI-Fachgruppen "Simulation technischer Systeme" und "Grundlagen und Methoden in Modellbildung und Simulation" |
Referenz:
|
| Bremen, 2007
| Hyperlink:
|
| [Link zum Workshop]
|
» Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse
|
|
|
|
Autor:
|
|
Andre Sülflow, Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Referenz:
|
| pp. 101-110, Erlangen, 2007
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Formal Verification on the Word Level using SAT-like Proof
Techniques
|
|
|
|
Autor:
|
|
Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Referenz:
|
| pp. 165-173, Erlangen, 2007
| Hyperlink:
|
| [Link zum Workshop]
|
» Efficient Design-Flow for Counting Heads
|
|
|
|
Autor:
|
|
Sebastian Kinder und Rolf Drechsler |
| Workshop: |
|
8. Bieleschweig Workshop „Systems Engineering”:
Modellbasierte Entwicklung & Human-Centered Engineering |
Referenz:
|
| Braunschweig 2006
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Exact Toffoli Network Synthesis of Reversible Logic using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Daniel Große, Xiaobo Chen, Rolf Drechsler |
| Workshop: |
|
Fifth IEEE Dallas Circuits and Systems Workshop |
Referenz:
|
| pp. 51-54, Dallas, 2006
| Hyperlink:
|
| [Link zum Workshop]
|
» Complete Formal Verification of Multi Core Embedded Systems using Bounded Model Checking
|
|
|
|
Autor:
|
|
Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Workshop: |
|
Fifth IEEE Dallas Circuits and Systems Workshop |
Referenz:
|
| pp. 147-150, Dallas, 2006
| Hyperlink:
|
| [Link zum Workshop]
|
» Efficiency of Multi-Valued Encoding in SAT-based ATPG
|
|
|
|
Autor:
|
|
Görschwin Fey, Junhao Shi , Rolf Drechsler |
| Workshop: |
|
18. Workshop „Testmethoden und Zuverlässigkeit von Schaltungen und Systemen“
|
Referenz:
|
| Titisee, 2006
|
» Technische Dokumentation von Soft- und Hardware-Systemen:
Die vergessene Welt
|
|
|
|
Autor:
|
|
Beate Muranko, Rolf Drechsler |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Referenz:
|
| Dresden, 2006
| PDF:
|
| [hier ansehen]
|
» SAT-Based Calculation of Source Code Coverage for BMC
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Referenz:
|
| Dresden, 2006
| PDF:
|
| [hier ansehen]
|
» Efficient Evolutionary Approaches for the Data Ordering Problem with Inversion
|
|
|
|
Autor:
|
|
Doina Logofatu, Rolf Drechsler |
| Workshop: |
|
3rd European Workshop on Hardware Optimisation Techniques (EvoHOT) |
Referenz:
|
| LNCS 3907, pp. 320-331, Budapest, 2006
| Hyperlink:
|
| [Link zum Workshop]
|
» HW/SW Co-Verification of a RISC CPU using Bounded Model Checking
|
|
|
|
Autor:
|
|
Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
|
6th International Workshop on Microprocessor Test and Verification (MTV'05) |
Referenz:
|
| pp. 133-137, Austin, 2005
| PDF:
|
| [hier ansehen]
|
» Bounded Model Checking mit SystemC
|
|
|
|
Autor:
|
|
Sebastian Kinder, Rolf Drechsler, Jan Peleska |
| Workshop: |
|
Bieleschweig 6 - Workshop "Systems Engineering" |
Referenz:
|
| Braunschweig, 2005
|
» Bounded Model Checking of Tram Control Systems
|
|
|
|
Autor:
|
|
Sebastian Kinder, Daniel Große, Jan Peleska, Rolf Drechsler |
| Workshop: |
|
TRain Workshop @ SEFM2005 |
Referenz:
|
| Koblenz, 2005
|
» Formale Verifikation des Befehlssatzes eines in SystemC modellierten Mikroprozessors
|
|
|
|
Autor:
|
|
Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
|
Entwurfsmethoden für Nanometer VLSI Design |
Referenz:
|
| pp. 308-312, Bonn, 2005
| PDF:
|
| [hier ansehen]
|
» On the Exact Minimization of Path-Related Objective Functions for BDDs
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Rolf Drechsler |
| Workshop: |
|
International Workshop on Logic and Synthesis (IWLS'05) |
Referenz:
|
| pp. 333-400, Lake Arrowhead, California, 2005
| PDF:
|
| [hier ansehen]
|
» Acceleration of SAT-based Iterative Property Checking
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Referenz:
|
| München, 2005
| PDF:
|
| [hier ansehen]
|
» Modellierung eines Mikroprozessors in SystemC
|
|
|
|
Autor:
|
|
Daniel Große, Ulrich Kühne, Christian Genz, Frank Schmiedle, Bernd Becker, Rolf Drechsler, Paul Molitor |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Referenz:
|
| München, 2005
| PDF:
|
| [hier ansehen]
|
» SyCE: An Integrated Environment for System Design in SystemC
|
|
|
|
Autor:
|
|
Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große |
| Workshop: |
|
16th IEEE International Workshop on Rapid System Prototyping (RSP) |
Referenz:
|
| pp. 258-260, Montreal, 2005
| PDF:
|
| [hier ansehen]
|
» PASSAT: Efficient SAT-based Test Pattern Generation
|
|
|
|
Autor:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
| Workshop: |
|
IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| Sopron, 2005
| PS:
|
| [hier ansehen]
|
» Efficient Hierarchical System Debugging for Property Checking
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| Sopron, 2005
| PDF:
|
| [hier ansehen]
|
» ParSyC: An Efficient SystemC Parser
|
|
|
|
Autor:
|
|
Görschwin Fey, Daniel Große, Tim Cassens, Christian Genz, Tim Warode, Rolf Drechsler |
| Workshop: |
|
12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2004) |
Referenz:
|
| pp. 148-154, Kanazawa, 2004
| PDF:
|
| [hier ansehen]
|
» Design Understanding by Automatic Property Generation
|
|
|
|
Autor:
|
|
Rolf Drechsler, Görschwin Fey |
| Workshop: |
|
12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2004) |
Referenz:
|
| pp.274-281, Kanazawa, 2004
| PDF:
|
| [hier ansehen]
|
» Debugging Sequential Circuits Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Moayad Ali, Andreas Veneris, Sean Safarpour, Magdy Abadir, Rolf Drechsler, Alexander Smith |
| Workshop: |
|
5th International Workshop on Microprocessor Test and Verification (MTV'04) |
Referenz:
|
| Austin, 2004
|
» Experimental Studies on Test Pattern Generation for BDD Circuits
|
|
|
|
Autor:
|
|
Junhao Shi, Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
International Workshop on Boolean Problems (IWSBP) |
Referenz:
|
| pp. 71-76, Freiberg, 2004
| PDF:
|
| [hier ansehen]
|
» Towards Formal Verification on the System Level
|
|
|
|
Autor:
|
|
Rolf Drechsler |
| Workshop: |
|
15th IEEE International Workshop on Rapid System Prototyping |
Referenz:
|
| Invited Talk, pp. 2-5, Geneva, 2004
| PDF:
|
| [hier ansehen]
|
» Visualization of Diagnosis Results for Design Debugging
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
13th International Workshop on Post-Binary ULSI Systems |
Referenz:
|
| pp. 1-2, Toronto, 2004
| PS:
|
| [hier ansehen]
|
» Disjoint Sum of Product Minimization by Evolutionary Algorithms
|
|
|
|
Autor:
|
|
Nicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
1st European Workshop on Hardware Optimisation Techniques (EvoHOT) |
Referenz:
|
| Applications of Evolutionary Computing: EvoWorkshops 2004, LNCS 3005, p. 198-207, Coimbra, 2004
| PDF:
|
| [hier ansehen]
|
» Efficient (Non-)Reachability Analysis of Counterexamples
|
|
|
|
Autor:
|
|
Rolf Drechsler, Wolfgang Günther, Burkhard Stubert |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Referenz:
|
| pp. 250-259, Kaiserslautern, 2004
| PDF:
|
| [hier ansehen]
|
» Using Synthesis Techniques in SAT Solvers
|
|
|
|
Autor:
|
|
Rolf Drechsler |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Referenz:
|
| pp. 165-173, Kaiserslautern, 2004
| PDF:
|
| [hier ansehen]
|
» A Tight Lower Bound for Dynamic BDD Minimization
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Rolf Drechsler |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Referenz:
|
| pp. 233-242, Kaiserslautern, 2004
| PS:
|
| [hier ansehen]
|
» An Approach to Formal Verification of Reconfigurable Systems
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler, Muazzam Ali |
| Workshop: |
|
1st IFIP WG 10.5 Workshop on "Frontiers in Automotive Electronics"
|
Referenz:
|
| Darmstadt, 2003
| PS:
|
| [hier ansehen]
|
» BDD-Based Verification of Scalable Designs
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Workshop: |
|
IEEE International High Level Design Validation and Test Workshop (HLDVT'2003) |
Referenz:
|
| pp. 123-128, San Francisco, 2003
| PDF:
|
| [hier ansehen]
|
» Random Pattern Testability of Circuits Derived from BDDs
|
|
|
|
Autor:
|
|
Junhao Shi, Göschwin Fey and Rolf Drechsler |
| Workshop: |
|
4th Workshop on RTL and High Level Testing(WRTLT'03) |
Referenz:
|
| p.70-78,
Xi'an, 2003
| PDF:
|
| [hier ansehen]
|
» Synthesizing Checkers for On-line Verification of System-on-Chip Designs
|
|
|
|
Autor:
|
|
Rolf Drechsler |
| Workshop: |
|
GI/GMM/ITG Fachtagung Entwurf Integrierter Schaltungen (11. E.I.S.-Workshop) |
Referenz:
|
| Erlangen, 2003, page 69
|
» BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
|
|
|
|
Autor:
|
|
Junhao Shi, Görschwin Fey and Rolf Drechsler |
| Workshop: |
|
IEEE European Test Workshop (ETW'03) |
Referenz:
|
| pp. 109-110, Maastricht, 2003
| PDF:
|
| [hier ansehen]
|
» MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits
|
|
|
|
Autor:
|
|
Rolf Drechsler |
| Workshop: |
|
15th ITG/GMM/GI Workshop Test methods and Reliability of Circuits and Systems |
Referenz:
|
| Timmendorfer Strand, 2003
| PS:
|
| [hier ansehen]
|
» BDD Circuit Optimization for Path Delay Fault-Testability
|
|
|
|
Autor:
|
|
Görschwin Fey, Junhao Shi, Rolf Drechsler |
| Workshop: |
|
15th ITG/GMM/GI Workshop Test methods and Reliability of Circuits and Systems |
Referenz:
|
| Timmendorfer Strand, 2003
| PS:
|
| [hier ansehen]
|
» A Hybrid Approach Combining Symbolic and Structural Techniques for Disjoint SOP Minimization
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler |
| Workshop: |
|
11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2003) |
Referenz:
|
| pp. 54-60, Hiroshima, 2003
| PS:
|
| [hier ansehen]
|
» GAME-HDL: Implementation of Evolutionary Algorithms using Hardware Description Languages
|
|
|
|
Autor:
|
|
Rolf Drechsler, Nicole Drechsler |
| Workshop: |
|
5th European Workshop on Evolutionary Computation in Image Analysis and Signal Processing (EvoIASP2003) |
Referenz:
|
| LNCS 2611, pp. 378-387, Colchester, 2003
| PDF:
|
| [hier ansehen]
|
» Formale Verifikation von LTL-Formeln für SystemC-Beschreibungen
|
|
|
|
Autor:
|
|
Daniel Große, Rolf Drechsler |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Referenz:
|
| pp. 229-238, Bremen, 2003
| PDF:
|
| [hier ansehen]
|
» Complete BDDs for Fast and Efficient Equivalence Checking, In Workshop on Computational Intelligence and Information Technologies
|
|
|
|
Autor:
|
|
Rolf Drechsler |
| Workshop: |
|
XXXVII International Scientific Conference on Information Communication and Energy Systems and Technologies (ICEST 2002) |
Referenz:
|
| Nis, 2002, pages 741-744
|
» Gatecomp: Equivalence Checking of Digital Circuits in an Industrial Environment
|
|
|
|
Autor:
|
|
Rolf Drechsler, Stefan Höreth |
| Workshop: |
|
International Workshop on Boolean Problems |
Referenz:
|
| Freiberg, 2002, pages 195-200
| PDF:
|
| [hier ansehen]
|
» Low Power Optimization Technique for BDD Mapped Finite State Machines
|
|
|
|
Autor:
|
|
M. Kerttu, P. Lindgren, Rolf Drechsler, M. Thornton |
| Workshop: |
|
International Workshop on Logic Synthesis (IWLS'2002) |
Referenz:
|
| New Orleans, 2002
|
» Low Power Optimization Techniques for BDD Mapped Circuits Using Temporal Correlation
|
|
|
|
Autor:
|
|
Rolf Drechsler, M. Kerttu, P. Lindgren, M. Thornton |
| Workshop: |
|
International Workshop on System-on-Chip for Real-Time Applications 2002 |
Referenz:
|
| Banff, 2002
|
» Symbolic Simulation of Algorithms Specified in HDL
|
|
|
|
Autor:
|
|
Klaus-Jürgen Englert, Bernd Becker, Rolf Drechsler |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Referenz:
|
| Tübingen, 2002, pages 113 - 122
| PDF:
|
| [hier ansehen]
| PS:
|
| [hier ansehen]
|
» Implementation and Visualization of a BDD Package in JAVA
|
|
|
|
Autor:
|
|
Rolf Drechsler, Jochen Römmler |
| Workshop: |
|
GI/ITG/GMM-Workshop 2002, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Referenz:
|
| Tübingen, 2002, pages 219 - 228
| PDF:
|
| [hier ansehen]
| PS:
|
| [hier ansehen]
|
|
|
|
