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Home « Team « Publikationen
» Publikationen von
Rolf Drechsler
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BÜCHER |
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» Advanced Logic Synthesis
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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André Inácio Reis, Rolf Drechsler |
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eBook |
Erscheinungsjahr:
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2017
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» Formal System Verification
State-of the-Art and Future Trends
[Lesen Sie hier mehr!]
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Verlag: |
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Springer Verlag |
Autor:
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Rolf Drechsler |
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Hardcover, eBook |
Erscheinungsjahr:
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2017
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» Computer: Wie funktionieren Smartphone, Tablet & Co.?
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Rolf Drechsler, Andrea Fink, Jannis Stoppe |
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Taschenbuch |
Erscheinungsjahr:
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2017
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» Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
[Lesen Sie hier mehr!]
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Verlag: |
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Shaker Verlag |
Autor:
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Daniel Große, Rolf Drechsler |
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Gebunden |
Erscheinungsjahr:
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2017
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» Automatic Methods for the Refinement of System Models
[Lesen Sie hier mehr!]
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Verlag: |
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Springer International Publishing |
Autor:
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Julia Seiter, Robert Wille, Rolf Drechsler |
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Taschenbuch |
Erscheinungsjahr:
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2016
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» Reversible and Quantum Circuits
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Nabila Abdessaied, Rolf Drechsler |
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eBook, Hardcover |
Erscheinungsjahr:
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2016
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» Languages, Design Methods, and Tools for Electronic System Design
[Lesen Sie hier mehr!]
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Verlag: |
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Springer International Publishing (Verlag) |
Autor:
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Rolf Drechsler, Robert Wille (Hrsg.) |
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Buch | Hardcover |
Erscheinungsjahr:
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2016
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» Synthese- und Optimierungsverfahren für zukünftige Computerparadigmen
[Lesen Sie hier mehr!]
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Verlag: |
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Shaker Verlag |
Autor:
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Robert Wille,
Oliver Keszöcze,
Rolf Drechsler (Hrsg.) |
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gebunden |
Erscheinungsjahr:
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2015
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» Formal Modeling and Verification of Cyber-Physical Systems
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Rolf Drechsler, Ulrich Kühne (Hrsg.) |
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eBook, Softcover |
Erscheinungsjahr:
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2015
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» Formal Specification Level
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Mathias Soeken, Rolf Drechsler |
| Format: |
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eBook, Hardcover |
Erscheinungsjahr:
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2014
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» Aspekte der Technischen Informatik
[Lesen Sie hier mehr!]
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Verlag: |
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MV-Wissenschaft |
Autor:
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Rolf Drechsler (Hrsg.) |
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Softcover |
Erscheinungsjahr:
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2014
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» Auf dem Weg zum Quantencomputer - Entwurf reversibler Logik
[Lesen Sie hier mehr!]
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Verlag: |
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Shaker Verlag |
Autor:
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Rolf Drechsler, Mathias Soeken, Robert Wille (Hrsg.) |
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gebunden |
Erscheinungsjahr:
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2012
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» High Quality Test Pattern Generation and Boolean Satisfiability
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Stephan Eggersglüß, Rolf Drechsler |
| Format: |
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Hardcover |
Erscheinungsjahr:
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2012
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» Applications of Evolutionary Computation
Applications of Evolutionary Computation
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Cecilia Di Chio, Anthony Brabazon, Gianni A. Di Caro, Rolf Drechsler, Muddassar Farooq, Jörn Grahl, Gary Greenfield, Christian Prins, Juan Romero und Giovanni Squillero, et al. |
| Format: |
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Gebunden |
Erscheinungsjahr:
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2011
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» Towards a Design Flow for Reversible Logic
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Robert Wille, Rolf Drechsler |
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Gebunden |
Erscheinungsjahr:
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2010
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» Debugging at the Electronic System Level
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Frank Rogin, Rolf Drechsler |
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Gebunden |
Erscheinungsjahr:
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2010
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» Quality-Driven SystemC Design
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Daniel Große, Rolf Drechsler |
| Format: |
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Hardcover |
Erscheinungsjahr:
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2010
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» Test Pattern Generation using Boolean Proof Engines
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille |
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Hardcover |
Erscheinungsjahr:
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2009
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» Robustness and Usability in Modern Design Flows
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Görschwin Fey, Rolf Drechsler |
| Format: |
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Hardcover |
Erscheinungsjahr:
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2008
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» Applications of Evolutionary Computing
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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M. Giacobini, A. Brabazon, S. Cagnoni, G. A. DiCaro, Rolf Drechsler, A. Ekart, A. I. Esparcia-Alcazar, M. Farooq, A. Fink, J. McCormack, M. O'Neill, J. Romero, F. Rothlauf, G. Squillero, S. Uyar, S. Yang
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| Format: |
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Gebunden |
Erscheinungsjahr:
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2008
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» Applications of Evolutionary Computing
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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M. Giacobini, A. Brabazon, S. Cagoni, G.A. Di Caro, Rolf Drechsler, M. Farooq, A. Fink, E. Lutton, P. Machado, S. Minner, M. O'Neill, J. Romero, F. Rothlauf, G. Squillero, H. Takagi, A.S. Uyar, S. Yang |
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Gebunden |
Erscheinungsjahr:
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2007
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» SATRIX - Algorithmen für Boolesche Erfüllbarkeit
[Lesen Sie hier mehr!]
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Verlag: |
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Shaker Verlag |
Autor:
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Daniel Große, Görschwin Fey, Rolf Drechsler (Hrsg.) |
| Format: |
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Gebunden |
Erscheinungsjahr:
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2007
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» Applications of Evolutionary Computing
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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F. Rothlauf, J. Branke, S. Cagnoni, E. Costa, C. Cotta, Rolf Drechsler, E. Lutton, P. Machado, J.H. Moore, J. Romero, G.D. Smith, G. Squillero, H. Takagi (Eds.) |
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Gebunden |
Erscheinungsjahr:
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2006
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» Advanced BDD Optimization
[Lesen Sie hier mehr!]
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Verlag: |
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Springer Verlag |
Autor:
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Rüdiger Ebendt, Görschwin Fey, Rolf Drechsler |
| Format: |
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Hardcover |
Erscheinungsjahr:
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2005
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» Technische Informatik - Eine Einführung
[Lesen Sie hier mehr!]
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Verlag: |
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Pearson Studium |
Autor:
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Bernd Becker, Rolf Drechsler, Paul Molitor |
| Format: |
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Gebunden |
Erscheinungsjahr:
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2005
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» Applications of Evolutionary Computing
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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Franz Rothlauf, Jürgen Branke, Stefano Cagnoni, David W. Corne, Rolf Drechsler, Yaochu Jin, Penousal Machado, Elena Marchiori, Juan Romero, George D. Smith, Giovanni Squillero |
| Format: |
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Gebunden |
Erscheinungsjahr:
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2005
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» FunTaskIC - Eine integrierte Entwurfsumgebung für SystemC
[Lesen Sie hier mehr!]
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Verlag: |
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Shaker Verlag |
Autor:
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Görschwin Fey, Rolf Drechsler (Hrsg.) |
| Format: |
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Gebunden |
Erscheinungsjahr:
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2005
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» Applications of Evolutionary Computing
[Lesen Sie hier mehr!]
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Verlag: |
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Springer |
Autor:
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G.R. Raidl, S. Cagnoni, J. Branke, D.W. Corne, Rolf Drechsler, Y. Jin, C.G. Johnson, P. Machado, E. Marchiori,F. Rothlauf, G.D. Smith, G. Squillero
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| Format: |
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Gebunden |
Erscheinungsjahr:
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2004
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» Advanced Formal Verification
[Lesen Sie hier mehr!]
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Verlag: |
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Kluwer Academic Publishers |
Autor:
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Rolf Drechsler |
| Format: |
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Gebunden |
Erscheinungsjahr:
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2004
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» Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
[Lesen Sie hier mehr!]
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Verlag: |
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Shaker Verlag |
Autor:
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Rolf Drechsler |
| Format: |
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Gebunden |
Erscheinungsjahr:
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2003
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» Evolutionary Algorithms for Embedded System Design
[Lesen Sie hier mehr!]
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Verlag: |
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Kluwer Academic Publishers |
Autor:
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Rolf Drechsler, Nicole Drechsler |
| Format: |
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Gebunden |
Erscheinungsjahr:
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2002
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» Software-Engineering und Hardware-Design
[Lesen Sie hier mehr!]
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Verlag: |
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Carl Hanser Verlag |
Autor:
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Axel Sikora, Rolf Drechsler
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| Format: |
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Gebunden |
Erscheinungsjahr:
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2002
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» Towards One-Pass Synthesis
[Lesen Sie hier mehr!]
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Verlag: |
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Kluwer Academic Publishers |
Autor:
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Rolf Drechsler, Wolfgang Günther
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| Format: |
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Hardcover |
Erscheinungsjahr:
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2002
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» Spectral Techniques in VLSI CAD
[Lesen Sie hier mehr!]
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Verlag: |
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Kluwer Academic Publishers |
Autor:
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Mitchell A. Thornton, Rolf Drechsler, D. Michel Miller |
| Format: |
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Hardcover |
Erscheinungsjahr:
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2001
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» Formal Verification of Circuits
[Lesen Sie hier mehr!]
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Verlag: |
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Kluwer Academic Publishers |
Autor:
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Rolf Drechsler |
| Format: |
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Hardcover |
Erscheinungsjahr:
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2000
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» Evolutionary Algorithms for VLSI CAD
[Lesen Sie hier mehr!]
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Verlag: |
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Kluwer Academic Publishers |
Autor:
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Rolf Drechsler |
| Format: |
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Hardcover |
Erscheinungsjahr:
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1998
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» Binary Decision Diagrams: Theory and Implementations
[Lesen Sie hier mehr!]
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Verlag: |
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Kluwer Academic Publisher |
Autor:
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Rolf Drechsler, Bernd Becker |
| Format: |
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Hardcover |
Erscheinungsjahr:
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1998
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» Graphenbasierte Funktionsdarstellung
[Lesen Sie hier mehr!]
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Verlag: |
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B.G. Teubner |
Autor:
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Rolf Drechsler, Bernd Becker |
| Format: |
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Gebunden |
Erscheinungsjahr:
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1998
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» Functional Decision Diagrams und ihre Anwendung
[Lesen Sie hier mehr!]
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Verlag: |
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Modell Verlag |
Autor:
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Rolf Drechsler |
| Format: |
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Gebunden |
Erscheinungsjahr:
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1996
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BUCHBEITRÄGE |
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| » On the Computational Complexity of Error Metrics in Approximate Computing |
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Autor:
| Oliver Keszöcze, Mathias Soeken, Rolf Drechsler
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| Herausgeber: | Bernd Steinbach |
| Buchtitel: | Further Improvements in the Boolean Domain |
| Verlag: | Cambridge Scholars Publishing |
| Seiten: | |
| Erscheinungsjahr: | 2018 |
| Format: | Paperback |
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| » On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-Based Error Effect Simulation: A Case Study |
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Autor:
| Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
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| Herausgeber: | Franco Fummi, Robert Wille |
| Buchtitel: | Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2016 |
| Verlag: | Springer |
| Seiten: | 39-58 |
| Erscheinungsjahr: | 2018 |
| Format: | Hardcover |
|
| » Logic Synthesis for Majority based In-Memory Computing |
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Autor:
| Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler
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| Herausgeber: | Sundarapandian Vaidyanathan, Christos Volos |
| Buchtitel: | Advances in Memristors, Memristive Devices and Systems |
| Verlag: | Springer |
| Seiten: | 425 - 448 |
| Erscheinungsjahr: | 2017 |
| Format: | Hardcover |
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| » Formal Verification of SystemC-based Cyber Components |
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Autor:
| Daniel Große, Hoang M. Le, Rolf Drechsler
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| Herausgeber: | Sabina Jeschke, Christian Brecher, Houbing Song, Danda B. Rawat |
| Buchtitel: | Industrial Internet of Things: Cybermanufacturing Systems |
| Verlag: | Springer |
| Seiten: | 137-167 |
| Erscheinungsjahr: | 2016 |
| Format: | Hardcover |
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| » A framework for reversible circuit complexity |
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Autor:
| Mathias Soeken, Nabila Abdessaied, Rolf Drechsler
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| Herausgeber: | Bernd Steinbach |
| Buchtitel: | Problems and New Solutions in the Boolean Domain |
| Verlag: | Cambridge Scholars Publishing |
| Seiten: | 327 - 341 |
| Erscheinungsjahr: | 2016 |
| Format: | Paperback |
|
| » Formal Specification Level |
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Autor:
| Rolf Drechsler, Mathias Soeken, Robert Wille
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| Herausgeber: | Jan Haase |
| Buchtitel: | Models, Methods, and Tools for Complex Chip Design: Selected Contributions from FDL 2012 |
| Verlag: | Springer |
| Seiten: | 37-52 |
| Erscheinungsjahr: | 2014 |
| Format: | Hardcover |
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| » SyReC: A Programming Language for Synthesis of Reversible Circuits |
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Autor:
| Robert Wille, Sebastian Offermann, Rolf Drechsler
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| Herausgeber: | Tom J. Kazmierski, Adam Morawiec |
| Buchtitel: | System Specification and Design Languages: Selected Contributions from FDL 2010 |
| Verlag: | Springer |
| Seiten: | 207-222 |
| Erscheinungsjahr: | 2012 |
| Format: | Hardcover |
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| » Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis |
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Autor:
| Daniel Große, Görschwin Fey, Rolf Drechsler
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| Herausgeber: | Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus |
| Buchtitel: | Design and Test Technology for Dependable Systems-on-Chip |
| Verlag: | Information Science Reference |
| Seiten: | 119-129 |
| Erscheinungsjahr: | 2011 |
| Format: | Hardcover |
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| » SMT-based Stimuli Generation in the SystemC Verification Library |
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Autor:
| Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler
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| Herausgeber: | Dominique Borrione |
| Buchtitel: | Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s: Selected Contributions on Specification, Design, and Verification from FDL 2009 |
| Verlag: | Springer |
| Seiten: | 227-244 |
| Erscheinungsjahr: | 2010 |
| Format: | Hardcover |
|
| » Synthesis of Boolean Functions in Reversible Logic |
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Autor:
| Robert Wille, Rolf Drechsler
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| Herausgeber: | Tsutomu Sasao, Jon T. Butler, Mitchell Thornton |
| Buchtitel: | Progress in Applications of Boolean Functions (Synthesis Lectures on Digital Circuits and Systems) |
| Verlag: | Morgan and Claypool Publishers |
| Seiten: | 75-92 |
| Erscheinungsjahr: | 2010 |
| Format: | Paperback |
|
| » Non-Clausal SAT and ATPG |
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Autor:
| Rolf Drechsler, Tommi Junttila and Ilkka Niemelä
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| Herausgeber: | A. Biere, M. Heule, H. van Maaren, T. Walsh |
| Buchtitel: | Handbook of Satisfiability |
| Verlag: | IOS Press |
| Seiten: | 655-693 |
| Erscheinungsjahr: | 2009 |
| Format: | gebunden |
|
| » Debugging Contradictory Constraints in Constraint-based Random Simulation |
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Autor:
| Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
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| Herausgeber: | Martin Radetzki |
| Buchtitel: | Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL'08 |
| Verlag: | Springer |
| Seiten: | 273-290 |
| Erscheinungsjahr: | 2009 |
| Format: | gebunden |
|
| » SWORD: A SAT like Prover Using Word Level Information |
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Autor:
| Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
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| Herausgeber: | Ricardo Reis, Vincent Mooney, Paul Hasler |
| Buchtitel: | VLSI-SoC: Advanced Topics on Systems on a Chip:
A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip |
| Verlag: | Springer |
| Seiten: | 175-192 |
| Erscheinungsjahr: | 2009 |
| Format: | Hardcover |
|
| » An Integrated SystemC Debugging Environment |
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Autor:
| Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke
|
| Herausgeber: | Eugenio Villar |
| Buchtitel: | Embedded Systems Specification and Design Languages: Selected contributions from FDL'07 |
| Verlag: | Springer |
| Seiten: | 59-71 |
| Erscheinungsjahr: | 2008 |
| Format: | gebunden |
|
| » Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques |
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Autor:
| Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler
|
| Herausgeber: | Eugenio Villar |
| Buchtitel: | Embedded Systems Specification and Design Languages: Selected contributions from FDL'07 |
| Verlag: | Springer |
| Seiten: | 73-86 |
| Erscheinungsjahr: | 2008 |
| Format: | gebunden |
|
| » Exact BDD Minimization for Path-Related Objective Functions |
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Autor:
| Rüdiger Ebendt, Rolf Drechsler
|
| Herausgeber: | Ricardo Reis, Ada Osseiran, Hans-Jörg Pleiderer |
| Buchtitel: | VLSI-SoC: From Systems to Silicon |
| Verlag: | Springer |
| Seiten: | 299-315 |
| Erscheinungsjahr: | 2007 |
| Format: | gebunden |
|
| » Stuck-At-Fault Testability of SPP Three-Level Logic Forms |
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Autor:
| V. Ciriani, A. Bernasconi, Rolf Drechsler
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| Herausgeber: | M. Glesner, R. Reis, L. Indrusiak, V. Mooney, H. Eveking |
| Buchtitel: | VLSI-SOC: From Systems to Chips |
| Verlag: | Springer |
| Seiten: | 299-313 |
| Erscheinungsjahr: | 2006 |
| Format: | gebunden |
|
| » Exploration of Sequential Depth by Evolutionary Algorithms |
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Autor:
| Nicole Drechsler, Rolf Drechsler
|
| Herausgeber: | M. Glesner, R. Reis, L. Indrusiak, V. Mooney, H. Eveking |
| Buchtitel: | VLSI-SOC: From Systems to Chips |
| Verlag: | Springer Boston |
| Seiten: | 73-83 |
| Erscheinungsjahr: | 2006 |
| Format: | gebunden |
|
| » Processor Verification |
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Autor:
| Daniel Große, Robert Siegmund, Rolf Drechsler
|
| Herausgeber: | Paolo Ienne, Rainer Leupers |
| Buchtitel: | Customizable Embedded Processors |
| Verlag: | Elsevier |
| Seiten: | 281-302 |
| Erscheinungsjahr: | 2006 |
| Format: | gebunden |
|
| » Automatic Test Pattern Generation |
|
Autor:
| Rolf Drechsler, Görschwin Fey
|
| Herausgeber: | Marco Bernardo, Alessandro Cimatti |
| Buchtitel: | Formal Methods for Hardware Verification, LNCS 3965 |
| Verlag: | Springer |
| Seiten: | 30-55 |
| Erscheinungsjahr: | 2006 |
| Format: | gebunden |
|
| » System-level validation using formal techniques |
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Autor:
| Rolf Drechsler, Daniel Große
|
| Herausgeber: | Bashir M. Al-Hashimi |
| Buchtitel: | System-on-Chip: Next Generation Electronics |
| Verlag: | The IEE |
| Seiten: | 715-745 |
| Erscheinungsjahr: | 2006 |
| Format: | gebunden |
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ZEITSCHRIFTEN |
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» Arduinos in der Schule -
Lernen mit Mikrocontrollern
[Link zur Zeitschriften-Homepage]
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Autor:
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Cornelia Große, Claudia Sobich, Sebastian Huhn, Markus Leuschner, Rolf Drechsler, Lutz
Mädler |
| Zeitschrift: |
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Computer + Unterricht |
| Details: |
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Volume 110, May 2018, Pages 43-45 |
Jahr:
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2018
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» Verifying SystemC using Intermediate Verification Language and Stateful Symbolic Simulation
[Link zur Zeitschriften-Homepage]
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Autor:
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Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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accepted |
Jahr:
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2018
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» Behaviour Driven Development for Hardware Design
[Link zur Zeitschriften-Homepage]
|
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Autor:
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Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Große, Rolf Drechsler |
| Zeitschrift: |
|
IPSJ Transactions on System LSI Design Methodology |
| Details: |
|
accepted |
Jahr:
|
|
2018
|
|
» An Automated Approach for Generating and Checking Control Logic for Reversible Hardware Description Language-Based Designs
[Link zur Zeitschriften-Homepage]
|
 |
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Autor:
|
|
Robert Wille, Oliver Keszöcze, Larts Othmer, Michael Kirkedal Thomsen, Rolf Drechsler |
| Zeitschrift: |
|
Journal of Low Power Electronics |
| Details: |
|
Volume 13, Number 4, Pages 633-641 |
Jahr:
|
|
2017
|
|
» An Energy-aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata
[Link zur Zeitschriften-Homepage]
|
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|
Autor:
|
|
Frank Sill Torres, Robert Wille, Philipp Niemann, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
accepted |
Jahr:
|
|
2017
|
|
» Frame Conditions in the Automatic Validation and Verification of UML/OCL Models: A Symbolic Formulation of modifies only Statements
[Link zur Zeitschriften-Homepage]
|
 |
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Autor:
|
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Nils Przigoda, Philipp Niemann, Jonas Gomes Filho, Robert Wille, Rolf Drechsler |
| Zeitschrift: |
|
Computer Languages, Systems & Structures |
| Details: |
|
accepted |
Jahr:
|
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2017
|
|
» Logic synthesis for RRAM-based in-memory computing
[Link zur Zeitschriften-Homepage]
|
 |
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Autor:
|
|
Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| Details: |
|
vol. 37, no. 7, pp. 1422-1435, July 2018.
DOI: 10.1109/TCAD.2017.2750064 |
Jahr:
|
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2018
|
|
» Synthesis of optical circuits using binary decision diagrams
[Link zur Zeitschriften-Homepage]
|
 |
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|
Autor:
|
|
Arighna Deb, Robert Wille, Oliver Keszöcze, Saeideh Shirinzadeh, Rolf Drechsler |
| Zeitschrift: |
|
Integration, the VLSI Journal |
| Details: |
|
Volume 59, September 2017, Pages 42–51 |
Jahr:
|
|
2017
|
|
» A PLiM computer for the IoT
[Link zur Zeitschriften-Homepage]
|
 |
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Autor:
|
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Mathias Soeken, Pierre-Emmanuel Gaillardon, Saeideh Shirinzadeh, Rolf Drechsler, Giovanni De Micheli |
| Zeitschrift: |
|
Computer |
| Details: |
|
50(6):35-40, DOI: 10.1109/MC.2017.173 |
Jahr:
|
|
2017
|
|
» Towards a Verification Flow Across Abstraction Levels:
Verifying Implementations Against Their Formal Specification
[Link zur Zeitschriften-Homepage]
|
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|
|
Autor:
|
|
Pablo Gonzalez-de-Aledo, Nils Przigoda, Robert Wille, Rolf Drechsler, Pablo Sanchez |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
36(3):475-488, DOI: 10.1109/TCAD.2016.2611494
|
Jahr:
|
|
2017
|
|
» metaSMT: Focus On Your Application And Not On Solver Integration
[Link zur Zeitschriften-Homepage]
|
 |
|
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Autor:
|
|
Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler,
Görschwin Fey |
| Zeitschrift: |
|
International Journal of Software Tools for Technology Transfer |
| Details: |
|
19(5):605-621, DOI10.1007/s10009-016-0426-1 Link |
Jahr:
|
|
2017
|
|
» Verifying the Structure and Behavior in UML/OCL Models Using Satisfiability Solvers
[Link zur Zeitschriften-Homepage]
|
 |
|
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|
|
Autor:
|
|
Nils Przigoda, Mathias Soeken, Robert Wille, Rolf Drechsler |
| Zeitschrift: |
|
IET Cyber-Physical Systems: Theory & Applications |
| Details: |
|
Volume 1, Issue 1, December 2016, pp. 49-59
DOI: 10.1049/iet-cps.2016.0022
|
Jahr:
|
|
2016
|
|
» Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits
[Link zur Zeitschriften-Homepage]
|
 |
|
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|
Autor:
|
|
Arighna Deb, Robert Wille, Oliver Keszöcze, Stefan Hillmich, Rolf Drechsler |
| Zeitschrift: |
|
Journal on Emerging Technologies in Computing Systems (JETC) |
| Details: |
|
Volume 13, Issue 1 |
Jahr:
|
|
2016
|
|
» Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability
[Link zur Zeitschriften-Homepage]
|
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|
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|
Autor:
|
|
Arighna Deb, Debesh K. Das, Hafizur Rahaman, Robert Wille, Rolf Drechsler, Bhargab B. Bhattacharya |
| Zeitschrift: |
|
Journal on Emerging Technologies in Computing Systems (JETC) |
| Details: |
|
Volume 12 Issue 4, Article No. 34 |
Jahr:
|
|
2016
|
|
» On Optimization-based ATPG and its Application for Highly Compacted Test Sets
[Link zur Zeitschriften-Homepage]
|
|
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Vol. 35(12), pp. 2104-2117 |
Jahr:
|
|
2016
|
|
» Time-resolved detection of diffusion limited temperature gradients inside single isolated burning droplets using Rainbow Refractometry
[Link zur Zeitschriften-Homepage]
|
 |
|
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|
Autor:
|
|
Christopher Rosebrock, Saeideh Shirinzadeh, Mathias Soeken, Norbert Riefler, Thomas Wriedt, Rolf Drechsler, Lutz Mädler |
| Zeitschrift: |
|
Combustion and Flame |
| Details: |
|
Volume 168, June 2016, Pages 255–269 |
Jahr:
|
|
2016
|
|
» Complexity of Reversible Circuits and their Quantum Implementations
[Link zur Zeitschriften-Homepage]
|
 |
|
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|
Autor:
|
|
Nabila Abdessaied, Matthew Amy, Rolf Drechsler, Mathias Soeken |
| Zeitschrift: |
|
Theoretical Computer Science |
| Details: |
|
Volume 618, (March 2016), pp. 85–106.
DOI:10.1016/j.tcs.2016.01.011 |
Jahr:
|
|
2016
|
|
» Analyzing Inconsistencies in UML/OCL Models
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Nils Przigoda, Robert Wille, Rolf Drechsler |
| Zeitschrift: |
|
Journal of Circuits, Systems and Computers |
| Details: |
|
Volume 25, Issue 03, March 2016DOI: 10.1142/S0218126616400211 |
Jahr:
|
|
2016
|
|
» Atomic distributions in crystal structures solved by Boolean satisfiability techniques
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Mathias Soeken, Rolf Drechsler, Reinhard X. Fischer |
| Zeitschrift: |
|
Zeitschrift für Kristallographie - Crystalline Materials |
| Details: |
|
Z. Kristallogr. 2016; 231(2): 107–111 |
Jahr:
|
|
2015
|
|
» SyReC: A Hardware Description Language for the Specification and Synthesis of Reversible Circuits
[Link zur Zeitschriften-Homepage]
|
|
|
|
|
|
Autor:
|
|
Robert Wille, Eleonora Schonborn, Mathias Soeken, Rolf Drechsler |
| Zeitschrift: |
|
INTEGRATION, the VLSI Journal |
| Details: |
|
53(3):39-53 |
Jahr:
|
|
2016
|
|
» Analyzing SystemC Designs: SystemC Analysis Approaches for Varying Applications
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Jannis Stoppe, Rolf Drechsler |
| Zeitschrift: |
|
Sensors |
| Details: |
|
Volume (issue) 15(5), pages 10399-10421 |
Jahr:
|
|
2015
|
|
» Scalable One-Pass Synthesis for Digital Microfluidic Biochips
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Robert Wille, Oliver Keszöcze, Tobias Boehnisch, Alexander Kroker, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Design & Test of Computers |
| Details: |
|
Volume 32, Issue 66, Pages 41—50 |
Jahr:
|
|
2015
|
|
» QMDDs: Efficient Quantum Function Representation and Manipulation
[Link zur Zeitschriften-Homepage]
|
|
|
|
|
|
Autor:
|
|
Philipp Niemann, Robert Wille, D. Michael Miller, Mitchell A. Thornton, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 35, Number 1, pp. 86-99DOI: 10.1109/TCAD.2015.2459034
|
Jahr:
|
|
2016
|
|
» Embedding of Large Boolean Functions for Reversible Logic
[Link zur Zeitschriften-Homepage]
|
|
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler |
| Zeitschrift: |
|
Journal on Emerging Technologies in Computing Systems (JETC) |
| Details: |
|
Volume 12, Issue 4
Preprint available at arXiv 1408.3586 |
Jahr:
|
|
2015
|
|
» Ancilla-free synthesis of large reversible functions using binary decision diagrams
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler |
| Zeitschrift: |
|
Journal of Symbolic Computation |
| Details: |
|
accepted, preprint available at arXiv 1408.3955 |
Jahr:
|
|
2015
|
|
» Benefits of illustrations and videos for technical documentations
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Cornelia Große, Lisa Jungmann, Rolf Drechsler |
| Zeitschrift: |
|
Computers in Human Behavior |
| Details: |
|
Volume 45, April 2015, Pages 109–120
DOI: 10.1016/j.chb.2014.11.095 |
Jahr:
|
|
2015
|
|
» Incorporating User Preferences in Many-Objective Optimization using Relation epsilon-Preferred
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Nicole Drechsler, André Sülflow, Rolf Drechsler |
| Zeitschrift: |
|
Natural Computing |
| Details: |
|
Volume 14, Issue 3, pp 469-483 |
Jahr:
|
|
2015
|
|
» Exact Reordering of Circuit Lines for Nearest Neighbor Quantum Architectures
[Link zur Zeitschriften-Homepage]
|
|
|
|
|
|
Autor:
|
|
Robert Wille, Aaron Lye, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 33, Number 12, pp. 1818-1831DOI: 10.1109/TCAD.2014.2356463
|
Jahr:
|
|
2014
|
|
» Special Issue on Reversible Computation
[Link zur Zeitschriften-Homepage]
|
|
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler, Mehdi . B. Tahoori (editors)
|
| Zeitschrift: |
|
Journal on Emerging Technologies in Computing Systems (JETC) |
| Details: |
|
Volume 11, Number 2 |
Jahr:
|
|
2014
|
|
» An effective fault ordering heuristic for SAT-based dynamic test compaction techniques
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Zeitschrift: |
|
it-Information Technology |
| Details: |
|
Volume 56, Number 4, pp. 157-164
Special Issue |
Jahr:
|
|
2014
|
|
» Testing integrated circuits
[Link zur Zeitschriften-Homepage]
|
|
|
|
|
|
Autor:
|
|
Rolf Drechsler |
| Zeitschrift: |
|
it-Information Technology |
| Details: |
|
Volume 56, Number 4, pp. 148-149
Special Issue |
Jahr:
|
|
2014
|
|
» Upper bounds for reversible circuits based on Young subgroups
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Nabila Abdessaied, Mathias Soeken, Michael Kirkedal Thomsen, Rolf Drechsler |
| Zeitschrift: |
|
Information Processing Letters |
| Details: |
|
Volume 114, Number 06 (June 2014), pp. 282-286.
DOI: 10.1016/j.ipl.2014.01.003 |
Jahr:
|
|
2014
|
|
» Considering Nearest Neighbor Constraints of Quantum Circuits at the Reversible Circuit Level
|
 |
|
|
|
|
Autor:
|
|
Robert Wille, Aaron Lye, Rolf Drechsler |
| Zeitschrift: |
|
Quantum Information Processing |
| Details: |
|
DOI: http://dx.doi.org/10.1007/s11128-013-0642-5 |
Jahr:
|
|
2013
|
|
» Quantum circuits employing roots of the Pauli matrices
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Mathias Soeken, D. Michael Miller, Rolf Drechsler |
| Zeitschrift: |
|
Physical Review A |
| Details: |
|
Volume 88, 042322, 2013, DOI: 10.1103/PhysRevA.88.042322 |
Jahr:
|
|
2013
|
|
» Trading Off Circuit Lines and Gate Costs in the Synthesis of Reversible Logic
[Link zur Zeitschriften-Homepage]
|
|
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, D. Michael Miller, Rolf Drechsler |
| Zeitschrift: |
|
INTEGRATION, the VLSI Journal |
| Details: |
|
Volume 47, Number 2, pp. 284-294, DOI: 10.1016/j.vlsi.2013.08.002 |
Jahr:
|
|
2014
|
|
» A Formal Model for Embedded Brain Reading
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Elsa Andrea Kirchner, Rolf Drechsler |
| Zeitschrift: |
|
Industrial Robot: an International Journal |
| Details: |
|
Volume 40, Issue 6, pp. 530-540 |
Jahr:
|
|
2013
|
|
» Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler |
| Zeitschrift: |
|
Multiple-Valued Logic and Soft Computing |
| Details: |
|
Volume 21, Number 5-6, 2013, pp. 627-640 |
Jahr:
|
|
2013
|
|
» RevKit: An Open Source Toolkit for the Design of Reversible Circuits
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler |
| Zeitschrift: |
|
Reversible Computation 2011 (Series: Lecture Notes in Computer Science) |
| Details: |
|
Volume 7165, Third International Workshop, RC 2011, Revised Papers, pp. 64-76 |
Jahr:
|
|
2012
|
|
» Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis
|
 |
|
|
|
|
Autor:
|
|
Daniel Große, Görschwin Fey, Rolf Drechsler |
| Zeitschrift: |
|
Electronic Communications of the EASST |
| Details: |
|
Volume 62, 13 pages |
Jahr:
|
|
2013
|
|
» Automatic TLM Fault Localization for SystemC
[Link zur Zeitschriften-Homepage]
|
|
|
|
|
|
Autor:
|
|
Hoang M. Le, Daniel Große, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 31, Number 8, pp. 1249-1262,
DOI: 10.1109/TCAD.2012.2188800
|
Jahr:
|
|
2012
|
|
» Special Issue on Reversible Computation
[Link zur Zeitschriften-Homepage]
|
|
|
|
|
|
Autor:
|
|
Rolf Drechsler, Irek Ulidowski, Robert Wille (editors) |
| Zeitschrift: |
|
Multiple-Valued Logic and Soft Computing |
| Details: |
|
Volume 18, Number 1 |
Jahr:
|
|
2012
|
|
» RevKit: A Toolkit for Reversible Circuit Design
[Link zur Zeitschriften-Homepage]
|
|
|
|
|
|
Autor:
|
|
Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler |
| Zeitschrift: |
|
Multiple-Valued Logic and Soft Computing |
| Details: |
|
Volume 18, Number 1, pp. 55-65 |
Jahr:
|
|
2012
|
|
» A Highly Fault-Efficient SAT-Based ATPG Flow
[Link zur Zeitschriften-Homepage]
|
|
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Design & Test of Computers |
| Details: |
|
Volume 29, Issue 4 (July/August), pp. 63-70
|
Jahr:
|
|
2012
|
|
» Efficient Data Structures and Methodologies for SAT-based ATPG providing High Fault Coverage in Industrial Application
[Link zur Zeitschriften-Homepage]
|
|
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 30, Number 9, pp. 1411-1415,
DOI: 10.1109/TCAD.2011.2152450 |
Jahr:
|
|
2011
|
|
» Effective Robustness Analysis using Bounded Model Checking Techniques
[Link zur Zeitschriften-Homepage]
|
|
|
|
|
|
Autor:
|
|
Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 30, Number 8, pp. 1239-1252
DOI: 10.1109/TCAD.2011.2120950 |
Jahr:
|
|
2011
|
|
» Synthesis of Quantum Circuits for Linear Nearest Neighbor Architectures
[Link zur Zeitschriften-Homepage]
|
|
|
|
|
|
Autor:
|
|
Mehdi Saeedi, Robert Wille, Rolf Drechsler |
| Zeitschrift: |
|
Quantum Information Processing |
| Details: |
|
Volume 10, Number 3, pp. 355-377DOI: 10.1007/s11128-010-0201-2 |
Jahr:
|
|
2011
|
|
» Debugging Reversible Circuits
[Link zur Zeitschriften-Homepage]
|
|
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler |
| Zeitschrift: |
|
INTEGRATION, the VLSI Journal |
| Details: |
|
Volume 44, Number 1, pp. 51-61, JanuaryDOI: 10.1016/j.vlsi.2010.08.002 |
Jahr:
|
|
2011
|
|
» BDD-Based Synthesis of Reversible Logic
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler |
| Zeitschrift: |
|
International Journal of Applied Metaheuristic Computing (IJAMC) |
| Details: |
|
Volume 1, Number 4, pp. 25-41 |
Jahr:
|
|
2010
|
|
» Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Görschwin Fey, Andre Sülflow, Stefan Frehse, Rolf Drechsler |
| Zeitschrift: |
|
it-Information Technology |
| Details: |
|
Volume 52, Number 4, pp. 216-223
PDF Download |
Jahr:
|
|
2010
|
|
» Towards Fully Automatic Synthesis of Embedded Software
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Embedded Systems Letters |
| Details: |
|
Volume 2, Number 3, pp. 53-57, September |
Jahr:
|
|
2010
|
|
» Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler |
| Zeitschrift: |
|
Electronic Notes in Theoretical Computer Science |
| Details: |
|
Volume 253, Number 6, pp. 57-70DOI: 10.1016/j.entcs.2010.02.006 |
Jahr:
|
|
2010
|
|
» Incremental Solving Techniques for SAT-based ATPG
[Link zur Zeitschriften-Homepage]
|
|
|
|
|
|
Autor:
|
|
Daniel Tille, Stephan Eggersglüß, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 29, Number 7, pp. 1125-1130, July |
Jahr:
|
|
2010
|
|
» Synthese reversibler Logik
[Link zur Zeitschriften-Homepage]
|
|
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler |
| Zeitschrift: |
|
it-Information Technology |
| Details: |
|
Volume 52, Number 1, pp. 30-38
PDF Download |
Jahr:
|
|
2010
|
|
» MONSOON: SAT-based ATPG for Path Delay Faults Using Multiple-Valued Logics
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Rolf Drechsler |
| Zeitschrift: |
|
Journal of Electronic Testing: Theory and Applications |
| Details: |
|
Volume 26, Number 3 / June, pp. 307-322
Pdf download (Preliminary Version)
The final publication is available at www.springerlink.com |
Jahr:
|
|
2010
|
|
» Overcoming the limitations of data introspection for SystemC
[Link zur Zeitschriften-Homepage]
|
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Autor:
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Christian Genz, Rolf Drechsler |
| Zeitschrift: |
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EDA Tech Forum |
| Details: |
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Volume 6, Issue 5, Pages 30-34 (December 2009) |
Jahr:
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2009
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» Weighted A* search - unifying view and application
[Link zur Zeitschriften-Homepage]
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Autor:
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Rüdiger Ebendt, Rolf Drechsler |
| Zeitschrift: |
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Artificial Intelligence |
| Details: |
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Volume 173, Issue 15, Pages 1367-1456 (September 2009) |
Jahr:
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2009
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» Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille |
| Zeitschrift: |
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it - information technology |
| Details: |
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Volume 51, Number 2, pp. 102-111
Pdf download |
Jahr:
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2009
|
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» Exact Synthesis of Elementary Quantum Gate Circuits
[Link zur Zeitschriften-Homepage]
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Autor:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Zeitschrift: |
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Multiple-Valued Logic and Soft Computing |
| Details: |
|
Volume 15, Number 4, pp. 283-300 |
Jahr:
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2009
|
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» Advanced Verification by Automatic Property Generation
[Link zur Zeitschriften-Homepage]
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Autor:
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Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke |
| Zeitschrift: |
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IET Computers & Digital Techniques |
| Details: |
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Volume 3, Issue 4, pp. 338-353, July |
Jahr:
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2009
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» Exact Multiple Control Toffoli Network Synthesis with SAT Techniques
[Link zur Zeitschriften-Homepage]
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Autor:
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Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 28, Number 5, pp. 703-715, MayDOI: 10.1109/TCAD.2009.2017215 |
Jahr:
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2009
|
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» Modeling and Proving Completeness in Formal Verification of Counting Heads
[Link zur Zeitschriften-Homepage]
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Autor:
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Sebastian Kinder, Rolf Drechsler |
| Zeitschrift: |
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Software Tools for Technology Transfer (STTT)
|
| Details: |
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Springer, Volume 10, Number 6, pp. 521 - 534 |
Jahr:
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2008
|
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» On Acceleration of SAT-based ATPG for Industrial Designs
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Daniel Tille |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 27, Number 7, pp. 1329-1333, July |
Jahr:
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2008
|
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» Improved SAT-based Reachability Analysis with Observability Don’t Cares
[Link zur Zeitschriften-Homepage]
|
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Autor:
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Sean Safarpour, Andreas Veneris and Rolf Drechsler |
| Zeitschrift: |
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Journal on Satisfiability, Boolean Modeling and Computation (JSAT) |
| Details: |
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Volume 5, pp. 1-25, Special Volume on Application of Constraints to Formal Verification |
Jahr:
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2008
|
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» On the Construction of Small Fully Testable Circuits with Low Depth
[Link zur Zeitschriften-Homepage]
|
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Autor:
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Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler |
| Zeitschrift: |
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Embedded Hardware Design - Microprocessors and Microsystems (MICPRO) |
| Details: |
|
Special Issue, Volume 32, Issues 5-6, pp. 263-269 |
Jahr:
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2008
|
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» Logic Minimization and Testability of 2-SPP Networks
[Link zur Zeitschriften-Homepage]
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Autor:
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Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 27, Number 7, pp. 1190-1202, July |
Jahr:
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2008
|
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» Analyzing Functional Coverage in Bounded Model Checking
[Link zur Zeitschriften-Homepage]
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Autor:
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Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 27, Number 7, pp. 1305-1314, July |
Jahr:
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2008
|
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» Automatic Fault Localization for Property Checking
[Link zur Zeitschriften-Homepage]
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Autor:
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Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler |
| Zeitschrift: |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 27, Number 6, pp. 1138-1149, June |
Jahr:
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2008
|
|
» BDD-based Verification of Scalable Designs
[Link zur Zeitschriften-Homepage]
|
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Autor:
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Daniel Große, Rolf Drechsler |
| Zeitschrift: |
|
Facta Universitatis, Series: Electronics and Energetics |
| Details: |
|
Volume 20, Number 3, pp. 367-379 |
Jahr:
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2007
|
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» Building Free Binary Decision Diagrams Using SAT Solvers
[Link zur Zeitschriften-Homepage]
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Autor:
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Robert Wille, Görschwin Fey, Rolf Drechsler |
| Zeitschrift: |
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Facta Universitatis, Series: Electronics and Energetics |
| Details: |
|
Volume 20, Number 3, pp. 381-394, |
Jahr:
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2007
|
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» An Integrated Approach for Combining BDDs and SAT Provers
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler, Görschwin Fey, Sebastian Kinder |
| Zeitschrift: |
|
Facta Universitatis, Series: Electronics and Energetics
|
| Details: |
|
Volume 20, Number 3, pp. 415-436 |
Jahr:
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2007
|
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» Technische Dokumentation von Soft- und Hardware in
eingebetteten Systemen
[Link zur Zeitschriften-Homepage]
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Autor:
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Beate Muranko, Rolf Drechsler |
| Zeitschrift: |
|
it - information technology |
| Details: |
|
Number 2, pp. 110-117
Pdf download |
Jahr:
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2007
|
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» Exact minimisation of path-related objective functions for binary decision diagrams
[Link zur Zeitschriften-Homepage]
|
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Autor:
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Rüdiger Ebendt, Rolf Drechsler |
| Zeitschrift: |
|
IEE Proceedings Computer & Digital Techniques |
| Details: |
|
Volume 153, Number 4, pp. 231-242, July |
Jahr:
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2006
|
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» Testability of SPP Three-Level Logic Networks in Static Fault Models
[Link zur Zeitschriften-Homepage]
|
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Autor:
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Valentina Ciriani, Anna Bernasconi, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 25, Number 10, pp. 2241-2248, October |
Jahr:
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2006
|
|
» The Effect of Improved Lower Bounds in Dynamic BDD Reordering
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Rüdiger Ebendt, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 25, Number 5, pp. 902-909, May |
Jahr:
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2006
|
|
» Minimizing the Number of Paths in BDDs
- Theory and Algorithm
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Görschwin Fey, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 25, Number 1, pp. 4-11, January |
Jahr:
|
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2006
|
|
» Combining Ordered Best-First Search with Branch and Bound for Exact BDD Minimization
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 24, Number 10, pp. 1515-1529, October |
Jahr:
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2005
|
|
» System Level Validation Using Formal Techniques
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Rolf Drechsler, Daniel Große |
| Zeitschrift: |
|
IEE Proceedings Computer & Digital Techniques, Special Issue on Embedded Microelectronic Systems: Status and Trends |
| Details: |
|
Volume 152, Number 3, pp. 393-406, May |
Jahr:
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2005
|
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» Generic Implementation of Multi-Valued Decision Diagram Packages
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Autor:
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Rolf Drechsler, Dragan Jankovic, Radomir Stankovic |
| Zeitschrift: |
|
Multiple-Valued Logic and Soft Computing |
| Details: |
|
Volume 11, Numbers 1-2, pp. 1-18 |
Jahr:
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2005
|
|
» Project-Based Learning in Student Teams in Computer Science Education
[Link zur Zeitschriften-Homepage]
|
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Autor:
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Andreas Breiter, Görschwin Fey, Rolf Drechsler |
| Zeitschrift: |
|
Facta Universitatis, Series: Electronics and Energetics
|
| Details: |
|
Volume 18, Number 2, August, pp. 165-180. |
Jahr:
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2005
|
|
» Synthesis of Fully Testable Circuits from BDDs
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Rolf Drechsler, Junhao Shi, Görschwin Fey |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 23, Number 3, March |
Jahr:
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2004
|
|
» Methods for Construction of Recursive Algorithms for Reed-Mulle-Fourier Polarity Matrices Calculation
|
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Autor:
|
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Dragan Jankovic, Rolf Drechsler |
| Zeitschrift: |
|
Multiple-Valued Logic and Soft Computing |
| Details: |
|
Volume 10, Numbers 1, pp. 29-50 |
Jahr:
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2004
|
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» Using Word-Level Information in Formal Hardware Verification
[Link zur Zeitschriften-Homepage]
|
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Autor:
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Rolf Drechsler |
| Zeitschrift: |
|
Automation and Remote Control |
| Details: |
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Jahr:
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Volume 65, Issue 6, pp. 963-977, June 2004
|
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» An Improved Branch and Bound Algorithm for Exact BDD Minimization
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 22, Number 12, pp. 1657-1663, December |
Jahr:
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2003
|
|
» Recursive Bi-Partitioning of Netlists for Large Number of Partitions
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
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Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst |
| Zeitschrift: |
|
Journal of Systems Architecture - the Euromicro Journal |
| Details: |
|
Volume 49, pp. 521-528 |
Jahr:
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2003
|
|
» Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Daniel Große, Rolf Drechsler |
| Zeitschrift: |
|
it - information technology |
| Details: |
|
Number 4, pp. 219-226, August |
Jahr:
|
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2003
|
|
» Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Wolfgang Günther, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computers |
| Details: |
|
Volume 52, Number 9, pp. 1196-1209, September |
Jahr:
|
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2003
|
|
» Exact Routing with Search Space Reduction
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Frank Schmiedle, Rolf Drechsler, Bernd Becker |
| Zeitschrift: |
|
IEEE Transactions on Computers |
| Details: |
|
Volume 52, Number 6, pp. 815-825, June |
Jahr:
|
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2003
|
|
» Computer Architecture Core of Knowledge for Computer Science Studies
|
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Autor:
|
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M. Stojcev, I. Milentijevic, D. Kehagias, Rolf Drechsler, M. Gusev |
| Zeitschrift: |
|
Cyprus Computer Society Journal |
| Details: |
|
Volume I, Edition 4, April |
Jahr:
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2003
|
|
» Polynomial Formal Verification of Multipliers
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
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Martin Keim, Rolf Drechsler, Bernd Becker, Michael Martin, Paul Molitor |
| Zeitschrift: |
|
Formal Methods in System Design: An International Journal |
| Details: |
|
Volume 22, Issue 1, pp. 39-58 |
Jahr:
|
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2003
|
|
» Low Power Optimization Techniques for BDD Mapped Circuits Using Temporal Correlation
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
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Rolf Drechsler, Mikael Kerttu, Per Lindgren, Mitch Thornton |
| Zeitschrift: |
|
Canadian Journal of Electrical and Computer Engineering |
| Details: |
|
Volume 27, Number 4, pp. 159-164, October |
Jahr:
|
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2002
|
|
» Minimization of Word-level Decision Diagrams
[Link zur Zeitschriften-Homepage]
|
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Autor:
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Rolf Drechsler, Wolfgang Günther, Stefan Höreth. |
| Zeitschrift: |
|
INTEGRATION, the VLSI Journal |
| Details: |
|
Volume 33, Issue 1-2, pp. 39-70 |
Jahr:
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2002
|
|
» Minimization of Free BDDs
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Wolfgang Günther, Rolf Drechsler |
| Zeitschrift: |
|
INTEGRATION, the VLSI Journal |
| Details: |
|
Volume 32, Issue 1-2, pp. 41-59 |
Jahr:
|
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2002
|
|
» Verifying Integrity of Decision Diagrams
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
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Rolf Drechsler |
| Zeitschrift: |
|
INTEGRATION, the VLSI Journal |
| Details: |
|
Volume 32, Issue 1-2, pp. 61-75 |
Jahr:
|
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2002
|
|
» Heuristic Learning based on Genetic Programming
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
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Frank Schmiedle, Nicole Drechsler, Daniel Große and Rolf Drechsler |
| Zeitschrift: |
|
Genetic Programming and Evolvable Machines |
| Details: |
|
Volume 3, pp. 363-388, December |
Jahr:
|
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2002
|
|
» Dynamic Re-Encoding During MDD Minimization
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Frank Schmiedle, Wolfgang Günther, Rolf Drechsler |
| Zeitschrift: |
|
Multiple-Valued Logic - An International Journal |
| Details: |
|
Volume 8, Numbers 5-6, pp. 625-643 |
Jahr:
|
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2002
|
|
» History-based Dynamic BDD Minimization
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Rolf Drechsler, Wolfgang Günther |
| Zeitschrift: |
|
INTEGRATION, the VLSI Journal |
| Details: |
|
Volume 31, Issue 1, pp. 51-63 |
Jahr:
|
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2001
|
|
» Äquivalenzvergleich digitaler Schaltungen im industriellen Umfeld
|
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Autor:
|
|
Rolf Drechsler |
| Zeitschrift: |
|
it+ti - Informationstechnik und Technische Informatik |
| Details: |
|
Oldenbourg Wissenschaftsverlag, Number 4, pp. 200-205 |
Jahr:
|
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2001
|
|
» Fault Simulation in Multi-Valued Logic Networks
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
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Rolf Drechsler, Martin Keim, Bernd Becker |
| Zeitschrift: |
|
Multiple-Valued Logic - An International Journal |
| Details: |
|
Volume 7, Numbers 1-2, pp. 25-47 |
Jahr:
|
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2001
|
|
» Binary Decision Diagrams in Theory and Practice
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Rolf Drechsler, Detlef Sieling |
| Zeitschrift: |
|
Software Tools for Technology Transfer (STTT) |
| Details: |
|
Springer, Number 3, pp. 112-136 |
Jahr:
|
|
2001
|
|
» Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker |
| Zeitschrift: |
|
Journal of Electronic Testing, Theory and Application (JETTA) |
| Details: |
|
No. 17, pp. 37-51, February |
Jahr:
|
|
2001
|
|
» Decision Diagram Method for Calculation of Pruned Walsh Transform
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Dragan Jankovic, Radomir Stankovic, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computers |
| Details: |
|
Volume 50, Number 2, pp. 147-157, February |
Jahr:
|
|
2001
|
|
» Using Lower Bounds during Dynamic BDD Minimization
[Link zur Zeitschriften-Homepage]
|
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|
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Autor:
|
|
Rolf Drechsler, Wolfgang Günther, Fabio Somenzi |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 20, Number 1, pp. 51-57, January |
Jahr:
|
|
2001
|
|
» ACTion: Combining Logic Synthesis and Technology Mapping for MUX based FPGAs
[Link zur Zeitschriften-Homepage]
|
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|
Autor:
|
|
Wolfgang Günther and Rolf Drechsler. |
| Zeitschrift: |
|
Journal of Systems Architecture - the Euromicro Journal |
| Details: |
|
Volume 46, Issue 14, pp. 1321-1334, December |
Jahr:
|
|
2000
|
|
» Boolean Function Representation and Spectral Characterization Using AND/OR Graphs
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Alenka Zuzek, Rolf Drechsler, Mitch Thornton |
| Zeitschrift: |
|
INTEGRATION, the VLSI Journal |
| Details: |
|
Volume 29, Issue 2, pp. 101-116, September |
Jahr:
|
|
2000
|
|
» Genetic Algorithm for Minimization of fixed polarity Reed-Muller expressions
|
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Autor:
|
|
Rolf Drechsler, Bernd Becker and Nicole Drechsler |
| Zeitschrift: |
|
IEE Proceedings Computers and Digital Techniques |
| Details: |
|
Volume 147, Number 5, September |
Jahr:
|
|
2000
|
|
» On the Computational Power of Linearly Transformed BDDs
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Wolfgang Günther, Rolf Drechsler |
| Zeitschrift: |
|
Information Processing Letters |
| Details: |
|
Volume 75, Nummer 3, pp. 119-125, August |
Jahr:
|
|
2000
|
|
» Fast Exact Minimization of BDDs
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Rolf Drechsler, Nicole Drechsler, Wolfgang Günther |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 19, Number 3, pp. 384-389, March |
Jahr:
|
|
2000
|
|
» Pseudo Kronecker Expressions for Symmetric Functions
[Link zur Zeitschriften-Homepage]
|
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|
|
Autor:
|
|
Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computers |
| Details: |
|
Volume 48, Number 9, pp. 987-990, September |
Jahr:
|
|
1999
|
|
» Testability of 2-Level AND/EXOR Circuits
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker |
| Zeitschrift: |
|
Journal of Electronic Testing, Theory and Application (JETTA) |
| Details: |
|
Volume 14, Number 3, pp. 173-192, June |
Jahr:
|
|
1999
|
|
» BDD Minimization Using Symmetries
[Link zur Zeitschriften-Homepage]
|
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Autor:
|
|
Christoph Scholl, Dirk Möller, Paul Molitor, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
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Volume 18, Number 2, pp. 81-100, February |
Jahr:
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1999
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» On Variable Ordering and Decomposition Type Choice in OKFDDs
[Link zur Zeitschriften-Homepage]
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Autor:
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Rolf Drechsler, Bernd Becker, Andrea Jahnke |
| Zeitschrift: |
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IEEE Transactions on Computers |
| Details: |
|
Volume 47, Number 12, December |
Jahr:
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1998
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KONFERENZEN |
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» Exploration of the Synchronization Constraint in Quantum-dot Cellular Automata
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Autor:
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Frank Sill Torres, Pedro A. Silva, Geraldo Fontes, José Augusto M. Nacif, Ricardo Santos Ferreira,
Omar Paranaiba Vilela Neto, Jeferson F. Chaves, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| Prague, Czech Republic, 2018
| Hyperlink:
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| [Link zur Konferenz]
|
» Multi-Objective Synthesis of Quantum Circuits Using Genetic Programming
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Autor:
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Moein Sarvaghad-Moghaddam, Philipp Niemann, Rolf Drechsler
|
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Leicester, UK, 2018
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Towards Reversed Approximate Hardware Design
|
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Autor:
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Saman Froehlich, Daniel Große, Rolf Drechsler |
| Konferenz: |
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Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| Prague, Czech Republic, 2018
| Hyperlink:
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| [Link zur Konferenz]
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» Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata
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Autor:
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Frank Sill Torres, Robert Wille, Marcel Walter, Philipp Niemann, Daniel Große, Rolf Drechsler |
| Konferenz: |
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Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| Prague, Czech Republic, 2018
| Hyperlink:
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| [Link zur Konferenz]
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» Synchronization of Clocked Field-Coupled Circuits
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Autor:
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Frank Sill Torres, Marcel Walter, Robert Wille, Daniel Große, Rolf Drechsler |
| Konferenz: |
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IEEE International Conference on Nanotechnology (Nano) |
Referenz:
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| Cork, Ireland, 2018
| Hyperlink:
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| [Link zur Konferenz]
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» Logic Synthesis for In-Memory Computing using Resistive Memories
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Autor:
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Saeideh Shirinzadeh, Rolf Drechsler |
| Konferenz: |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| Hong Kong SAR, China, 2018
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» A Novel Approach for Nearest Neighbor Realization of 2D Quantum Circuits
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Autor:
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Anirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| Hong Kong SAR, China, 2018
| Hyperlink:
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| [Link zur Konferenz]
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» Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers
|
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Autor:
|
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Alireza Mahzoon, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| Hong Kong SAR, China, 2018
| Hyperlink:
|
| [Link zur Konferenz]
|
» Towards Dynamic Execution Environment for System Security Protection against Hardware Flaws
|
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Autor:
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Kenneth Schmitz, Oliver Keszöcze, Jurij Schmidt, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| Hong Kong SAR, China, 2018
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reliability Improvements for Multiprocessor Systems by Health-Aware Task Scheduling
|
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Autor:
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Robert Schmidt, Rehab Massoud, Jaan Raik, Alberto Garcia-Ortiz, Rolf Drechsler |
| Konferenz: |
|
24th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) |
Referenz:
|
| Costa Brava, Spain, 2018
| Hyperlink:
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| [Link zur Konferenz]
|
» Natural Language based Power Domain Partitioning
|
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Autor:
|
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David Lemma, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| Budapest, Hungary, 2018
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Constraint-based Pattern Retargeting for Reducing Localized Power Activity during Testing
|
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Autor:
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Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen |
| Konferenz: |
|
21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| Budapest, Hungary, 2018
| Hyperlink:
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| [Link zur Konferenz]
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» SAT-Lancer: A Hardware SAT-Solver for Self-Verification
|
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Autor:
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Buse Ustaoglu, Sebastian Huhn, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
28th ACM Great Lakes Symposium on VLSI (GLVLSI) |
Referenz:
|
| Chicago, Illinois, USA, 2018
Received Best Poster Award
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Synthesis of Reversible Circuits Using Conventional Hardware Description Languages
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Autor:
|
|
Zaid Al-Wardi, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Linz, Austria, 2018
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Logic Design using Memristors: An Emerging Technology
|
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Autor:
|
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Saeideh Shirinzadeh, Kamalika Datta, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Linz, Austria, 2018
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Building Fast Multi-Agent Systems using Hardware Design Languages for High-Throughput Systems
|
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Autor:
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Jannis Stoppe, Christina Plump, Sebastian Huhn, Rolf Drechsler |
| Konferenz: |
|
6th International Conference on Dynamics in Logistics (LDIC) |
Referenz:
|
| Bremen, Germany, 2018
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Improved Synthesis of Clifford+T Quantum Functionality
|
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Autor:
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|
Philipp Niemann, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Dresden, Germany, 2018
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Resiliency Evaluation via Symbolic Fault Injection on Intermediate Code
|
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Autor:
|
|
Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Dresden, Germany, 2018
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Towards Fully Automated TLM-to-RTL Property Refinement
|
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Autor:
|
|
Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Dresden, Germany, 2018
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Testbench Qualification for SystemC-AMS Timed
Data Flow Models
|
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Autor:
|
|
Muhammad Hassan, Daniel Große, Hoang M. Le, Thilo Vörtler, Karsten Einwich, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Dresden, Germany, 2018
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Approximate Hardware Generation using Symbolic Computer Algebra employing Gröbner Basis
|
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Autor:
|
|
Saman Fröhlich, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Dresden, Germany, 2018
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» An Exact Method for Design Exploration of Quantum-dot Cellular Automata
|
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Autor:
|
|
Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Dresden, Germany, 2018
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Analyzing Frame Conditions in UML/OCL Models:
Consistency, Equivalence, and Independence
|
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Autor:
|
|
Philipp Niemann, Nils Przigoda, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
6th International Conference on Model-Driven Engineering and Software Development (MODELSWARD) |
Referenz:
|
| Funchal, Portugal, 2018
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Approximation-aware Testing for Approximate Circuits
|
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Autor:
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|
Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
23rd Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| pp. 239 - 244, Jeju, Korea, 2018
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips
|
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Autor:
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Oliver Keszöcze, Mohamed Ibrahim, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler |
| Konferenz: |
|
International Conference on VLSI Design (VLSID) |
Referenz:
|
| Pune, Indien, 2018
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Revealing Properties of Structural Materials by Combining Regression-based Algorithms and Nano Indentation Measurements
|
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Autor:
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Sebastian Huhn, Heike Sonnenberg, Stephan Eggersglüß, Brigitte Clausen, Rolf Drechsler |
| Konferenz: |
|
10th IEEE Symposium Series on Computational Intelligence (SSCI) |
Referenz:
|
| Hawaii, USA, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Towards Lightweight Satisfiability Solvers for Self-Verification
|
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Autor:
|
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Fritjof Bornebusch, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
7th International Symposium on Embedded Computing and System Design (ISED) |
Referenz:
|
| Durgapur, Indien, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Verifying Next Generation Electronic Systems
|
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Autor:
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Rolf Drechsler, Daniel Große |
| Konferenz: |
|
International Conference on Infocom Technologies and Unmanned Systems (ICTUS) |
Referenz:
|
| pp. 6 - 10, Dubai, United Arab Emirates, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata
|
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Autor:
|
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Mehran Goli, Jannis Stoppe, Rolf Drechsler |
| Konferenz: |
|
35th IEEE International Conference on Computer Design (ICCD) |
Referenz:
|
| Boston Area, Massachusetts, USA, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Identification of Efficient Clustering Techniques for Test Power Activity on the Layout
|
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Autor:
|
|
Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
26th IEEE Asian Test Symposium (ATS) |
Referenz:
|
| Taipei, Taiwan, 2017
| Hyperlink:
|
| [Link zur Konferenz]
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» More than true or false: Native Support of Irregular Values in the Automatic Validation & Verification of UML/OCL Models
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Autor:
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Nils Przigoda, Philipp Niemann, Judith Peters, Frank Hilken, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) |
Referenz:
|
| pp. 77-86, Vienna, Austria, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Yise - A novel Framework for Boolean Networks using Y-Inverter Graphs
|
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Autor:
|
|
Arun Chandrasekharan, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) |
Referenz:
|
| pp. 114-117, Vienna, Austria, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reconfigurable TAP Controllers with Embedded Compression for Large Test Data Volume
|
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Autor:
|
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Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
30th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) |
Referenz:
|
| Cambridge, UK, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Machine Learning Based Test Pattern Analysis for
Localizing Critical Power Activity Areas
|
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|
|
Autor:
|
|
Harshad Dhotre, Stephan Eggersglüß, Mehdi Dehbashi, Ulrike Pfannkuchen, Rolf Drechsler |
| Konferenz: |
|
30th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) |
Referenz:
|
| Cambridge, UK, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Unintrusive Aging Analysis based on Offline Learning
|
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Autor:
|
|
Frank Sill Torres, Pedro F. R. Leite Junior and Rolf Drechsler |
| Konferenz: |
|
30th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) |
Referenz:
|
| Cambridge, UK, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Towards Early Validation of Firmware-Based Power
Management using Virtual Prototypes:
A Constrained Random Approach
|
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Autor:
|
|
Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Verona, Italy, 2017
Best Paper Candidate
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Semi-Formal Cycle-Accurate Temporal Execution Traces Reconstruction
|
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|
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Autor:
|
|
Rehab Massoud, Jannis Stoppe, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
15th International Conference on Formal Modelling and Analysis of Timed Systems (FORMATS) |
Referenz:
|
| pp. 335-351, Berlin, Germany, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Early SoC Security Validation by VP-based Static Information Flow Analysis
|
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Autor:
|
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Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
|
| Konferenz: |
|
International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| pp. 400-407, Irvine, USA, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Dedicated Synthesis for MZI-based Optical Circuits based on AND-Inverter Graphs
|
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Autor:
|
|
Arighna Deb, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| Irvine, USA, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Self-practicing of logic circuits through mobile devices: Lecturers' and students' perceptions
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Autor:
|
|
Mazyar Seraj, Cornelia Große, Rolf Drechsler |
| Konferenz: |
|
9th annual International Conference on Education and New Learning Technologies (EduLearn17) |
Referenz:
|
| Barcelona, Spain, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» BioViz: An Interactive Visualization Engine for Digital Microfluidic Biochips
|
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|
|
Autor:
|
|
Jannis Stoppe, Oliver Keszöcze, Maximilian Luenert, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| Bochum, Germany, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Towards VHDL-based Design of Reversible Circuits
|
|
|
|
Autor:
|
|
Zaid Al-Wardi, Robert Wille, Rolf Drechsler
|
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Kolkata, India, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Efficient Construction of QMDDs for Irreversible, Reversible and Quantum Functions
|
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|
|
Autor:
|
|
Philipp Niemann, Alwin Zulehner, Robert Wille, Rolf Drechsler
|
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| pp. 214-231, Kolkata, India, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» An Adaptive Prioritized ε-Preferred Evolutionary Algorithm for Approximate BDD Optimization
|
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|
|
Autor:
|
|
Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Genetic and Evolutionary Computation Conference (GECCO) |
Referenz:
|
| Berlin, Germany, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» ProACt: A Processor for High Performance On-demand Approximate Computing
|
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|
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Autor:
|
|
Arun Chandrasekharan, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
27th ACM Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 463-466, Banff, Alberta, Canada, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» OR-Inverter Graphs for the Synthesis of Optical Circuits
|
|
|
|
Autor:
|
|
Arighna Deb, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
47th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Novi Sad, Serbia, 2017
| Hyperlink:
|
| [Link zur Konferenz]
|
» Extensions to the Reversible Hardware Description Language SyReC
|
|
|
|
Autor:
|
|
Zaid Al-Wardi, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
47th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Novi Sad, Serbia, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Error Bounded Exact BDD Minimization in Approximate Computing
|
|
|
|
Autor:
|
|
Saman Froehlich, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
47th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 254-259, Novi Sad, Serbia, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Exact Synthesis of Ternary Reversible Functions using Ternary Toffoli Gates
|
|
|
|
Autor:
|
|
Abhoy Kole, P. Mercy Nesa Rani, Kamalika Datta, Indranil Sengupta, Rolf Drechsler |
| Konferenz: |
|
47th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Novi Sad, Serbia, 2017
| Hyperlink:
|
| [Link zur Konferenz]
|
» Effects of Cell Shapes on the Routability of Digital Microfluidic Biochips
|
|
|
|
Autor:
|
|
Kevin Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Lausanne, Switzerland, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Automatic Equivalence Checking for SystemC-TLM 2.0 Models
Against their Formal Specifications
|
|
|
|
Autor:
|
|
Mehran Goli, Jannis Stoppe, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Lausanne, Switzerland, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Data Flow Testing for Virtual Prototypes
|
|
|
|
Autor:
|
|
Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Lausanne, Switzerland, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Endurance Management for Resistive Logic-In-Memory Computing Architectures
|
|
|
|
Autor:
|
|
Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Lausanne, Switzerland, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Optimization of Retargeting for IEEE 1149.1 TAP Controllers with Embedded Compression
|
|
|
|
Autor:
|
|
Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Lausanne, Schweiz, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Trust is good, Control is better: Hardware-based Instruction-Replacement for Reliable Processor-IPs
|
|
|
|
Autor:
|
|
Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
22nd Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| Chiba/Tokyo, Japan, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Enhancing Robustness of Sequential Circuits Using
Application-specific Knowledge and Formal Methods
|
|
|
|
Autor:
|
|
Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
22nd Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| Chiba/Tokyo, Japan, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Exact Routing for Micro-Electrode-Dot-Array Digital Microfluidic Biochips
|
|
|
|
Autor:
|
|
Oliver Keszöcze, Zipeng Li, Andreas Grimmer, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler |
| Konferenz: |
|
22nd Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| Chiba/Tokyo, Japan, 2017
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Exploring Superior Structural Materials Using Multi-Objective Optimization and Formal Techniques
|
|
|
|
Autor:
|
|
Rolf Drechsler, Stephan Eggersglüß, Nils Ellendt, Sebastian Huhn, Lutz Mädler |
| Konferenz: |
|
6th IEEE International Symposium on Embedded Computing & System Design (ISED) |
Referenz:
|
| Indian Institute of Technology, Patna, India, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Clocks vs. Instants Relations: Verifying CCSL Time Constraints in UML/MARTE Models
|
|
|
|
Autor:
|
|
Judith Peters, Nils Przigoda, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) |
Referenz:
|
| Indian Institute of Technology, Kanpur, India, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Frame Conditions in Symbolic Representations of UML/OCL Models
|
|
|
|
Autor:
|
|
Nils Przigoda, Jonas Gomes Filho, Philipp Niemann, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) |
Referenz:
|
| pp. 65-70, Indian Institute of Technology, Kanpur, India, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Guided Lightweight Software Test Qualification for IP Integration using Virtual Prototypes
|
|
|
|
Autor:
|
|
Daniel Große, Hoang M. Le, Muhammad Hassan, Rolf Drechsler |
| Konferenz: |
|
IEEE International Conference on Computer Design (ICCD) |
Referenz:
|
| Phoenix, USA, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» AIBA: an Automated Intra-Cycle Behavioral Analysis
for SystemC-based Design Exploration
|
|
|
|
Autor:
|
|
Mehran Goli, Jannis Stoppe, Rolf Drechsler |
| Konferenz: |
|
IEEE International Conference on Computer Design (ICCD) |
Referenz:
|
| Phoenix, USA, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Generating and Checking Control Logic in the HDL-based Design of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler |
| Konferenz: |
|
International Symposium on Electronic System Design (ISED) |
Referenz:
|
| Patna, Indien, 2016
| Hyperlink:
|
| [Link zur Konferenz]
|
» An Improved Gate Library for Logic Synthesis of Optical Circuits
|
|
|
|
Autor:
|
|
Shuchisman Burman, Kamalika Datta, Robert Wille, Indranil Sengupta, Rolf Drechsler |
| Konferenz: |
|
International Symposium on Electronic System Design (ISED) |
Referenz:
|
| Patna, Indien, 2016
| Hyperlink:
|
| [Link zur Konferenz]
|
» Towards a Model-Based Verification Methodology
for Complex Swarm Systems
|
|
|
|
Autor:
|
|
Jonas Gomes Filho, Nils Przigoda, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
International Symposium on Electronic System Design (ISED) |
Referenz:
|
| Patna, Indien, 2016
| Hyperlink:
|
| [Link zur Konferenz]
|
» Ground Setting Properties for an Efficient Translation of OCL in SMT-based Model Finding
|
|
|
|
Autor:
|
|
Nils Przigoda, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
ACM/IEEE 19th International Conference on Model Driven Engineering Languages and Systems (MoDELS) |
Referenz:
|
| Saint Malo, Brittany, France, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Equivalence Checking Using Gröbner Bases
|
|
|
|
Autor:
|
|
Amr Sayed Ahmed, Daniel Große, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Formal Methods in Computer Aided Design (FMCAD) |
Referenz:
|
| Mountain View, USA, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-based Error Effect Simulation - A Case Study
|
|
|
|
Autor:
|
|
Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Bremen, Germany, 2016
Best Paper Candidate
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Approximation-aware Rewriting of AIGs for Error Tolerant Applications
|
|
|
|
Autor:
|
|
Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
|
| Konferenz: |
|
International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| Austin, USA, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Compiled Symbolic Simulation for SystemC
|
|
|
|
Autor:
|
|
Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
|
| Konferenz: |
|
International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| Austin, USA, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs
|
|
|
|
Autor:
|
|
Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Bologna, Italy, 2016
| Hyperlink:
|
| [Link zur Konferenz]
|
» ParCoSS: Efficient Parallelized Compiled Symbolic Simulation
|
|
|
|
Autor:
|
|
Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
International Conference on Computer Aided Verification (CAV) |
Referenz:
|
| Toronto, Canada, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm
|
|
|
|
Autor:
|
|
Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Genetic and Evolutionary Computation Conference (GECCO) |
Referenz:
|
| Denver, USA, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» An MIG-based Compiler for Programmable Logic-in-Memory Architectures
|
|
|
|
Autor:
|
|
Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli
|
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| Austin, USA, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Precise Error Determination of Approximated Components in Sequential Circuits with Model Checking
|
|
|
|
Autor:
|
|
Arun Chandrasekharan,
Mathias Soeken,
Daniel Große,
Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| Austin, USA, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Multi-Objective BDD Optimization for RRAM based Circuit Design
|
|
|
|
Autor:
|
|
Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'16) |
Referenz:
|
| Košice, Slovakia, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers
|
|
|
|
Autor:
|
|
Sebastian Huhn, Stephan Eggersglüß and Rolf Drechsler |
| Konferenz: |
|
IEEE European Test Symposium (ETS) |
Referenz:
|
| Amsterdam, Niederlande, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Fault Detection in Parity Preserving Reversible Circuits
|
|
|
|
Autor:
|
|
Nils Przigoda, Gerhard Dueck, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
46th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Sapporo, Japan, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Re-writing HDL Descriptions for Line-aware Synthesis of Reversible Circuits
|
|
|
|
Autor:
|
|
Zaid Al-Wardi, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
46th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Sapporo, Japan, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation
|
|
|
|
Autor:
|
|
Laxmidhar Biswal, Chandan Bandyopadhyay, Anupam Chattopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman |
| Konferenz: |
|
46th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Sapporo, Japan, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Technology mapping of reversible circuits to Clifford+T quantum circuits
|
|
|
|
Autor:
|
|
Nabila Abdessaied, Matthew Amy, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
46rd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Sapporo, Japan, 2016
| Hyperlink:
|
| [Link zur Konferenz]
|
» Quantitative Timing Analysis of UML Activity Diagrams Using Statistical Model Checking
|
|
|
|
Autor:
|
|
Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Große,
Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 780-785, Dresden, Germany, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Towards Formal Verification of Real-World SystemC TLM Peripheral Models - A Case Study
|
|
|
|
Autor:
|
|
Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1160-1163, Dresden, Germany, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Formal Verification of Integer Multipliers by Combining Gröbner Basis with Logic Reduction
|
|
|
|
Autor:
|
|
Amr Sayed Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1048-1053, Dresden, Germany, 2016
Best Paper Candidate
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Fast Logic Synthesis for RRAM-based In-Memory Computing using Majority-Inverter Graphs
|
|
|
|
Autor:
|
|
Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Dresden, Germany, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Look-ahead Schemes for Nearest Neighbor Optimization of 1D and 2D Quantum Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Oliver Keszöcze, Marcel Walter, Patrick Rohrs, Anupam Chattopadhyay, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| Macao, China, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» BDD Minimization for Approximate Computing
|
|
|
|
Autor:
|
|
Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| pp. 474-479, Macao, China, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library
|
|
|
|
Autor:
|
|
Laxmidhar Biswal, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman |
| Konferenz: |
|
International Conference on VLSI Design (VLSI Design) |
Referenz:
|
| Kolkata, India, 2016
| Hyperlink:
|
| [Link zur Konferenz]
|
» Hardware/Software Co-Visualization on the Electronic System Level using SystemC
|
|
|
|
Autor:
|
|
Rolf Drechsler, Jannis Stoppe |
| Konferenz: |
|
International Conference
on VLSI Design |
Referenz:
|
| Kolkata, India, 2016
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Ensuring Safety and Reliability of IP-based System
Design – A Container Approach
|
|
|
|
Autor:
|
|
Arun Chandrasekharan, Kenneth Schmitz, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Rapid System Protoyping (RSP), 2015 |
Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reversible Computation: An Alternative Computation Paradigm for Low Power Applications
|
|
|
|
Autor:
|
|
Rolf Drechsler, Robert Wille |
| Konferenz: |
|
International Green and Sustainable Computing Conference (IGSC) |
Referenz:
|
| Las Vegas, USA, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Checking Concurrent Behavior in UML/OCL Models
|
|
|
|
Autor:
|
|
Nils Przigoda, Christoph Hilken, Robert Wille, Jan Peleska, Rolf Drechsler |
| Konferenz: |
|
ACM/IEEE 18th International Conference on Model Driven Engineering Languages and Systems (MoDELS) |
Referenz:
|
| Ottawa, Kanada, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven Generation
|
|
|
|
Autor:
|
|
Hoang M. Le, Rolf Drechsler
|
| Konferenz: |
|
Design and Verification Conference and Exhibition Europe (DVCon Europe) |
Referenz:
|
| Munich, Germany, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reverse Engineering with Simulation Graphs
|
|
|
|
Autor:
|
|
Mathias Soeken, Baruch Sterin, Rolf Drechsler, Robert K. Brayton |
| Konferenz: |
|
Formal Methods in Computer Aided Design (FMCAD) |
Referenz:
|
| Austin, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reversible Circuit Rewriting with Simulated Annealing
|
|
|
|
Autor:
|
|
Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, and Rolf Drechsler |
| Konferenz: |
|
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) |
Referenz:
|
| Daejeon, Korea, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Lazy-CSeq-SP: Boosting Sequentialization-based Verification of Multi-Threaded C Programs via Symbolic Pruning of Redundant Schedules
|
|
|
|
Autor:
|
|
Vladimir Herdt, Hoang M. Le, Daniel Große and Rolf Drechsler |
| Konferenz: |
|
Automated Technology for Verification and Analysis (ATVA) |
Referenz:
|
| pp. 228-233, Shanghai, China, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» A General and Exact Routing Methodology for Digital Microfluidic
Biochips
|
|
|
|
Autor:
|
|
Oliver Keszöcze, Robert Wille, Krishnendu Chakrabarty Rolf Drechsler
|
| Konferenz: |
|
International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| Austin, USA, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Formal Methods for Emerging Technologies
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler
|
| Konferenz: |
|
International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| Austin, USA, 2015
| Hyperlink:
|
| [Link zur Konferenz]
|
» Leveraging the Analysis for Invariant Independence in Formal System Models
|
|
|
|
Autor:
|
|
Nils Przigoda, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| Funchal, Madeira, Portugal, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Verification-driven Design Across Abstraction Levels - A Case Study
|
|
|
|
Autor:
|
|
Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| Funchal, Madeira, Portugal, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Envisioning Self-Verification of Electronic Systems
|
|
|
|
Autor:
|
|
Rolf Drechsler, Martin Fränzle, Robert Wille |
| Konferenz: |
|
Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) |
Referenz:
|
| Bremen, Germany, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits
|
|
|
|
Autor:
|
|
Amr Sayed Ahmed, Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2015). |
Referenz:
|
| pp. 1-6, Montpellier, France, 2015.
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Coverage of OCL Operation Specifications and Invariants
|
|
|
|
Autor:
|
|
Mathias Soeken, Julia Seiter, Rolf Drechsler |
| Konferenz: |
|
9th International Conference on Tests & Proofs (TAP) |
Referenz:
|
| L’Aquila, Italy, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Towards Line-aware Realizations of Expressions for HDL-based Synthesis of Reversible Circuits
|
|
|
|
Autor:
|
|
Zaid Al-Wardi, Robert Wille, Rolf Drechsler
|
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Grenoble, France, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Technology mapping for quantum circuits using Boolean functional decomposition
|
|
|
|
Autor:
|
|
Nabila Abdessaied, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Grenoble, France, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Multi-Objective BDD Optimization with Evolutionary Algorithms
|
|
|
|
Autor:
|
|
Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Genetic and Evolutionary Computation Conference (GECCO) |
Referenz:
|
| Madrid, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Contradiction Analysis for Inconsistent Formal Models
|
|
|
|
Autor:
|
|
Nils Przigoda, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15) |
Referenz:
|
| Belgrade, Serbia, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Requirement Phrasing Assistance using Automatic Quality Assessment
|
|
|
|
Autor:
|
|
Arman Allahyari-Abhari, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15) |
Referenz:
|
| Belgrade, Serbia, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» A Generic Representation of CCSL Time Constraints for UML/MARTE Models
|
|
|
|
Autor:
|
|
Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| San Francisco, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Verifying SystemC using Stateful Symbolic Simulation
|
|
|
|
Autor:
|
|
Vladimir Herdt, Hoang M. Le, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| San Francisco, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization
|
|
|
|
Autor:
|
|
Arighna Deb, Robert Wille, Rolf Drechsler, Debesh Das |
| Konferenz: |
|
45th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Waterloo, Canada, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» An Examination of the NCV-v1 Quantum Library Based on Minimal Circuits
|
|
|
|
Autor:
|
|
Arman Allahyari-Abhari, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
45th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Waterloo, Canada, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Automated Feature Localization for Dynamically Generated SystemC Designs
|
|
|
|
Autor:
|
|
Jannis Stoppe, Robert Wille, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE'15) |
Referenz:
|
| Grenoble, France, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» BDD-based Synthesis for All-optical Mach-Zehnder Interferometer Circuits
|
|
|
|
Autor:
|
|
Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler |
| Konferenz: |
|
International Conference on VLSI Design (VLSI Design) |
Referenz:
|
| Bengaluru, India, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Determining the Minimal Number of SWAP Gates for Multi-dimensional Nearest Neighbor Quantum Circuits
|
|
|
|
Autor:
|
|
Aaron Lye, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| Chiba/Tokyo, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reverse BDD-based Synthesis for Splitter-free Optical Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Oliver Keszöcze, Clemens Hopfmuller, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| Chiba/Tokyo, 2015
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Safe IP Integration Using Container Modules
|
|
|
|
Autor:
|
|
Rolf Drechsler, Ulrich Kühne
|
| Konferenz: |
|
International Symposium on Electronic System Design (ISED) |
Referenz:
|
| Mangalore, India, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Exact Routing for Digital Microfluidic Biochips with Temporary Blockages
|
|
|
|
Autor:
|
|
Oliver Keszöcze, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| San Jose, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Automated and Quality-driven Requirements Engineering
|
|
|
|
Autor:
|
|
Rolf Drechsler, Mathias Soeken, Robert Wille, |
| Konferenz: |
|
International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| San Jose, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemC
|
|
|
|
Autor:
|
|
Hoang M. Le, Rolf Drechsler
|
| Konferenz: |
|
Design and Verification Conference and Exhibition Europe (DVCon Europe) |
Referenz:
|
| Munich, Germany, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» metaSMT: A Unified Interface to SMT-LIB2
|
|
|
|
Autor:
|
|
Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler
|
| Konferenz: |
|
Forum on specification & Design Languages (FDL'14) |
Referenz:
|
| pp. 1-6, Munich, Germany, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Automating the Translation of Assertions Using Natural Language Processing Techniques
|
|
|
|
Autor:
|
|
Mathias Soeken, Christopher B. Harris, Nabila Abdessaied, Ian G. Harris and Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Munich, Germany, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Automatic Refinement Checking for Formal System Models
|
|
|
|
Autor:
|
|
Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Munich, Germany, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Verifying Consistency between Activity Diagrams and Their Corresponding OCL Contracts
|
|
|
|
Autor:
|
|
Christoph Hilken, Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Munich, Germany, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Quality Assessment for Requirements based on Natural Language Processing
|
|
|
|
Autor:
|
|
Mathias Soeken, Nabila Abdessaied, Arman Allahyari-Abhari, Andi Buzo, Liana Musat, Georg Pelz, Rolf Drechsler |
| Konferenz: |
|
Special Session at the Forum on Specification & Design Languages (FDL'14) |
Referenz:
|
| Munich, Germany, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Improving Coverage of Simulation-based Verification by Dedicated Stimuli Generation
|
|
|
|
Autor:
|
|
Shuo Yang, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 599-606, Verona, Italy, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Determining Cases of Scenarios to Improve Coverage in Simulation-based Verication
|
|
|
|
Autor:
|
|
Shuo Yang, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Symposium on Integrated Circuits and System Design (SBCCI) |
Referenz:
|
| Aracaju, Brazil, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Validating SystemC Implementations Against Their Formal Specifications
|
|
|
|
Autor:
|
|
Jannis Stoppe, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Symposium on Integrated Circuits and System Design (SBCCI) |
Referenz:
|
| Aracaju, Brazil, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Self-Verification as the Key Technology for Next Generation Electronic Systems
|
|
|
|
Autor:
|
|
Rolf Drechsler, Hoang M. Le, Mathias Soeken |
| Konferenz: |
|
Symposium on Integrated Circuits and System Design (SBCCI) |
Referenz:
|
| Aracaju, Brazil, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Recent Advances in SAT-based ATPG: Non-Standard Fault Models, Multi Constraints and Optimization
|
|
|
|
Autor:
|
|
Bernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer |
| Konferenz: |
|
International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) |
Referenz:
|
| pp. 1-10, Santorini, Greece, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Behaviour Driven Development for Tests and Verification
|
|
|
|
Autor:
|
|
Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
8th International Conference on Tests & Proofs (TAP) |
Referenz:
|
| pp. 61-77, York, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Generating SystemC Implementations for Clock Constraints specified in UML/MARTE CCSL
|
|
|
|
Autor:
|
|
Judith Peters, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
International Conference on Engineering of Complex Computer Systems (ICECCS) |
Referenz:
|
| pp. 116-125, Tianjin, China, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Exact One-pass Synthesis of Digital Microfluidic Biochips
|
|
|
|
Autor:
|
|
Oliver Keszöcze, Robert Wille, Tsung-Yi Ho, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| San Francisco, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State-of-the-Art and Research Challenges
|
|
|
|
Autor:
|
|
Jan-Hendrik Oetjens,
Nico Bannow,
Markus Becker,
Oliver Bringmann,
Andreas Burger,
Moomen Chaari,
Samarjit Chakraborty,
Rolf Drechsler,
Wolfgang Ecker,
Kim Gruettner,
Thomas Kruse,
Christoph Kuznik,
Hoang M. Le,
Andreas Mauderer,
Wolfgang Mueller,
Daniel Mueller-Gritschneder,
Frank Poppen,
Hendrik Post,
Sebastian Reiter,
Wolfgang Rosenstiel,
Simon Roth,
Ulf Schlichtmann,
Andreas von Schwerin,
Bogdan-Andrei Tabacaru,
Alexander Viehl |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| pp. 113:1-6, San Francisco, 2014
| Hyperlink:
|
| [Link zur Konferenz]
|
» Mapping NCV Circuits to Optimized Clifford+T Circuits
|
|
|
|
Autor:
|
|
D. Michael Miller, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Kyoto, Japan, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Equivalence Checking in Multi-level Quantum Systems
|
|
|
|
Autor:
|
|
Philipp Niemann, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| pp. 201-215, Kyoto, Japan, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» RevVis: Visualization of Structures and Properties in Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Jannis Stoppe, Eleonora Schönborn, Kamalika Datta, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Kyoto, Japan, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Quantum Circuit Optimization by Hadamard Gate Reduction
|
|
|
|
Autor:
|
|
Nabila Abdessaied, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| Kyoto, Japan, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Optimizing DD-based Synthesis of Reversible Circuits using Negative Control Lines
|
|
|
|
Autor:
|
|
Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler |
| Konferenz: |
|
IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 129-134, Warschau, Polen, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Optimization-based Multiple Target Test Generation for Highly Compacted Test Sets
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler |
| Konferenz: |
|
19th IEEE European Test Symposium (ETS) |
Referenz:
|
| Paderborn, Germany, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» A Cube Pairing Approach for Synthesis of ESOP based Reversible Circuit
|
|
|
|
Autor:
|
|
Chandan Bandyopadhyay, Hafizur Rahaman, Rolf Drechsler |
| Konferenz: |
|
44rd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| Bremen, 2014
| Hyperlink:
|
| [Link zur Konferenz]
|
» Future SoC Verification Methodology: UVM
Evolution or Revolution?
|
|
|
|
Autor:
|
|
Rolf Drechsler, Christophe Chevallaz, Franco Fummi, Alan Hu, Ronny Morad, Frank Schirrmeister, Alex Goryachev |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE'14) |
Referenz:
|
| Dresden, Germany, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Towards Verifying Determinism of SystemC Designs
|
|
|
|
Autor:
|
|
Hoang M. Le, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE'14) |
Referenz:
|
| pp. 153:1-4, Dresden, Germany, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Grammar-based Program Generation Based on Model Finding
|
|
|
|
Autor:
|
|
Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
IEEE Design and Test Symposium 2013 (IDT) |
Referenz:
|
| Marrakesch, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Optimal SWAP Gate Insertion for Nearest Neighbor Quantum Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Aaron Lye, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| pp. 489-494, Singapore, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Efficient Synthesis of Quantum Circuits Implementing Clifford Group Operations
|
|
|
|
Autor:
|
|
Philipp Niemann, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| pp. 483-488, Singapore, 2014
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Improved SAT-based ATPG: More Constraints, Better Compaction
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
IEEE/ACM International Conference on Computer-Aided Design (ICCAD) |
Referenz:
|
| pp. 85-90, San Jose, USA, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» A Compact and Efficient SAT Encoding for Quantum Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Nils Przigoda, Rolf Drechsler |
| Konferenz: |
|
IEEE Africon |
Referenz:
|
| Mauritius, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Exploiting Reversibility in the Complete Simulation of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Simon Stelter, Rolf Drechsler |
| Konferenz: |
|
IEEE Africon |
Referenz:
|
| Mauritius, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Cone of Influence Analysis at the Electronic System Level Using Machine Learning
|
|
|
|
Autor:
|
|
Jannis Stoppe, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| Santander, Spain, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Minimal Stimuli Generation in Simulation-based Verification
|
|
|
|
Autor:
|
|
Shuo Yang, Robert Wille, Daniel Große and Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| Santander, Spain, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» The SyReC Hardware Description Language:
Enabling Scalable Synthesis of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler |
| Konferenz: |
|
International Midwest Symposium on Circuits and Systems (MWSCAS) |
Referenz:
|
| Columbus, USA, 2013
| Hyperlink:
|
| [Link zur Konferenz]
|
» Incorporating User Preferences in Many-Objective Optimization using Relation Epsilon-Preferred
|
|
|
|
Autor:
|
|
Nicole Drechsler, André Sülflow, Rolf Drechsler |
| Konferenz: |
|
International Conference on Evolutionary Computation Theory and Applications (ECTA) |
Referenz:
|
| Vilamoura, Portugal, 2013
| Hyperlink:
|
| [Link zur Konferenz]
|
» Data Extraction from SystemC Designs using Debug Symbols and the SystemC API
|
|
|
|
Autor:
|
|
Jannis Stoppe, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| Natal, Brazil, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» On the “Q” in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-structure
|
|
|
|
Autor:
|
|
Philipp Niemann, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| pp. 125-140, Victoria, Canada, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Exploiting Negative Control Lines in the Optimization of Reversible Circuits
|
|
|
|
Autor:
|
|
Kamalika Datta, Gaurav Rathi, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| pp. 209-220, Victoria, Canada, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure
|
|
|
|
Autor:
|
|
Arighna Deb, Debesh Kumar Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| pp. 182-195, Victoria, Canada, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reducing the Depth of Quantum Circuits Using Additional Lines
|
|
|
|
Autor:
|
|
Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Reversible Computation |
Referenz:
|
| pp. 221-233, Victoria, Canada, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Hardware-Software Co-Visualization: Developing Systems in the Holodeck
|
|
|
|
Autor:
|
|
Rolf Drechsler, Mathias Soeken |
| Konferenz: |
|
16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 1-4, Karlovy Vary, Czech Republic, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Verifying SystemC using an Intermediate Verification Language and Symbolic Simulation
|
|
|
|
Autor:
|
|
Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| pp. 116:1-6 Austin, Texas, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Hongyan Zhang, Rolf Drechsler |
| Konferenz: |
|
43rd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 29-34, Toyama, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Debugging of Reversible Circuits using πDDs
|
|
|
|
Autor:
|
|
Laura Tague, Mathias Soeken, Shin-ichi Minato, Rolf Drechsler |
| Konferenz: |
|
43rd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 316-321, Toyama, Japan, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Exact Template Matching Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
43rd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 328-333, Toyama, Japan, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Synchronized Debugging across Different Abstraction Levels in System Design
|
|
|
|
Autor:
|
|
Rolf Drechsler, Daniel Große, Hoang M. Le, André Sülflow |
| Konferenz: |
|
embedded world Conference 2013 |
Referenz:
|
| Nürnberg, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Scalable Fault Localization for SystemC TLM Designs
|
|
|
|
Autor:
|
|
Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE'13) |
Referenz:
|
| pp. 35-38, Grenoble, France, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Determining Relevant Model Elements for the Verification of UML/OCL Specifications
|
|
|
|
Autor:
|
|
Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1189-1192, Grenoble, France, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Towards a Generic Verification Methodology for System Models
|
|
|
|
Autor:
|
|
Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1193-1196, Grenoble, France, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Improving the Mapping of Reversible Circuits to Quantum Circuits Using Multiple Target Lines
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| pp. 145-150. Yokohama, Japan, 2013
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» An Evolutionary Approach to Reversible Logic Synthesis using Output Permutation
|
|
|
|
Autor:
|
|
Kamalika Datta, Indranil Sen Gupta, Hafizur Rahaman, Rolf Drechsler |
| Konferenz: |
|
IEEE Design and Test Symposium 2012 (IDT) |
Referenz:
|
| Doha, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Towards Dialog Systems for Assisted Natural Language Processing in the Design of Embedded Systems
|
|
|
|
Autor:
|
|
Rolf Drechsler, Mathias Soeken, Robert Wille |
| Konferenz: |
|
IEEE Design and Test Symposium 2012 (IDT) |
Referenz:
|
| Doha, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Synthesis of Reversible Circuits Using Decision Diagrams
|
|
|
|
Autor:
|
|
Rolf Drechsler, Robert Wille |
| Konferenz: |
|
International Symposium on Electronic System Design (ISED) |
Referenz:
|
| pp. 1-5, Kolkata, WB, India, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» SyDe - a New Graduate School for
System Design in an Excellent Setting
|
|
|
|
Autor:
|
|
Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Informatics Europe (ECSS) |
Referenz:
|
| Barcelona, 2012
| Hyperlink:
|
| [Link zur Konferenz]
|
» From Requirements and Scenarios to ESL Design in SystemC
|
|
|
|
Autor:
|
|
Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
International Symposium on Electronic System Design (ISED) |
Referenz:
|
| pp. 183-187, Kolkata, WB, India, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» FoREnSiC - An Automatic Debugging Environment for C Programs
|
|
|
|
Autor:
|
|
Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow
|
| Konferenz: |
|
Haifa Verification Conference (HVC) |
Referenz:
|
| Haifa, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» The System Verification Methodology for
Advanced TLM Verification
|
|
|
|
Autor:
|
|
Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler, Wolfgang Ecker, Volkan Esen |
| Konferenz: |
|
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) |
Referenz:
|
| pp. 313-322, Tampere, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Complete and Effective Robustness Checking by Means of Interpolation
|
|
|
|
Autor:
|
|
Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav and Rolf Drechsler |
| Konferenz: |
|
Formal Methods in Computer-Aided Design (FMCAD'12) |
Referenz:
|
| Cambridge, UK, 2012, page 82-90
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Completeness-Driven Development
|
|
|
|
Autor:
|
|
Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille |
| Konferenz: |
|
International Conference on Graph Transformation |
Referenz:
|
| pp. 38-50, Bremen, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC
|
|
|
|
Autor:
|
|
Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
International Symposium on System-on-Chip (SoC) |
Referenz:
|
| pp. 1-7, Tampere, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Localizing Features of ESL Models for Design Understanding
|
|
|
|
Autor:
|
|
Marc Michael, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Vienna, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Formal Specification Level: Towards Verification-driven Design Based on Natural Language Processing
|
|
|
|
Autor:
|
|
Rolf Drechsler, Mathias Soeken, Robert Wille |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 53-58, Vienna, Austria, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Circuit Line Minimization in the HDL-based Synthesis of Reversible Logic
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| pp. 213-218, Amherst, USA, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Coverage-driven Stimuli Generation
|
|
|
|
Autor:
|
|
Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
15th Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| Izmir, Turkey, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology
|
|
|
|
Autor:
|
|
Rolf Drechsler, Robert Wille |
| Konferenz: |
|
International Symposium on VLSI Design and Test (VDAT) |
Referenz:
|
| Shibpur, India, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Assisted Behavior Driven Development Using Natural Language Processing
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
50th International Conference on Objects, Models, Components, Patterns (TOOLS) |
Referenz:
|
| pp. 269-287, Prague, Czech Republic, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» A New SAT-based ATPG for Generating Highly Compacted Test Sets
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler |
| Konferenz: |
|
15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 230-235, Tallinn, Estonia, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits
|
|
|
|
Autor:
|
|
Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler |
| Konferenz: |
|
42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 173-178, Victoria, Canada, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» A Synthesis Flow for Sequential Reversible Circuits
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler |
| Konferenz: |
|
42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 299-304, Victoria, Canada, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler |
| Konferenz: |
|
42nd International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 69-74, Victoria, Canada, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler, Christof Oswald, Alberto Garcia-Ortiz |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Dresden, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» A Guiding Coverage Metric for Formal Verification
|
|
|
|
Autor:
|
|
Finn Haedicke, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| Dresden, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Eliminating Invariants in UML/OCL Models
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1142-1145, Dresden, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Debugging of Inconsistent UML/OCL Models
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1078-1083, Dresden, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Synthesis of Reversible Circuits with Minimal Lines for Large Functions
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler |
| Konferenz: |
|
Asia and South Pacific Design Automation Conference (ASP-DAC) |
Referenz:
|
| pp. 85-92, Sydney, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Improved Fault Diagnosis for Reversible Circuits
|
|
|
|
Autor:
|
|
Hongyan Zhang, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Asian Test Symposium (ATS) |
Referenz:
|
| New Delhi, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Hochoptimierter Ablauf zur Robustheitsprüfung
|
|
|
|
Autor:
|
|
Stefan Frehse, Finn Haedicke, Melanie Diepenbeck, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) |
Referenz:
|
| Hamburg-Harburg, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Analyzing Dependability Measures at the Electronic System Level
|
|
|
|
Autor:
|
|
Marc Michael, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 1-8, Oldenburg, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Efficient Realization of Control Logic in Reversible Circuits
|
|
|
|
Autor:
|
|
Sebastian Offermann, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| Oldenburg, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Determining Minimal Testsets for Reversible Circuits Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Hongyan Zhang, Stefan Frehse, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
10th IEEE Africon |
Referenz:
|
| Livingstone, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» VisSAT: Visualization of SAT Solver Internals for Computer Aided Hardware Verification
|
|
|
|
Autor:
|
|
Robert Wille, André Sülflow, Rolf Drechsler |
| Konferenz: |
|
International Conference on Modeling, Simulation and Visualization Methods (MSV) |
Referenz:
|
| pp. 36-39, Las Vegas, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» ATPG for Reversible Circuits Using Simulation,
Boolean Satisfiability, and Pseudo Boolean
Optimization
|
|
|
|
Autor:
|
|
Robert Wille, Hongyan Zhang, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| pp. 120-125, Chennai, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Encoding OCL Data Types for SAT-based Verification of UML/OCL Models
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
5th International Conference on Tests & Proofs (TAP) |
Referenz:
|
| pp. 152-170, Zurich, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Automatic Property Generation for the Formal Verification of Bus Bridges
|
|
|
|
Autor:
|
|
Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 417-422, Cottbus, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» TLM Protocol Compliance Checking at the Electronic System Level
|
|
|
|
Autor:
|
|
Mohamed Bawadekji, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 435-440, Cottbus, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Designing a RISC CPU in Reversible Logic
|
|
|
|
Autor:
|
|
Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler |
| Konferenz: |
|
41st International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 170-175, Tuusula, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits
|
|
|
|
Autor:
|
|
Rolf Drechsler, Robert Wille |
| Konferenz: |
|
41st International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 78-85, Tuusula, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Simulation-based Equivalence Checking between SystemC Models at different Levels of Abstraction
|
|
|
|
Autor:
|
|
Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 223-228, Lausanne, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Verifying Dynamic Aspects of UML Models
|
|
|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1077-1082, Grenoble, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Determining the Minimal Number of Lines for Large Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Oliver Keszöcze, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1204—1207, Grenoble, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1291-1296, Grenoble, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Automatic Fault Localization for Programmable Logic Controllers
|
|
|
|
Autor:
|
|
Andre Sülflow, Rolf Drechsler |
| Konferenz: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT) |
Referenz:
|
| pp. 247-256, Braunschweig, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Robust Algorithms for High Quality Test Pattern Generation Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
International Test Conference (ITC) |
Referenz:
|
| pp. 1-10, Austin, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Polynomial Datapath Optimization using Constraint Solving and Formal Modelling
|
|
|
|
Autor:
|
|
Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler |
| Konferenz: |
|
IEEE/ACM International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| San Jose, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» SyReC: A Programming Language for Synthesis of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Sebastian Offermann, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 184-189, Southampton, 2010
Received Best Paper Award
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Proving Transaction and System-level Properties of Untimed SystemC TLM Designs
|
|
|
|
Autor:
|
|
Daniel Große, Hoang M. Le, Rolf Drechsler |
| Konferenz: |
|
International Conference on
Formal Methods and Models for Codesign (MEMOCODE) |
Referenz:
|
| pp. 113-122, Grenoble, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» RobuCheck: A Robustness Checker for Digital Circuits
|
|
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Autor:
|
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Stefan Frehse, Görschwin Fey, Andre Sülflow and Rolf Drechsler
|
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 226-231, Lille, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reducing the Number of Lines in Reversible Circuits
|
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Autor:
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|
Robert Wille, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| pp. 647-652, Anaheim, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Synthesizing Multiplier in Reversible Logic
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Autor:
|
|
Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 335-340, Vienna, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Window Optimization of Reversible and Quantum Circuits
|
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Autor:
|
|
Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 431-435, Vienna, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» A Better-Than-Worst-Case Robustness Measure
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Autor:
|
|
Stefan Frehse, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 78-83, Vienna, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Enhancing Debugging of Multiple Missing Control Errors in Reversible Logic
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|
Autor:
|
|
Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler
|
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 465-470, Rhode Island, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Improving CNF Representations in SAT-based ATPG for Industrial Circuits using BDDs
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|
Autor:
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|
Daniel Tille, Stephan Eggersglüß, René Krenz-Bååth, Juergen Schloeffel, Rolf Drechsler |
| Konferenz: |
|
15th IEEE European Test Symposium (ETS) |
Referenz:
|
| pp. 176-181, Prag, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions
|
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Autor:
|
|
Alexander Finder, Rolf Drechsler |
| Konferenz: |
|
40th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 150-155, Barcelona, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Efficient Simulation-based Debugging of Reversible Logic
|
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|
|
Autor:
|
|
Stefan Frehse, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
40th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 156-161, Barcelona, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reducing Reversible Circuit Cost by Adding Lines
|
|
|
|
Autor:
|
|
D. Michael Miller, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
40th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 217-222, Barcelona, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Efficient Test Generation with Maximal Crosstalk-Induced Noise using Unconstrained Aggressor Excitation
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS) |
Referenz:
|
| pp. 649-652, Paris, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Using QBF to Increase Accuracy of SAT-Based Debugging
|
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|
|
Autor:
|
|
Andre Sülflow, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS) |
Referenz:
|
| pp.641-644, Paris, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Verifying UML/OCL Models Using Boolean Satisfiability
|
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|
|
Autor:
|
|
Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1341-1344, Dresden, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Timing Arc Based Logic Analysis for False Noise Reduction
|
|
|
|
Autor:
|
|
Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler |
| Konferenz: |
|
IEEE/ACM International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| pp. 225-230, San Jose, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Anwendungsbezogene Analyse der Robustheit von Digitalen Schaltungen
|
|
|
|
Autor:
|
|
Andre Sülflow, Stefan Frehse, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) |
Referenz:
|
| pp. 45-52, Stuttgart, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Structural Heuristics for SAT-based ATPG
|
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|
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Autor:
|
|
Daniel Tille, Stephan Eggersglüß, Hoang M. Le, Rolf Drechsler |
| Konferenz: |
|
17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2009) |
Referenz:
|
| pp. 77-82, Florianópolis, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Speeding up SAT-based ATPG using Dynamic Clause Activation
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
| Konferenz: |
|
18th Asian Test Symposium (ATS'09) |
Referenz:
|
| pp. 177-182, Taichung, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Automatic Debugging of System-on-a-Chip Designs
|
|
|
|
Autor:
|
|
Frank Rogin, Rolf Drechsler, Steffen Rülke |
| Konferenz: |
|
IEEE International SOC Conference (SOCC) |
Referenz:
|
| Belfast, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» SMT-based Stimuli Generation in the SystemC Verification Library
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 1-6, Sophia Antipolis, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Robustness Check for Multiple Faults using Formal Techniques
|
|
|
|
Autor:
|
|
Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 85-90, Patras, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» BDD-based Synthesis of Reversible Logic for Large Functions
|
|
|
|
Autor:
|
|
Robert Wille, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| pp. 270-275, San Francisco, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Computing Bounds for Fault Tolerance using Formal Techniques
|
|
|
|
Autor:
|
|
Görschwin Fey, Andre Sülflow, Rolf Drechsler |
| Konferenz: |
|
Design Automation Conference (DAC) |
Referenz:
|
| pp. 190-195, San Francisco, USA, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» WoLFram - A Word Level Framework for Formal Verification
|
|
|
|
Autor:
|
|
Andre Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
IEEE/IFIP International Symposium on Rapid System Prototyping (RSP) |
Referenz:
|
| pp. 11-17, Paris, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» A Fast Untestability Proof for SAT-based ATPG
|
|
|
|
Autor:
|
|
Daniel Tille, Rolf Drechsler |
| Konferenz: |
|
12th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems |
Referenz:
|
| pp. 38-43, Liberec, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Increasing Robustness of SAT-based Delay Test Generation using Efficient Dynamic Learning Techniques
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
14th IEEE European Test Symposium (ETS) |
Referenz:
|
| pp. 81-86, Sevilla, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Contradictory Antecedent Debugging in Bounded Model Checking
|
|
|
|
Autor:
|
|
Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
|
| pp. 173-176, Boston, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Evaluation of Cardinality Constraints on SMT-based Debugging
|
|
|
|
Autor:
|
|
Andre Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
39th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 298-303, Naha, Okinawa, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Equivalence Checking of Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler |
| Konferenz: |
|
39th International Symposium on Multiple-Valued Logic (ISMVL) |
Referenz:
|
| pp. 324-330, Naha, Okinawa, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Approximate BDD Minimization by Weighted A*
|
|
|
|
Autor:
|
|
Rüdiger Ebendt, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'09) |
Referenz:
|
| Taipei, 2009
| Hyperlink:
|
| [Link zur Konferenz]
|
» Overcoming Limitations of the SystemC Data Introspection
|
|
|
|
Autor:
|
|
Christian Genz, Rolf Drechsler |
| Konferenz: |
|
Design Automation and Test in Europe (DATE)
|
Referenz:
|
| pp. 590-593, Nice, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Property Analysis and Design Understanding
|
|
|
|
Autor:
|
|
Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE)
|
Referenz:
|
| pp. 1246-1249, Nice, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Debugging of Toffoli Networks
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
|
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1284-1289, Nice, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Increasing the Accuracy of SAT-based Debugging
|
|
|
|
Autor:
|
|
Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1326-1332, Nice, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Reversible Logic Synthesis with Output Permutation
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
22nd International Conference on VLSI Design |
Referenz:
|
| pp. 189-194, New Delhi, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Formaler Nachweis der Fehlertoleranz von Schaltkreisen
|
|
|
|
Autor:
|
|
Görschwin Fey, Andre Sülflow, Stefan Frehse, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
|
GMM/GI/ITG-Fachtagung: Zuverlässigkeit und Entwurf (ZuE 2008) |
Referenz:
|
| pp. 75-82, Ingolstadt, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Verification of PLC Programs using Formal Proof Techniques
|
|
|
|
Autor:
|
|
Andre Sülflow, Rolf Drechsler |
| Konferenz: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008) |
Referenz:
|
| pp. 43-50, Budapest, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Efficient Formal Verification of Track Vacancy Detection Sections
|
|
|
|
Autor:
|
|
Sebastian Kinder und Rolf Drechsler |
| Konferenz: |
|
Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008)
|
Referenz:
|
| pp. 233-240, Budapest, 2008
| Hyperlink:
|
| [Link zur Konferenz]
|
» Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking
|
|
|
|
Autor:
|
|
Robert Wille, Görschwin Fey, Marc Messing, Gerhard
Angst, Lothar Linhard, Rolf Drechsler |
| Konferenz: |
|
Euromicro Conference on Digital System Design (DSD) |
Referenz:
|
| pp. 542-549, Parma, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Contradiction Analysis for Constraint-based Random Simulation
|
|
|
|
Autor:
|
|
Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler |
| Konferenz: |
|
Forum on specification & Design Languages (FDL) |
Referenz:
|
| pp. 130-135, Stuttgart, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler |
| Konferenz: |
|
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Referenz:
|
| pp. 411-416, Montpellier, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» RevLib: An Online Resource for
Reversible Functions and Reversible Circuits
|
|
|
|
Autor:
|
|
Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Referenz:
|
| pp. 220-225, Dallas, 2008
RevLib is available at www.revlib.org
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Exact Synthesis of Elementary Quantum Gate
Circuits for Reversible Functions with Don’t Cares
|
|
|
|
Autor:
|
|
Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| Konferenz: |
|
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Referenz:
|
| pp. 214-219, Dallas, 2008
Received IEEE Young Researcher Award
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» On the Influence of Boolean Encodings in SAT-based ATPG for Path Delay Faults
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Referenz:
|
| pp. 94-99, Dallas, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Using Unsatisfiable Cores to Debug Multiple Design Errors
|
|
|
|
Autor:
|
|
Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
| Konferenz: |
|
IEEE Great Lakes Symposium on VLSI (GLSVLSI'08) |
Referenz:
|
| pp. 77-82, Orlando, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Process Variations Aware Robust on-Chip Bus Architecture Synthesis for MPSoCs
|
|
|
|
Autor:
|
|
Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'08) |
Referenz:
|
| Seattle, 2008
| Hyperlink:
|
| [Link zur Konferenz]
|
» A Basis for Formal Robustness Checking
|
|
|
|
Autor:
|
|
Görschwin Fey, Rolf Drechsler
|
| Konferenz: |
|
International Symposium on Quality of Electronic Design (ISQED) |
Referenz:
|
| San Jose, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Adaptive Branch and Bound using SAT to Estimate False Crosstalk
|
|
|
|
Autor:
|
|
Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler
|
| Konferenz: |
|
International Symposium on Quality of Electronic Design (ISQED) |
Referenz:
|
| San Jose, 2008
| Hyperlink:
|
| [Link zur Konferenz]
|
» Automatic Generation of Complex Properties for Hardware Designs
|
|
|
|
Autor:
|
|
Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler Steffen Rülke |
| Konferenz: |
|
Design, Automation, and Test in Europe (DATE) |
Referenz:
|
| Munich, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs
|
|
|
|
Autor:
|
|
Sujan Pandey, Rolf Drechsler |
| Konferenz: |
|
Design, Automation, and Test in Europe (DATE) |
Referenz:
|
| Munich, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Robust On-Chip Bus architecture Synthesis for MPSoCs Under Random Tasks Arrival
|
|
|
|
Autor:
|
| |
