|
Home « Team « Publikationen
» Publikationen von
Stephan Eggersglüß
|
 |
BÜCHER |
 |
» High Quality Test Pattern Generation and Boolean Satisfiability
[Lesen Sie hier mehr!]
|
 |
|
Verlag: |
|
Springer |
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Format: |
|
Hardcover |
Erscheinungsjahr:
|
|
2012
|
|
» Test Pattern Generation using Boolean Proof Engines
[Lesen Sie hier mehr!]
|
 |
|
Verlag: |
|
Springer |
Autor:
|
|
Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille |
| Format: |
|
Hardcover |
Erscheinungsjahr:
|
|
2009
|
|
|
BUCHBEITRÄGE |
|
| » Robuste Erfüllbarkeitsalgorithmen für die Generierung hochwertiger Testmuster für digitale Schaltungen |
|
Autor:
| Stephan Eggersglüß
|
| Herausgeber: | S. Hölldobler et al. |
| Buchtitel: | Ausgezeichnete Informatikdissertationen 2010 |
| Verlag: | GI |
| Seiten: | 81-90 |
| Erscheinungsjahr: | 2011 |
| Format: | Paperback |
| » SWORD: A SAT like Prover Using Word Level Information |
|
Autor:
| Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
|
| Herausgeber: | Ricardo Reis, Vincent Mooney, Paul Hasler |
| Buchtitel: | VLSI-SoC: Advanced Topics on Systems on a Chip:
A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip |
| Verlag: | Springer |
| Seiten: | 175-192 |
| Erscheinungsjahr: | 2009 |
| Format: | Hardcover |
|
|
ZEITSCHRIFTEN |
|
» A Highly Fault-Efficient SAT-Based ATPG Flow
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Design & Test of Computers |
| Details: |
|
Volume 29, Issue 4 (July/August), pp. 63-70
|
Jahr:
|
|
2012
|
|
» Efficient Data Structures and Methodologies for SAT-based ATPG providing High Fault Coverage in Industrial Application
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 30, Number 9, pp. 1411-1415,
DOI: 10.1109/TCAD.2011.2152450 |
Jahr:
|
|
2011
|
|
» Incremental Solving Techniques for SAT-based ATPG
[Link zur Zeitschriften-Homepage]
|
|
|
|
|
|
Autor:
|
|
Daniel Tille, Stephan Eggersglüß, Rolf Drechsler |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 29, Number 7, pp. 1125-1130, July |
Jahr:
|
|
2010
|
|
» MONSOON: SAT-based ATPG for Path Delay Faults Using Multiple-Valued Logics
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Rolf Drechsler |
| Zeitschrift: |
|
Journal of Electronic Testing: Theory and Applications |
| Details: |
|
Volume 26, Number 3 / June, pp. 307-322
Pdf download (Preliminary Version)
The final publication is available at www.springerlink.com |
Jahr:
|
|
2010
|
|
» Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
[Link zur Zeitschriften-Homepage]
|
 |
|
|
|
|
Autor:
|
|
Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille |
| Zeitschrift: |
|
it - information technology |
| Details: |
|
Volume 51, Number 2, pp. 102-111
Pdf download |
Jahr:
|
|
2009
|
|
» On Acceleration of SAT-based ATPG for Industrial Designs
[Link zur Zeitschriften-Homepage]
|
|
|
|
|
|
Autor:
|
|
Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Daniel Tille |
| Zeitschrift: |
|
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| Details: |
|
Volume 27, Number 7, pp. 1329-1333, July |
Jahr:
|
|
2008
|
|
|
KONFERENZEN |
|
» Improved SAT-based ATPG: More Constraints, Better Compaction
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Robert Wille, Rolf Drechsler |
| Konferenz: |
|
IEEE/ACM International Conference on Computer-Aided Design (ICCAD) |
Referenz:
|
| San Jose, USA, 2013
| Hyperlink:
|
| [Link zur Konferenz]
|
» Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Mahmut Yilmaz, Krishnendu Chakrabarty |
| Konferenz: |
|
21st IEEE Asian Test Symposium (ATS) |
Referenz:
|
| pp. 290-295, Niigata, Japan, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» A New SAT-based ATPG for Generating Highly Compacted Test Sets
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler |
| Konferenz: |
|
15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
|
| pp. 230-235, Tallinn, Estonia, 2012
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
Design, Automation and Test in Europe (DATE) |
Referenz:
|
| pp. 1291-1296, Grenoble, 2011
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Robust Algorithms for High Quality Test Pattern Generation Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
International Test Conference (ITC) |
Referenz:
|
| pp. 1-10, Austin, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Improving CNF Representations in SAT-based ATPG for Industrial Circuits using BDDs
|
|
|
|
Autor:
|
|
Daniel Tille, Stephan Eggersglüß, René Krenz-Bååth, Juergen Schloeffel, Rolf Drechsler |
| Konferenz: |
|
15th IEEE European Test Symposium (ETS) |
Referenz:
|
| pp. 176-181, Prag, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Efficient Test Generation with Maximal Crosstalk-Induced Noise using Unconstrained Aggressor Excitation
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS) |
Referenz:
|
| pp. 649-652, Paris, 2010
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Timing Arc Based Logic Analysis for False Noise Reduction
|
|
|
|
Autor:
|
|
Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler |
| Konferenz: |
|
IEEE/ACM International Conference on Computer Aided Design (ICCAD) |
Referenz:
|
| pp. 225-230, San Jose, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Structural Heuristics for SAT-based ATPG
|
|
|
|
Autor:
|
|
Daniel Tille, Stephan Eggersglüß, Hoang M. Le, Rolf Drechsler |
| Konferenz: |
|
17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2009) |
Referenz:
|
| pp. 77-82, Florianópolis, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Speeding up SAT-based ATPG using Dynamic Clause Activation
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
| Konferenz: |
|
18th Asian Test Symposium (ATS'09) |
Referenz:
|
| pp. 177-182, Taichung, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Increasing Robustness of SAT-based Delay Test Generation using Efficient Dynamic Learning Techniques
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
14th IEEE European Test Symposium (ETS) |
Referenz:
|
| pp. 81-86, Sevilla, 2009
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» On the Influence of Boolean Encodings in SAT-based ATPG for Path Delay Faults
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08) |
Referenz:
|
| pp. 94-99, Dallas, 2008
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» SWORD: A SAT like Prover Using Word Level Information
|
|
|
|
Autor:
|
|
Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC) |
Referenz:
|
| pp. 88-93, Atlanta, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Improving Test Pattern Compactness in SAT-based ATPG
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Konferenz: |
|
16th Asian Test Symposium (ATS’07) |
Referenz:
|
| pp. 445-450, Beijing, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel |
| Konferenz: |
|
Fifth ACM-IEEE International Conference on
Formal Methods and Models for Codesign (MEMOCODE'2007) |
Referenz:
|
| pp. 181-187, Nice, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» Experimental Studies on SAT-based ATPG for Gate Delay Faults
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
| Konferenz: |
|
37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07) |
Referenz:
|
| Oslo, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
» SAT-based ATPG for Path Delay Faults in Sequential Circuits
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler |
| Konferenz: |
|
IEEE International Symposium on Circuits and Systems (ISCAS'07) |
Referenz:
|
| pp. 3671-3674, New Orleans, 2007
| Hyperlink:
|
| [Link zur Konferenz]
| PDF:
|
| [hier ansehen]
|
|
WORKSHOPS |
|
» Towards Increasing Test Compaction Abilities of SAT-based ATPG through Fault Detection Constraints
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Melanie Diepenbeck, Robert Wille, Rolf Drechsler |
| Workshop: |
|
IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12) |
Referenz:
|
| Niigata, Japan, 2012
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Formal Analysis Techniques: A Basis for High-Quality Designs
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Workshop: |
|
IEEE International Workshop on Processor Verification, Test and Debug |
Referenz:
|
| Invited Talk, Trondheim, 2011
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» On Timing-Aware ATPG using Pseudo-Boolean Optimization
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Workshop: |
|
IEEE European Test Symposium (ETS), Informal Digest of Papers |
Referenz:
|
| Trondheim, 2011
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Rolf Drechsler |
| Workshop: |
|
23. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2011 |
Referenz:
|
| Passau, 2011
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» A Two-Stage SAT-based ATPG Approach with Reduced Switching Activity
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler |
| Workshop: |
|
Second International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR) 2009 |
Referenz:
|
| Sevilla, Spain, 2009
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Robust Tests for Transition Faults with Long Propagation Paths Using Boolean Satisfiability
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
|
| Workshop: |
|
IEEE European Test Symposium (ETS), Informal Digest of Papers |
Referenz:
|
| Lago Maggiore, 2008
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» SAT-based ATPG for Path Delay Fault in Industrial Circuits
|
|
|
|
Autor:
|
|
Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel |
| Workshop: |
|
IEEE European Test Symposium (ETS), Informal Digest of Papers |
Referenz:
|
| Freiburg, 2007
| Hyperlink:
|
| [Link zum Workshop]
|
» Studies on Integrating SAT-based ATPG in an Industrial Environment
|
|
|
|
Autor:
|
|
Daniel Tille, Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
| Workshop: |
|
19. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
|
Referenz:
|
| Erlangen, 2007
| PDF:
|
| [hier ansehen]
| Hyperlink:
|
| [Link zum Workshop]
|
» Formal Verification on the Word Level using SAT-like Proof
Techniques
|
|
|
|
Autor:
|
|
Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler |
| Workshop: |
|
GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Referenz:
|
| pp. 165-173, Erlangen, 2007
| Hyperlink:
|
| [Link zum Workshop]
|
|
|
|
