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Home « Team « Publikationen
» Publikationen von
Sujan Pandey
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BÜCHER |
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BUCHBEITRÄGE |
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ZEITSCHRIFTEN |
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» Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic
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Autor:
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Sujan Pandey, Manfred Glesner |
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IEEE Transaction on Very Large Scale Integration (VLSI) Systems |
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Volume 15, Number 10, pp. 1111-1124, October |
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2007
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KONFERENZEN |
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» Process Variations Aware Robust on-Chip Bus Architecture Synthesis for MPSoCs
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Autor:
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Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner |
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IEEE International Symposium on Circuits and Systems (ISCAS'08) |
Referenz:
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| Seattle, 2008
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| [Link zur Konferenz]
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» Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs
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Autor:
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Sujan Pandey, Rolf Drechsler |
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Design, Automation, and Test in Europe (DATE) |
Referenz:
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| Munich, 2008
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| [Link zur Konferenz]
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» Robust On-Chip Bus architecture Synthesis for MPSoCs Under Random Tasks Arrival
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Autor:
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Sujan Pandey, Rolf Drechsler |
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13th Asia and South Pacific Design Automation Conference, (ASP-DAC 2008) |
Referenz:
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| Seoul, 2008
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| [Link zur Konferenz]
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» Co-Synthesis of Custom On-Chip Bus and Memory for
MPSoC Architectures
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Autor:
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Sujan Pandey, Christian Genz, Rolf Drechsler |
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IFIP International Conference on Very Large Scale Integration Systems and Systems on Chip (VLSI-SoC) |
Referenz:
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| pp. 304-307, Atlanta, 2007
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| [Link zur Konferenz]
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WORKSHOPS |
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» On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-Micron Interconnects.
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Autor:
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Tudor Murgan, Petru Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner |
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In Intl. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sept. 2007. |
Referenz:
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| pp. 242-254, Göteborg, Sweden
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| [Link zum Workshop]
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