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Universität Bremen Universität Bremen Fachbereich 3 Informatik
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» Publikationen von Sujan Pandey


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ZEITSCHRIFTEN

» Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic




Autor:

Sujan Pandey, Manfred Glesner
Zeitschrift:
IEEE Transaction on Very Large Scale Integration (VLSI) Systems
Details:
Volume 15, Number 10, pp. 1111-1124, October
Jahr:


2007





KONFERENZEN


» Process Variations Aware Robust on-Chip Bus Architecture Synthesis for MPSoCs




Autor:

Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner
Konferenz:
IEEE International Symposium on Circuits and Systems (ISCAS'08)
Referenz:

Seattle, 2008
Hyperlink:

[Link zur Konferenz]


» Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs




Autor:

Sujan Pandey, Rolf Drechsler
Konferenz:
Design, Automation, and Test in Europe (DATE)
Referenz:

Munich, 2008
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Robust On-Chip Bus architecture Synthesis for MPSoCs Under Random Tasks Arrival




Autor:

Sujan Pandey, Rolf Drechsler
Konferenz:
13th Asia and South Pacific Design Automation Conference, (ASP-DAC 2008)
Referenz:

Seoul, 2008
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


» Co-Synthesis of Custom On-Chip Bus and Memory for MPSoC Architectures




Autor:

Sujan Pandey, Christian Genz, Rolf Drechsler
Konferenz:
IFIP International Conference on Very Large Scale Integration Systems and Systems on Chip (VLSI-SoC)
Referenz:

pp. 304-307, Atlanta, 2007
Hyperlink:

[Link zur Konferenz]
PDF:

[hier ansehen]


WORKSHOPS


» On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-Micron Interconnects.




Autor:

Tudor Murgan, Petru Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner
Workshop:
In Intl. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sept. 2007.
Referenz:

pp. 242-254, Göteborg, Sweden
Hyperlink:

[Link zum Workshop]

















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