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Home « Team « Publikationen
» Publikationen von
Ulrich Kühne
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BÜCHER |
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» Advanced Automation in Formal Verification of Processors
[Lesen Sie hier mehr!]
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Verlag: |
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Shaker Verlag |
Autor:
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Ulrich Kühne |
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Gebunden |
Erscheinungsjahr:
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2009
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BUCHBEITRÄGE |
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ZEITSCHRIFTEN |
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» Parametric Verification and Test Coverage for Hybrid Automata using the Inverse Method
[Link zur Zeitschriften-Homepage]
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Autor:
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Laurent Fribourg, Ulrich Kühne |
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International Journal of Foundations of Computer Science (IJFCS) |
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Volume 24, Number 02 (February 2013), pp. 233-250 |
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2013
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» Towards Fully Automatic Synthesis of Embedded Software
[Link zur Zeitschriften-Homepage]
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Autor:
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Ulrich Kühne, Daniel Große, Rolf Drechsler |
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IEEE Embedded Systems Letters |
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Volume 2, Number 3, pp. 53-57, September |
Jahr:
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2010
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» Analyzing Functional Coverage in Bounded Model Checking
[Link zur Zeitschriften-Homepage]
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Autor:
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Daniel Große, Ulrich Kühne, Rolf Drechsler |
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IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
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Volume 27, Number 7, pp. 1305-1314, July |
Jahr:
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2008
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KONFERENZEN |
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» SyDe - a New Graduate School for
System Design in an Excellent Setting
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Autor:
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Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
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Informatics Europe (ECSS) |
Referenz:
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| Barcelona, 2012
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| [Link zur Konferenz]
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» Completeness-Driven Development
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Autor:
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Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille |
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International Conference on Graph Transformation |
Referenz:
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| pp. 38-50, Bremen, 2012
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Parametric Analysis of Hybrid Systems Using HyMITATOR (Tool Presentation)
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Autor:
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Étienne André, Ulrich Kühne |
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International Conference on Integrated Formal Methods (iFM)
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Referenz:
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| Pisa, Italy, 2012
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| [Link zur Konferenz]
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» IMITATOR 2.5: A Tool for Analyzing Robustness in Scheduling Problems (Tool Paper)
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Autor:
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Étienne André, Laurent Fribourg, Ulrich Kühne, Romain Soulat |
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International Symposium on Formal Methods (FM) |
Referenz:
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| Paris, France, 2012
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| [Link zur Konferenz]
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» Automatic Property Generation for the Formal Verification of Bus Bridges
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Autor:
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Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler |
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14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Referenz:
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| pp. 417-422, Cottbus, 2011
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Simulation-based Equivalence Checking between SystemC Models at different Levels of Abstraction
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Autor:
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Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler |
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Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
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| pp. 223-228, Lausanne, 2011
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Automated Formal Verification of Processors Based on Architectural Models
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Autor:
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Ulrich Kühne, Sven Beyer, Jörg Bormann, John Barstow |
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Formal Methods in Computer Aided Design (FMCAD) |
Referenz:
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| Lugano, Switzerland, 2010
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| [Link zur Konferenz]
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» Generating an Efficient Instruction Set Simulator from a Complete Property Suite
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Autor:
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Ulrich Kühne, Sven Beyer, Christian Pichler |
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IEEE/IFIP International Symposium on Rapid System Prototyping (RSP) |
Referenz:
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| pp. 109-115, Paris, 2009
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» WoLFram - A Word Level Framework for Formal Verification
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Autor:
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Andre Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler |
| Konferenz: |
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IEEE/IFIP International Symposium on Rapid System Prototyping (RSP) |
Referenz:
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| pp. 11-17, Paris, 2009
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Contradictory Antecedent Debugging in Bounded Model Checking
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Autor:
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Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
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Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
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| pp. 173-176, Boston, 2009
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Property Analysis and Design Understanding
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Autor:
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Ulrich Kühne, Daniel Große, Rolf Drechsler |
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Design, Automation and Test in Europe (DATE)
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Referenz:
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| pp. 1246-1249, Nice, 2009
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Increasing the Accuracy of SAT-based Debugging
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Autor:
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Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| pp. 1326-1332, Nice, 2009
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Formaler Nachweis der Fehlertoleranz von Schaltkreisen
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Autor:
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Görschwin Fey, Andre Sülflow, Stefan Frehse, Ulrich Kühne, Rolf Drechsler |
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GMM/GI/ITG-Fachtagung: Zuverlässigkeit und Entwurf (ZuE 2008) |
Referenz:
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| pp. 75-82, Ingolstadt, 2008
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
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Autor:
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Ulrich Kühne, Daniel Große, Rolf Drechsler |
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IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07) |
Referenz:
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| pp. 165-170, Porto Alegre, 2007
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» Estimating Functional Coverage in Bounded Model Checking
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Autor:
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Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Konferenz: |
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Design, Automation and Test in Europe (DATE) |
Referenz:
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| pp. 1176-1181, Nice, 2007
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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» HW/SW Co-Verification of Embedded Systems using Bounded Model Checking
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Autor:
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Daniel Große, Ulrich Kühne, Rolf Drechsler |
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Great Lakes Symposium on VLSI (GLSVLSI) |
Referenz:
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| pp. 43-48, Philadelphia, 2006
| Hyperlink:
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| [Link zur Konferenz]
| PDF:
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| [hier ansehen]
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WORKSHOPS |
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» Parametric Verification and Test Coverage for Hybrid Automata Using the Inverse Method
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Autor:
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Laurent Fribourg, Ulrich Kühne |
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5th Workshop on Reachability Problems (RP) |
Referenz:
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| Genua, 2011
| PDF:
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| [hier ansehen]
| Hyperlink:
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| [Link zum Workshop]
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» Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines
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Autor:
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Kim Grüttner, Andreas Herrholz, Ulrich Kühne, Daniel Große, Achim Rettberg, Wolfgang Nebel, Rolf Drechsler |
| Workshop: |
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SORT 2011: 2nd IEEE Workshop on Self-Organizing Real-Time Systems |
Referenz:
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| pp. 181-188, Newport Beach, 2011
| Hyperlink:
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| [Link zum Workshop]
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» Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction
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Autor:
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Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler |
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14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
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| pp. 269-278, Oldenburg, 2011
| Hyperlink:
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| [Link zum Workshop]
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» Towards Automatic Property Generation for the Formal Verification of Bus Bridges
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Autor:
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Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler |
| Workshop: |
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14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
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| Oldenburg, 2011
| Hyperlink:
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| [Link zum Workshop]
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» Increasing the Accuracy of SAT-based Debugging
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Autor:
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Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
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12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
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| pp. 47-56, Berlin, 2009
| PDF:
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| [hier ansehen]
| Hyperlink:
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| [Link zum Workshop]
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» Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow
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Autor:
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Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Workshop: |
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9th International Workshop on Microprocessor Test and Verification (MTV) |
Referenz:
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| pp. 88-93, Austin, Texas, 2008
| PDF:
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| [hier ansehen]
| Hyperlink:
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| [Link zum Workshop]
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» Computing Bounds for Fault Tolerance using Formal Techniques
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Autor:
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Andre Sülflow, Görschwin Fey, Stefan Frehse, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
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IEEE Workshop on Design for Reliability and Variability (DRV) |
Referenz:
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| Santa Clara, USA, 2008
| PDF:
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| [hier ansehen]
| Hyperlink:
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| [Link zum Workshop]
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» Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking
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Autor:
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Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
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11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen
zur Modellierung und Verifikation von Schaltungen und Systemen" |
Referenz:
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| pp. 169-178, Freiburg, 2008
| Hyperlink:
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| [Link zum Workshop]
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» Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits
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Autor:
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Andre Sülflow, Ulrich Kühne, Robert Wille, Daniel Große, Rolf Drechsler |
| Workshop: |
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IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07) |
Referenz:
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| pp. 31-36, Beijing, P.R.China, 2007
| PDF:
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| [hier ansehen]
| Hyperlink:
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| [Link zum Workshop]
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» Complete Formal Verification of Multi Core Embedded Systems using Bounded Model Checking
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Autor:
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Ulrich Kühne, Daniel Große, Rolf Drechsler |
| Workshop: |
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Fifth IEEE Dallas Circuits and Systems Workshop |
Referenz:
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| pp. 147-150, Dallas, 2006
| Hyperlink:
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| [Link zum Workshop]
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» Finding Compact BDDs Using Genetic Programming
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Autor:
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Ulrich Kühne, Nicole Drechsler |
| Workshop: |
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3rd European Workshop on Evolutionary Computation in Hardware Optimisation (EvoHOT)
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Referenz:
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| LNCS 3907, pp. 308-319, Budapest, 2006
| PDF:
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| [hier ansehen]
| Hyperlink:
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| [Link zum Workshop]
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» HW/SW Co-Verification of a RISC CPU using Bounded Model Checking
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Autor:
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Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
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6th International Workshop on Microprocessor Test and Verification (MTV'05) |
Referenz:
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| pp. 133-137, Austin, 2005
| PDF:
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| [hier ansehen]
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» Formale Verifikation des Befehlssatzes eines in SystemC modellierten Mikroprozessors
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Autor:
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Daniel Große, Ulrich Kühne, Rolf Drechsler |
| Workshop: |
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Entwurfsmethoden für Nanometer VLSI Design |
Referenz:
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| pp. 308-312, Bonn, 2005
| PDF:
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| [hier ansehen]
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» Modellierung eines Mikroprozessors in SystemC
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Autor:
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Daniel Große, Ulrich Kühne, Christian Genz, Frank Schmiedle, Bernd Becker, Rolf Drechsler, Paul Molitor |
| Workshop: |
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GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen |
Referenz:
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| München, 2005
| PDF:
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| [hier ansehen]
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