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» Time-stamps for Hardware Simulation Models Accurate Time-back Annotation




Autor:

Rehab Massoud, Jannis Stoppe, Karthik Maddikunta, Rolf Drechsler
Workshop:
5th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Referenz:

Dresden, Germany, 2018
Hyperlink:

[Link zum Workshop]



» A Codeword-based Compaction Technique for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks




Autor:

Sebastian Huhn, Marcel Merten, Stephan Eggersglüß and Rolf Drechsler
Workshop:
30. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2018)
Referenz:

Freiburg (Breisgau), Germany, 2018
Hyperlink:

[Link zum Workshop]



» A Lightweight Method for Transient Test Power Pattern Analysis for Pattern Selection




Autor:

Harshad Dhotre, Stephan Eggersglüß
Workshop:
29. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2017)
Referenz:

Lübeck, Germany, 2017
Hyperlink:

[Link zum Workshop]



» Making Waveforms Great Again




Autor:

Jannis Stoppe and Rolf Drechsler
Workshop:
4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Referenz:

Lausanne, Switzerland, 2017
Hyperlink:

[Link zum Workshop]



» A Human-Centered Approach to Routing for Digital Microfluidic Biochips




Autor:

Oliver Keszöcze, Andre Pols and Rolf Drechsler
Workshop:
4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Referenz:

Lausanne, Switzerland, 2017
Hyperlink:

[Link zum Workshop]



» Verilog2GEXF - Dynamic Large Scale Circuit Visualization




Autor:

Kenneth Schmitz, Jannis Stoppe, Rolf Drechsler
Workshop:
4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Referenz:

Lausanne, Switzerland, 2017
Hyperlink:

[Link zum Workshop]



» Computing Exact Fault Candidates Incrementally




Autor:

Heinz Riener, Görschwin Fey
Workshop:
4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Referenz:

Lausanne, Switzerland, 2017
Hyperlink:

[Link zum Workshop]



» Mining Latency Guarantees for RT-level Designs




Autor:

Jan Malburg, Heinz Riener, Görschwin Fey
Workshop:
4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Referenz:

Lausanne, Switzerland, 2017
Hyperlink:

[Link zum Workshop]



» Revisiting Symbolic Software-implemented Fault Injection




Autor:

Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
Workshop:
2nd International Workshop on Resiliency in Embedded Electronic Systems (REES)
Referenz:

Lausanne, Switzerland, 2017
Hyperlink:

[Link zum Workshop]



» Der Einfluss von Zellformen auf das Routing von Digital Microfluidic Biochips




Autor:

Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Workshop:
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Referenz:

Bremen, Germany, 2017
Hyperlink:

[Link zum Workshop]



» Exakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate Computing




Autor:

Saman Fröhlich, Daniel Große, Rolf Drechsler
Workshop:
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Referenz:

Bremen, Germany, 2017
Hyperlink:

[Link zum Workshop]



» Counterexample-Guided EF Synthesis of Boolean Functions




Autor:

Heinz Riener, Rüdiger Ehlers, Görschwin Fey
Workshop:
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Referenz:

Bremen, Germany, 2017
Hyperlink:

[Link zum Workshop]



» Using Lightweight Containers in Hardware/Software Co-Design for Security




Autor:

Daniel Große, Kenneth Schmitz, Rolf Drechsler
Workshop:
Workshop on Computer-Aided Design and Implementation for Cryptography and Security (CADICS)
Referenz:

Austin, USA, 2016
Hyperlink:

[Link zum Workshop]



» Integrating an SMT-based Model Finder into USE




Autor:

Nils Przigoda, Frank Hilken, Judith Peters, Robert Wille, Martin Gogolla, Rolf Drechsler
Workshop:
Workshop on Model-Driven Engineering, Verification, and Validation (MoDeVVa)
Referenz:

Saint-Malo, France, 2016
Hyperlink:

[Link zum Workshop]



» On the computational complexity of error metrics in approximate computing




Autor:

Oliver Keszöcze, Mathias Soeken, Rolf Drechsler
Workshop:
International Workshop on Boolean Problems
Referenz:

Freiberg, Germany, 2016
Hyperlink:

[Link zum Workshop]



» SystemCDG - AI Based Coverage Driven Stimuli Generation for SystemC




Autor:

Jannis Stoppe, Arved Friedemann, Rolf Drechsler
Workshop:
International Workshop on Logic & Synthesis (IWLS)
Referenz:

Austin, TX, USA, 2016
Hyperlink:

[Link zum Workshop]



» Counterexample-Guided Diagnosis




Autor:

Heinz Riener, Görschwin Fey
Workshop:
International Verification and Security Workshop (IVSW'16)
Referenz:

Sant Feliu de Guixols, Catalunya, Spain, 2016
Hyperlink:

[Link zum Workshop]
PDF:

[hier ansehen]



» Generating good properties from a small number of use cases




Autor:

Jan Malburg, Tino Flenker, Görschwin Fey
Workshop:
International Verification and Security Workshop (IVSW'16)
Referenz:

Sant Feliu de Guixols, Catalunya, Spain, 2016
Hyperlink:

[Link zum Workshop]



» SMT-Based CPS Parameter Synthesis




Autor:

Heinz Riener, Robert Könighofer, Görschwin Fey, Roderick Bloem
Workshop:
Applied Verification for Continuous and Hybrid Systems (ARCH@CPSWeek'16)
Referenz:

pp. 126-133, Vienna, Austria, 2016
Hyperlink:

[Link zum Workshop]
PDF:

[hier ansehen]



» Extraktion von Frame Conditions aus Operation Contracts




Autor:

Philipp Niemann, Frank Hilken, Martin Gogolla, Robert Wille
Workshop:
Software Engineering (SE)
Referenz:

Vienna, Austria, 2016
Hyperlink:

[Link zum Workshop]



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