SCA verification tools & topics


We present the multiplier generator GenMul, which outputs multiplier circuits in Verilog. The input size of a multiplier and each multiplier stage can be configured with GenMul. In addition, GenMul is open source under MIT-license to ease for adding new architectures. Overall, this allows to challenge formal methods as shown by experiments which compare recent verification approaches.

How to get GenMul

GenMul Web Generation

Multiplier size:

Multiplicand size:

Partial product generator:

Partial Product Accumulator:

Final stage adder:

Press the generate button to start the generation.
Attention: In case of large multiplier/multiplicand sizes your browser may runs for several minutes.

Created by
Group of
Computer Architecture, University of Bremen
University of Bremen
Institute for
Complex Systems, JKU Linz
Johannes Kepler University Linz

supported by SyDe