What is this all about
This webpage provides verification solutions targeting SystemC-based Virtual Prototypes (VPs). In addition, methods are presented where theses VPs are leveraged to solve more general verification problems, enabled via the abstraction of Transaction Level Modeling (TLM).
In the menu on the right you can select information about our developments in:
- RISC-V related approaches (RISC-V)
- RISC-V SystemC VP (RISC-V VP)
- Constraint-based random simulation (CRAVE)
- TLM property checking (SCIVER)
- SystemC intermediate verification language and symbolic simulation (SISSI)
Daniel Große, JKU Linz, Austria & DFKI Bremen, Germany
Vladimir Herdt, DFKI Bremen, Germany
Rolf Drechsler, University of Bremen & DFKI Bremen, Germany
