What is this all about
This webpage provides verification solutions for SystemC. In particular, SystemC Transaction Level Modeling (TLM) designs and virtual prototypes are targeted.
In the menu on the right you can select information about our approaches for:
- RISCV-based SystemC virtual prototype (RISCV VP)
- constraint-based random simulation (CRAVE)
- TLM property checking (SCIVER)
- SystemC intermediate verification language and symbolic simulation (SISSI)
Daniel Große and Rolf Drechsler
University of Bremen and DFKI
