RISC-V related approaches

Either our approaches target SystemC-based Virtual Prototypes (VPs) directly, or they leverage VPs to solve more general verification problems. In the following we provide a categorization of our RISC-V related approaches:

VP Model

• NEW: RISC-V based virtual prototype: An extensible and configurable platform for the system-level (JSA 2020)
• Extensible and configurable RISC-V based virtual prototype (FDL 2018) (Bibtex entry)

VP Model Verification

• NEW and to appear: Early verification of ISA extension specifications using deep reinforcement learning (GLSVLSI 2020) (Bibtex entry)
• Verifying instruction set simulators using coverage-guided fuzzing (DATE 2019) (Bibtex entry)

Cross-Level Verification

• NEW and to appear: Efficient cross-level testing for processor verification: A RISC-V case-study (FDL 2020) (Bibtex entry)

Software and Firmware Verification

• NEW: RVX - a tool for concolic testing of embedded binaries targeting RISC-V platforms (ATVA 2020) (Bibtex entry)
• NEW: Verification of embedded binaries using coverage-guided fuzzing with SystemC-based virtual prototypes (GLSVLSI 2020) (Bibtex entry)
• Systematic RISC-V based firmware design (FDL 2019) (Bibtex entry)
• Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study (DAC 2019) (Bibtex entry)

Compliance Testing

• NEW: Closing the RISC-V compliance gap: Looking from the negative testing side (DAC 2020) (Bibtex entry)
• NEW: Towards specification and testing of RISC-V ISA compliance (DATE 2020) (Bibtex entry)

Security

• NEW: Dynamic information flow tracking for embedded binaries using SystemC-based virtual prototypes (DAC 2020) (Bibtex entry)

VP Performance

• NEW: Fast and accurate performance evaluation for RISC-V using virtual prototypes (DATE 2020) (Bibtex entry)

For any questions or comments please contact us at riscv@systemc-verification.org