ESL verification tools & topics

RISC-V based Virtual Prototype

Our RISC-V based Virtual Prototype (VP) integrates a RISC-V RV32IM core, a PLIC-based interrupt controller and an essential set of peripherals together with SW debug capabilities. The VP is designed as extensible and configurable platform with a generic bus system and implemented in standard-compliant SystemC and TLM-2.0.

NEW: Our RISC-V VP is available at GitHub!

Note that we have FreeRTOS running on our RISC-V VP.

NEW: FreeRTOS for our RISC-V VP is available at GitHub!

Created by
Group of
Computer Architecture, University of Bremen
University of Bremen

supported by BMBF Project CONFIRM Project CONVERS Project EffektiV Project SANITAS