SystemC Intermediate Verification Language and Symbolic Simulator SISSI
NEW: the Language Reference Manual for the IVL is available here
SystemC Intermediate Verification Language (IVL) enables the independent development of front-ends and back-ends for SystemC formal verification. It is compact, intuitive, readable but expressive enough to capture the behavior of SystemC designs.
SISSI (SystemC IVL Symbolic Simulator) is a back-end for the IVL. It combines symbolic execution (full input coverage) and Partial Order Reduction (efficient pruning of search space). SISSI is able to find assertion violations as well as general errors such as division by zero or memory access violation in a given IVL description.
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Documentation & References
For the technical background on the IVL and the symbolic simulator SISSI we refer to the following paper:
- NEW: Verifying SystemC using Intermediate Verification Language and Stateful Symbolic Simulation (TCAD 2018)
- Verifying SystemC using Stateful Symbolic Simulation (DAC 2015)
- Verifying SystemC using an Intermediate Verification Language and Symbolic Simulation (DAC 2013)
For recent advancements based on SISSI: