Mein Forschungsinteresse liegt in der Formalen Verifikation von Schaltkreisen.
Ziel der Formalen Verifikation ist es (anders als bei simulationsbasierten
Verfahren, deren Grenzen z.B. durch den Pentium Bug aufgezeigt wurden) die
Korrektheit von Schaltkreisen zu beweisen.
Vor allem untersuche ich genauer, wie Hochspracheninformationen im
Verifikationsprozess Gewinn bringend eingesetzt werden können.
Dabei spielt die Systembeschreibungssprache SystemC eine wichtige Rolle.
Formal Verification of Structurally Complex Multipliers
Verbessertes virtuelles Prototyping
Recent Findings in Boolean Techniques
Enhanced Virtual Prototyping: Featuring RISC-V Case Studies
Languages, Design Methods, and Tools for Electronic System Design - Selected Contributions from FDL 2018
Languages, Design Methods, and Tools for Electronic System Design - Selected Contributions from FDL 2017
Design Automation Techniques for Approximation Circuits
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Quality-Driven SystemC Design
EXplayN - Strategieoptimierung und Analyse ausgewählter Spielprobleme
SATRIX - Algorithmen für Boolesche Erfüllbarkeit
Toward System-Level Assertions for Heterogeneous Systems
Automatic Design of Microfluidic
Devices: An Overview of Platforms
and Corresponding Design Tasks
Extensible and Configurable RISC-V Based Virtual Prototype
Approximate Memory: Data Storage in the Context of Approximate Computing
Approximate Hardware Generation Using Formal Techniques
Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach
On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-Based Error Effect Simulation: A Case Study
Formal Verification of SystemC-based Cyber Components
Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis
SMT-based Stimuli Generation in the SystemC Verification Library
Debugging Contradictory Constraints in Constraint-based Random Simulation
SWORD: A SAT like Prover Using Word Level Information
Qualitätsorientierter Entwurfs- und Verifikationsablauf für digitale Systeme
Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques
Processor Verification
System-level validation using formal techniques
RevSCA-2.0: SCA-based Formal Verification of Non-trivial Multipliers using Reverse Engineering and Local Vanishing Removal
Towards RISC-V CSR Compliance Testing
Adaptive Simulation with Virtual Prototypes in an Open-Source RISC-V Evaluation Platform
ReCoFused partial reconfiguration for secure moving-target countermeasures on FPGAs
On the Impact of the Synchronization Constraint and Interconnections in Quantum-dot Cellular Automata
RISC-V based Virtual Prototype: An Extensible and Configurable Platform for the System-level
Placement & Routing for Tile-based Field-coupled Nanocomputing Circuits is NP-complete
Combining Sequentialization-based Verification of Multi-Threaded C Programs with Symbolic Partial Order Reduction
Security Validation of VP-based SoCs Using Dynamic Information Flow Tracking
Verifying SystemC using Intermediate Verification Language and Stateful Symbolic Simulation
Behaviour Driven Development for Hardware Design
metaSMT: Focus On Your Application And Not On Solver Integration
Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis
Automatic TLM Fault Localization for SystemC
Debugging Reversible Circuits
Towards Fully Automatic Synthesis of Embedded Software
Exact Synthesis of Elementary Quantum Gate Circuits
Exact Multiple Control Toffoli Network Synthesis with SAT Techniques
Analyzing Functional Coverage in Bounded Model Checking
BDD-based Verification of Scalable Designs
System Level Validation Using Formal Techniques
Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC
Heuristic Learning based on Genetic Programming