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Protocol Transducer Synthesis using Divide and Conquer Approach



Datum: 19.07.2007

Ort: MZH 8090


Vortragende(r): Prof. Masahiro Fujita (University of Tokyo)

Raumänderung (s.o.)




In IP based design, the designers try to reuse existing IPs as much as possible. Since currently available IPs use various communication protocols, protocol conversion is one of the most important topics in IP-based design.
We propose a method for automatic protocol transducer synthesis which is applicable to complex protocols. The main idea of our proposed method is protocol transducer synthesis with a divide and conquer approach. We demonstrate our method by synthesizing transducers which translate among the real and complicated protocols with advanced features such as non-blocking transactions and out-of-order transactions.

Masahiro Fujita received his Ph.D. from the University of Tokyo in 1985. He is a professor in VLSI Design and Education Center (VDEC) at the University of Tokyo. Prior to joining the University of Tokyo in 2000, he was director of CAD for VLSI in Fujitsu Laboratories of America for 6 years. He has done innovative works in the areas of digital design verification, synthesis, and testing. He has co-authored 7 books, and has over 100 publications. He has been given several research awards from Japanese scientific societies. His current research interests include synthesis and verification in higher level design stages, hardware/sfotware co-designs and also digital/analog co-designs.



Ansprechpartner(in) / Einladende(r):
Prof. Dr. Rolf Drechsler





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