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2 Vorträge | University of Tokyo

Datum: 19.04.2010

Ort: Cartesium Rotunde

Vortragende(r): Dr. Tetsuya Iizuka und Prof. Dr. Kunihiro Asada (University of Tokyo, Japan)

Achtung! Kolloquium ausser der Reihe!
Das Kolloquium beginnt bereits um 16 Uhr c.t. !

Buffer‐Ring‐Based All‐Digital On‐Chip Monitor for PMOS and NMOS Process Variability and Aging Effects

The improvement of VLSI process technologies
over the last twenty years enables the integration
of a large number of transistors on a single chip,
and significantly improves the circuit performance.
However, VLSI design and verification processes
have become more and more complex. Moreover,
a smaller feature sizes degrade the tolerance to
the PVT (Process, Voltage, and Temperature)
variabilities and the reliability concerns such as
Negative Bias Instability (NBTI) and Channel Hot
Carrier (CHC) have become of critical importance
to nanoscale transistors.
In this talk, we present an all‐digital process
variability and aging monitor which utilizes a
simple buffer ring with a pulse counter. Using the
proposed circuit in combination with a simple ring
oscillator which monitors its oscillation period, we
can calculate the rise and fall delay values and we
can monitor the variability of PMOS and NMOS
devices independently. The experimental results of
the circuit simulation on 65nm CMOS process
indicate the feasibility of the proposed monitoring
circuit. The proposed monitoring technique is
suitable not only for the on‐chip process variability
monitoring but also for the infield monitoring of
aging effects such as NBTI and CHC.
Self‐timed Circuits as Resilient LSIs for

The operation of synchronous circuits, as widely
used today, is becoming increasingly unstable caused
by PVT variation. The conventional margin‐based
design approach pays a large overhead to guarantee
the safe operation, especially for delay. Recently,
semi‐self‐timed approaches have been proposed to
mitigate these problems, where the circuits have an
error recovery mechanism along with delay‐fault
detection/prediction circuits such as a double
sampling of signals. These approaches, however, still
need a timing margin, in which the delay variation
should be confined.
The self‐timed circuits, with a completion‐detection
mechanism, are ideally delay‐fault free. The dual‐rail
logic, used in our research, is a promising candidate
to realize the mechanism, where the PVT variation
causes not the delay‐fault but the minimum
performance degradation. The dual‐rail logic has an
additional feature to detect permanent and
intermittent logic faults due to its redundancy. In
this talk two examples will be given; an experimental
self‐timed CPU resilient for PVT variation and a selftimed
FPGA, which is inheriting not only the delayfault
free feature but also a high throughput
performance realized by the extremely fine‐grain
pipeline architecture.

Ansprechpartner(in) / Einladende(r):
Prof. Dr. Rolf Drechsler
Prof. Dr. Görschwin Fey