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Design for Testability for Reversible Circuits

Datum: 21.09.2012
Uhrzeit: 11:15 Uhr

Ort: MZH 1090

Vortragende(r): Debesh Das (Computer Science and Engineering Department, Jadavpur University)

Logic synthesis with reversible circuits has received considerable interest in the light of advances recently made in quantum computation. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely, single missing-gate fault (SMGF), repeated-gate fault (RGF), partial missing-gate fault (PMGF), and multiple missing-gate fault (MMGF), have been found to be more suitable for modeling defects in quantum k-CNOT gates. The talk proposes Design for Testability techniques for the different fault models in the reversible circuits. We propose testable designs with universal test set to detect these faults in a reversible circuit.

Ansprechpartner(in) / Einladende(r):
Prof. Dr. Rolf Drechsler